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Code Issues Projects Releases Wiki Activity
6,041 Commits 7 Branches 121 Tags 500 MiB
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866 Commits

Author SHA1 Message Date
Thomas Harte
8c736a639a Eliminates unexpected bottleneck created by ACIA. 2019-11-09 15:00:12 -05:00
Thomas Harte
14e790746b Fixes return value when reading received data. 2019-11-02 21:25:00 -04:00
Thomas Harte
75e34b4215 Reacts to no acknowledgement. 2019-10-31 21:00:05 -04:00
Thomas Harte
a5bbf54a27 Adds the ability for the 68901 to decline an interrupt acknowledgement. 2019-10-31 19:57:36 -04:00
Thomas Harte
731dc350b4 Adds sometime real-time clocking for DMA. 2019-10-30 22:59:32 -04:00
Thomas Harte
635e18a50d Ensures the MFP requests and receives real-time clocking when needed. 2019-10-30 22:42:06 -04:00
Thomas Harte
4857ceb3eb Attempts to get a bit more systematic. 
Spotted that interrupt_enable_ isn't being used properly while doing so, hopefully that's now correct.
 2019-10-29 23:16:08 -04:00
Thomas Harte
1c154131f9 Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate. 2019-10-29 22:36:29 -04:00
Thomas Harte
fd02b6fc18 Corrects in-service test; adds pending clearing upon enabled clearing. 2019-10-28 22:51:00 -04:00
Thomas Harte
553f3b6d8b Properly conforms to GPIP input/output blending. 2019-10-28 22:37:11 -04:00
Thomas Harte
a5057e6540 Ensures that stop means stop. 2019-10-28 22:12:45 -04:00
Thomas Harte
aa52652027 Adds a const. 2019-10-28 21:21:35 -04:00
Thomas Harte
5f6711b72c Ensures interrupt changes are notified to the delegate. 2019-10-28 21:13:06 -04:00
Thomas Harte
de1bfb4e24 Stores and returns timer configuration. 2019-10-27 22:38:49 -04:00
Thomas Harte
0082dc4411 Improves logging. 2019-10-27 00:02:55 -04:00
Thomas Harte
22754683f8 Ensures timer divisor values don't go out of range, adds timer interrupts. 
I suspect further timer issues remain.
 2019-10-26 23:20:13 -04:00
Thomas Harte
e89be6249d Adds a logging prefix. 2019-10-26 22:38:56 -04:00
Thomas Harte
e96386f572 Takes another stab at MFP interrupt management. 2019-10-26 15:55:19 -04:00
Thomas Harte
a8d481a764 Writes to the pending register appear to be able to clear interrupts too. 2019-10-25 22:46:30 -04:00
Thomas Harte
872897029e Attempts a complete wiring of 68901 interrupts. 2019-10-25 22:36:01 -04:00
Thomas Harte
7a2de47f58 Corrects interrupt mask generation. 2019-10-24 22:37:32 -04:00
Thomas Harte
f2f98ed60c Attempts some part of interrupt decision making. 2019-10-24 22:33:42 -04:00
Thomas Harte
77f14fa638 Starts trying to make sense of interrupts. 2019-10-23 23:09:49 -04:00
Thomas Harte
f09a240e6c Gives myself more trace details. 2019-10-21 23:20:03 -04:00
Thomas Harte
e30ba58e0d Attempts to wire ACIA interrupt signals into the MFP. 2019-10-21 23:02:30 -04:00
Thomas Harte
7cb82fccc0 Attempts properly to maintain interrupt flag; adds delegate. 2019-10-21 22:40:38 -04:00
Thomas Harte
ed9a5b0430 Adds receipt interrupt. 2019-10-21 21:27:57 -04:00
Thomas Harte
8f59a73425 Corrects incoming data capture. 2019-10-21 20:18:52 -04:00
Thomas Harte
91223b9ec8 Sets default level to high. 2019-10-21 20:18:33 -04:00
Thomas Harte
83f5f0e2ad Begins trying to receive ACIA data. 2019-10-21 20:10:19 -04:00
Thomas Harte
cf37e9f5de Remove source control markers. 2019-10-20 23:40:51 -04:00
Thomas Harte
e4f7ead894 Merge branch 'AtariST' of github.com:TomHarte/CLK into AtariST 2019-10-20 23:40:01 -04:00
Thomas Harte
4134463094 The ACIA now receives bits. 2019-10-20 23:34:30 -04:00
Thomas Harte
83d73fb088 The keyboard now responds to a reset on its serial line. 2019-10-20 23:13:44 -04:00
Thomas Harte
cf07982a9b Ensures good serial line and ACIA behaviour. 
Next stop: having the intelligent keyboard react.
 2019-10-20 22:10:05 -04:00
Thomas Harte
2e86dada1d Ensures updates even when the event queue is empty. 2019-10-20 20:38:56 -04:00
Thomas Harte
696af5c3a6 Starts to transfer serial line decoding logic into the line itself. 2019-10-20 20:38:56 -04:00
Thomas Harte
f08b38d0ae Silences, temporarily. 2019-10-20 20:38:55 -04:00
Thomas Harte
9a8352282d Mostly but not quite fixes serial work. 2019-10-20 20:38:55 -04:00
Thomas Harte
3d03cce6b1 Starts working on the GPIP functionality block. 2019-10-20 20:38:55 -04:00
Thomas Harte
34075a7674 Attempts to tie an intelligent keyboard to the other end of its serial line. 2019-10-20 20:38:55 -04:00
Thomas Harte
f79c87659f Corrects documentation error. 2019-10-20 20:38:55 -04:00
Thomas Harte
c10b64e1c0 Adds a received_data_ register, that presently can never fill. 2019-10-20 20:38:55 -04:00
Thomas Harte
5d5fe52144 Corrects transmission logic — exactly hitting write_data_time_remaining now works properly. 2019-10-20 20:38:55 -04:00
Thomas Harte
d461331fd2 Ensures remaining_delays_ is set properly after [reset/flush]_writing. 2019-10-20 20:38:55 -04:00
Thomas Harte
ff62eb6dce The ACIA actually has two clocks, though on an ST they're both 500,000 Hz. 2019-10-20 20:38:55 -04:00
Thomas Harte
374439693e Ensures serial lines know their writer's clock rate. 2019-10-20 20:38:55 -04:00
Thomas Harte
c4ef33b23f JustInTimeActors can now specify a clock divider. 2019-10-20 20:38:55 -04:00
Thomas Harte
a7ed357569 Attempts to implement transmission interrupts and ClockingHint::Source. 2019-10-20 20:38:55 -04:00
Thomas Harte
4e5b440145 Attempts mostly to implement 6850 output. 2019-10-20 20:38:55 -04:00
Thomas Harte
2bd7be13b5 Decodes the 6850 control register, and starts working on standardised serial ports. 2019-10-20 20:38:55 -04:00
Thomas Harte
4b09d7c41d Nudges 6850 towards coherence. 2019-10-20 20:38:55 -04:00
Thomas Harte
b0f5f7bd37 Attempts to start producing actual video. 2019-10-20 20:38:55 -04:00
Thomas Harte
4ead905c3c Adds an empty shell for the ACIA. 2019-10-20 20:38:55 -04:00
Thomas Harte
127bb043e7 Adds enough logic to advance to an ACIA access error. 2019-10-20 20:38:55 -04:00
Thomas Harte
2cf52fb89c Makes an unsuccessful first attempt at some timer functionality. 2019-10-20 20:38:54 -04:00
Thomas Harte
6e1b606adf Adds a target for MFP read/write operations. 
Completely without any implementation, so far.
 2019-10-20 20:38:54 -04:00
Thomas Harte
e095a622d3 Ensures updates even when the event queue is empty. 2019-10-17 23:59:43 -04:00
Thomas Harte
9ab49065cd Starts to transfer serial line decoding logic into the line itself. 2019-10-17 23:34:39 -04:00
Thomas Harte
ab50f17d87 Silences, temporarily. 2019-10-16 23:34:49 -04:00
Thomas Harte
f5a2e180f9 Mostly but not quite fixes serial work. 2019-10-16 23:34:37 -04:00
Thomas Harte
f2e1584275 Starts working on the GPIP functionality block. 2019-10-16 23:21:25 -04:00
Thomas Harte
0fd8813ddb Attempts to tie an intelligent keyboard to the other end of its serial line. 2019-10-16 23:21:14 -04:00
Thomas Harte
b69180ba01 Corrects documentation error. 2019-10-16 23:19:42 -04:00
Thomas Harte
c352d8ae8c Adds a received_data_ register, that presently can never fill. 2019-10-13 23:04:57 -04:00
Thomas Harte
530e831064 Corrects transmission logic — exactly hitting write_data_time_remaining now works properly. 2019-10-13 21:40:46 -04:00
Thomas Harte
3b165a78f2 Ensures remaining_delays_ is set properly after [reset/flush]_writing. 2019-10-13 21:39:25 -04:00
Thomas Harte
8d87e9eb1c The ACIA actually has two clocks, though on an ST they're both 500,000 Hz. 2019-10-13 21:32:34 -04:00
Thomas Harte
f86dc082bb Ensures serial lines know their writer's clock rate. 2019-10-13 20:41:08 -04:00
Thomas Harte
d7982aa84e JustInTimeActors can now specify a clock divider. 2019-10-13 18:19:39 -04:00
Thomas Harte
516d78f5a8 Attempts to implement transmission interrupts and ClockingHint::Source. 2019-10-12 23:46:57 -04:00
Thomas Harte
8b50a7d6e3 Attempts mostly to implement 6850 output. 2019-10-12 23:14:29 -04:00
Thomas Harte
4bf81d3b90 Decodes the 6850 control register, and starts working on standardised serial ports. 2019-10-12 18:19:55 -04:00
Thomas Harte
cd75978e4e Nudges 6850 towards coherence. 2019-10-12 00:04:02 -04:00
Thomas Harte
c5ebf75351 Attempts to start producing actual video. 2019-10-10 22:46:58 -04:00
Thomas Harte
d7ce2c26e8 Adds an empty shell for the ACIA. 2019-10-10 20:54:29 -04:00
Thomas Harte
f88e1b1373 Adds enough logic to advance to an ACIA access error. 2019-10-09 23:01:11 -04:00
Thomas Harte
1de1818ebb Makes an unsuccessful first attempt at some timer functionality. 2019-10-07 22:44:35 -04:00
Thomas Harte
885f890df1 Adds a target for MFP read/write operations. 
Completely without any implementation, so far.
 2019-10-06 23:14:05 -04:00
Thomas Harte
929475d31e Minor correction: round down, not up. 2019-09-28 23:49:32 -04:00
Thomas Harte
7758f9d0a9 Improves nomenclature. 2019-09-24 22:31:36 -04:00
Thomas Harte
8d4a96683a Reduces output noise. 2019-09-18 21:41:29 -04:00
Thomas Harte
f53411a319 Removes local NDEBUG. 2019-09-18 21:35:26 -04:00
Thomas Harte
962275c22a Removes clock for NCR 5380. 
It doesn't have one in real life, and now can live off the time counting that occurs on the SCSI bus.
 2019-09-18 20:17:47 -04:00
Thomas Harte
2f6c366668 Makes a concerted effort at properly wrapping a hard disk image. 2019-09-17 21:30:04 -04:00
Thomas Harte
2ce1f0a3b1 Implements multi-sector read/write. 
This once again unblocks Apple HD SC Setup. Progress!
 2019-09-16 22:20:42 -04:00
Thomas Harte
960b289e70 Edges closer towards proper DMA operation. 
Specifically: differentiates the three kinds of DMA operation. Still doesn't act correctly with regard to DACK though, and leaves the bus instantaneously improperly formed. Which I'm tempted to try to fix on the target side by properly obeying delays.
 2019-09-15 15:03:06 -04:00
Thomas Harte
243e40cd79 Adds signalling of DACK. 2019-09-14 13:48:33 -04:00
Thomas Harte
64dad35026 Decreases logging, at least temporarily. 2019-09-03 22:40:32 -04:00
Thomas Harte
1c7e0f3c9d Fixes control line modification by the 5380 and SCSI target command chaining. 
So now I'm back to trying to guess how a SCSI command terminates re: the relative meanings of a message phase and a status phase.
 2019-09-02 23:14:37 -04:00
Thomas Harte
ca08716c52 Introduces real hard disk images to the nascent world of SCSI. 2019-08-25 17:03:41 -04:00
Thomas Harte
c86db12f1c Starts implementing DMA support on the 5380. 
The Macintosh doesn't actually use the DMA signals, but uses pseudo-DMA mode so they nevertheless need to be appropriate.
 2019-08-24 22:47:11 -04:00
Thomas Harte
2d82855f26 Attempts to provide a data out phase. 2019-08-22 23:16:58 -04:00
Thomas Harte
faec516a2c Starts pushing towards figuring out a proper infrastructure for mass storage. 2019-08-21 23:22:58 -04:00
Thomas Harte
bb1a0a0b76 Sketches out further SCSI infrastructure. 2019-08-21 22:37:39 -04:00
Thomas Harte
252650808d Starts seeking to unbind SCSI bus logic and command performance. 2019-08-19 22:47:01 -04:00
Thomas Harte
e3d9254555 Implements phase-match bit. 
Seemingly causing the command phase to proceed.
 2019-08-18 23:15:54 -04:00
Thomas Harte
955e909e61 Attempts to nudge the command phase further towards functioning. 2019-08-18 22:39:27 -04:00
Thomas Harte
8339e2044c Switches to proper SCSI terminology and better attempts a command phase. 2019-08-18 15:10:07 -04:00
Thomas Harte
0e0c789b02 Starts attempting to introduce a direct access device. 
Without having access to the SCSI-1 standard, a lot of this is guesswork.
 2019-08-17 23:43:42 -04:00