684 Commits

Author	SHA1	Message	Date
Thomas Harte	95a6b0f85c	Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.	2017-06-22 21:09:26 -04:00
Thomas Harte	644ef13acd	Connected up the fast-tape GUI option for the ZX80 and '81.	2017-06-22 20:20:31 -04:00
Thomas Harte	0e0ce379b4	Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.	2017-06-21 20:38:08 -04:00
Thomas Harte	36e8a11505	Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.	2017-06-21 20:32:08 -04:00
Thomas Harte	108da64562	Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.	2017-06-20 22:25:00 -04:00
Thomas Harte	184b371649	Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.	2017-06-20 21:48:50 -04:00
Thomas Harte	27ac342928	Corrected conditional call timing, and its test.	2017-06-20 20:57:23 -04:00
Thomas Harte	6752f165db	Added failing tests for both kinds of CALL.	2017-06-19 22:03:29 -04:00
Thomas Harte	e05076b258	Added tests for everything except CALL. All passing.	2017-06-19 22:00:04 -04:00
Thomas Harte	fadbfdf801	Added DJNZ test.	2017-06-19 21:31:56 -04:00
Thomas Harte	cb277b8d1e	Added JP and JR tests.	2017-06-19 21:27:23 -04:00
Thomas Harte	234f14dbbe	Tests were at fault; all passing now.	2017-06-19 21:14:40 -04:00
Thomas Harte	99ede3a9ef	BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).	2017-06-19 21:04:14 -04:00
Thomas Harte	378233f53d	Extended to BITs and SETs, accruing three new failures.	2017-06-19 21:01:30 -04:00
Thomas Harte	f903408980	Caught up on comments.	2017-06-19 20:53:22 -04:00
Thomas Harte	b684254908	Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.	2017-06-19 20:33:34 -04:00
Thomas Harte	351d90ca55	Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.	2017-06-19 20:04:55 -04:00
Thomas Harte	23177df26a	Added various tests of the basic ALU ops.	2017-06-19 19:53:26 -04:00
Thomas Harte	ba15371948	Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.	2017-06-19 19:47:00 -04:00
Thomas Harte	8d60734737	Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.	2017-06-19 19:17:54 -04:00
Thomas Harte	002098d496	The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.	2017-06-19 07:45:41 -04:00
Thomas Harte	85c5c4405a	Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.	2017-06-19 07:30:01 -04:00
Thomas Harte	d668879ba6	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	b6f51474ff	Ensured that -description can handle the newly-captured bus actions.	2017-06-17 18:20:30 -04:00
Thomas Harte	0f18768091	Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.	2017-06-17 18:19:25 -04:00
Thomas Harte	50cd617bd9	Ensured test raises only the intentional failure exceptions.	2017-06-15 22:33:46 -04:00
Thomas Harte	838b818cd3	Finished transcribing first page of machine cycle documentation; several failures contained.	2017-06-15 22:19:49 -04:00
Thomas Harte	cf795562bf	Continued filling in tests, fleshing out what the test machine captures as a result.	2017-06-15 20:59:59 -04:00
Thomas Harte	ac37424878	Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.	2017-06-15 19:06:59 -04:00
Thomas Harte	aed2827e7b	Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.	2017-06-12 22:22:00 -04:00
Thomas Harte	a48616a138	Fixed reference to Swift-world MachineDocument for the ZX81 file type.	2017-06-12 18:51:11 -04:00
Thomas Harte	8222aac9e3	Added an official declaration of support for ZX81 files.	2017-06-11 21:40:41 -04:00
Thomas Harte	77aa3c187e	Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately.	2017-06-11 21:38:32 -04:00
Thomas Harte	8116f85479	Allowed the static analyser to specify a ZX80 or 81, and a memory model. Neither is respected yet in the machine.	2017-06-11 19:12:20 -04:00
Thomas Harte	50be3a24fe	Sought to ensure that Mode 1 interrupts aren't happening early. Which they seem not to be.	2017-06-11 13:30:08 -04:00
Thomas Harte	7e10c7f9d8	Relocated the ZX80/81 concept of a 'file' out from Tape into Data, given that it's an exact duplicate of memory.	2017-06-08 19:09:51 -04:00
Thomas Harte	60300851ea	Started sketching out a tape parser for ZX80 and '81 files. I think this'll help me to verify whether the .O input is working.	2017-06-07 10:12:13 -04:00
Thomas Harte	8c66e1d99d	Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.	2017-06-06 17:53:23 -04:00
Thomas Harte	cc4cb45e9d	Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.	2017-06-06 09:25:18 -04:00
Thomas Harte	c485c460f7	Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.	2017-06-04 18:08:35 -04:00
Thomas Harte	b0a7c58287	Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents.	2017-06-04 17:57:37 -04:00
Thomas Harte	d2637123c4	Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.	2017-06-04 17:55:19 -04:00
Thomas Harte	02b7c3d1b0	Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target.	2017-06-04 17:04:06 -04:00
Thomas Harte	8c1769f157	Made a quick attempt at serialising from ZX80 .O to waves.	2017-06-04 16:59:26 -04:00
Thomas Harte	655809517c	Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required.	2017-06-04 16:37:03 -04:00
Thomas Harte	2190f60a89	Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.	2017-06-04 15:46:35 -04:00
Thomas Harte	0eebfdb4cc	Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.	2017-06-04 15:39:37 -04:00
Thomas Harte	7811374b0f	Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).	2017-06-04 15:07:07 -04:00
Thomas Harte	87095b0578	Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.	2017-06-04 14:04:26 -04:00
Thomas Harte	b642d9f712	Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.	2017-06-03 21:54:42 -04:00
Thomas Harte	fd6623b5a5	Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.	2017-06-03 21:22:16 -04:00
Thomas Harte	b304c3a4b9	Eliminated the 6502's reliance on the micro-op scheduler.	2017-06-03 20:30:07 -04:00
Thomas Harte	b3da16911f	Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.	2017-06-03 18:42:54 -04:00
Thomas Harte	e52892f75b	Added a test of interrupt mode 1.	2017-06-03 18:16:13 -04:00
Thomas Harte	8c41a0f0ed	Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine.	2017-06-03 17:53:44 -04:00
Thomas Harte	3e9212aaff	Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.	2017-06-03 17:41:45 -04:00
Thomas Harte	d14902700a	Minor syntax and wiring fixes.	2017-06-01 22:33:05 -04:00
Thomas Harte	c95c32a9fe	Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.	2017-06-01 22:31:04 -04:00
Thomas Harte	494ce073b5	Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging.	2017-05-31 19:58:57 -04:00
Thomas Harte	5ff73faf48	Ensured Zexall can pass.	2017-05-31 19:55:06 -04:00
Thomas Harte	2f7f11e2e5	Added diagnosis props.	2017-05-31 06:54:25 -04:00
Thomas Harte	5119997122	Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.	2017-05-30 22:41:23 -04:00
Thomas Harte	7bddd294c9	Resolved an unpredictable conditional and temporarily disabled the Zexalltest as part of the default suite, since it takes so long to run.	2017-05-30 21:03:02 -04:00
Thomas Harte	244b5ba3c2	Added a proper termination condition for Zexall and, for now, a Mhz counter.	2017-05-30 18:32:38 -04:00
Thomas Harte	960de7bd7b	Marginally reduced test machine costs based on usage.	2017-05-30 11:59:07 -04:00
Thomas Harte	c6185baa99	Fixed R incrementation and attempted to make the status flags cheaper to write to.	2017-05-29 22:23:19 -04:00
Thomas Harte	4d4695032c	Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end.	2017-05-29 21:46:00 -04:00
Thomas Harte	6d22f6fcd5	Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being.	2017-05-29 17:17:17 -04:00
Thomas Harte	8bfaa487ce	Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).	2017-05-29 17:13:24 -04:00
Thomas Harte	267b2add9a	Adjusted for where FUSE nominally places timestamps. Down to 92 failures.	2017-05-29 16:44:07 -04:00
Thomas Harte	d290e3d99e	Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)	2017-05-29 16:35:00 -04:00
Thomas Harte	a6a4c5a936	Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.	2017-05-29 15:57:27 -04:00
Thomas Harte	ed7b07c8b1	Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.	2017-05-29 11:54:27 -04:00
Thomas Harte	d83dd17738	[DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed.	2017-05-29 11:40:56 -04:00
Thomas Harte	9ade0dcae3	One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison.	2017-05-29 11:06:23 -04:00
Thomas Harte	a329d85697	Instituted memory value checks, flushing out seven new failures.	2017-05-29 11:01:45 -04:00
Thomas Harte	c322410783	Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.	2017-05-29 10:52:54 -04:00
Thomas Harte	b67331e018	Fixing the OUT repetition group reduces the code to one failing test.	2017-05-29 10:48:53 -04:00
Thomas Harte	ad56a9215c	Implemented IN[I/D]x. 18 failures remaining.	2017-05-29 10:12:33 -04:00
Thomas Harte	c56a5344b9	Implemented CP[I/D]x.	2017-05-29 08:54:00 -04:00
Thomas Harte	409c82ce73	Implemented RLD and RRD. 34 failures remaining.	2017-05-28 16:46:27 -04:00
Thomas Harte	6e83b7d6df	Attempted to add a proper exit condition for Zexall.	2017-05-28 15:13:47 -04:00
Thomas Harte	5a4d448cc1	Corrected logical flags; now down to 68 failures, all of them on the ED page.	2017-05-28 15:09:58 -04:00
Thomas Harte	6b66c8f304	Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84.	2017-05-28 14:50:51 -04:00
Thomas Harte	035df316aa	FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures.	2017-05-27 23:54:53 -04:00
Thomas Harte	c7cb47a1d8	Readded and then disabled my temporary one-test-only patch. Failures are currently at 237.	2017-05-27 21:10:25 -04:00
Thomas Harte	98423c6e41	Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.	2017-05-27 16:19:15 -04:00
Thomas Harte	33c3fa21e3	Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.	2017-05-27 15:54:24 -04:00
Thomas Harte	9bc2b48d9b	Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.	2017-05-26 23:23:33 -04:00
Thomas Harte	e4e71a1e5f	Switched back to descriptive failures, but put a cap on them.	2017-05-25 21:08:24 -04:00
Thomas Harte	fba5af280e	Shortened failure message, at least for now.	2017-05-25 21:05:47 -04:00
Thomas Harte	2cadc706e2	Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started.	2017-05-25 21:00:33 -04:00
Thomas Harte	3c6f63abcc	Started towards running the FUSE tests. Just need to deal with the memory segments.	2017-05-25 19:12:59 -04:00
Thomas Harte	00cd7e7e9c	After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON.	2017-05-25 18:20:13 -04:00
Thomas Harte	055c860b43	Sealed off RegisterState as immutable, and started trying to parse the .expected file.	2017-05-23 22:32:36 -04:00
Thomas Harte	454c8628c3	Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable.	2017-05-23 22:05:33 -04:00
Thomas Harte	a23a6db4d6	Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine.	2017-05-23 08:13:24 -04:00
Thomas Harte	6575091a78	Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.	2017-05-22 21:50:34 -04:00
Thomas Harte	9e25d014d2	Made an attempt to log bus activity for comparison with FUSE results.	2017-05-22 19:49:38 -04:00