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Commit Graph

134 Commits

Author SHA1 Message Date
Thomas Harte
2cdeaa2575 Moves misplaced bracket. 2018-10-23 22:37:19 -04:00
Thomas Harte
286783e880 Accepts GCC's suggestion of extra clarity brackets. 2018-10-23 22:36:23 -04:00
Thomas Harte
00e7958a97 Separates request for an SMS2 VDP from current graphics mode.
Thereby fixes various minor segments of Codemasters games.
2018-10-23 22:19:45 -04:00
Thomas Harte
2f995eb622 Adjusts vertical timing for display height. 2018-10-23 21:20:44 -04:00
Thomas Harte
90fbad0f1c Implements SMS2-style addressing if in a 224 or 240-line mode.
This isn't quite accurate, but it'll do for development.
2018-10-23 20:30:08 -04:00
Thomas Harte
2cbd28478d Allows the sprite terminator to be specified. 2018-10-23 20:01:47 -04:00
Thomas Harte
7855145ebd Slightly adjusts pixel output time.
i.e. respective to reading; sprite collision times now seem correct.
2018-10-22 19:58:33 -04:00
Thomas Harte
883680731a Uses explicit state to determine whether a pixel target has been requested. 2018-10-21 21:18:41 -04:00
Thomas Harte
c07f9fed99 Corrects test and implementation to pass the exhaustive VDP interrupt prediction test. 2018-10-21 18:42:49 -04:00
Thomas Harte
16f08eb654 Slightly tweaks Master System timing numbers. 2018-10-21 13:58:34 -04:00
Thomas Harte
30b99f0049 Fixes a couple of interrupt prediction errors. 2018-10-20 18:25:28 -04:00
Thomas Harte
b61de65b43 Restores proper phase with the CPU. 2018-10-19 23:18:16 -04:00
Thomas Harte
0822c96ce0 Implements the proper row counter values for > 192 row modes. 2018-10-19 22:37:56 -04:00
Thomas Harte
f9a6c00493 Makes first attempt to support PAL timings. 2018-10-19 21:36:13 -04:00
Thomas Harte
4cd65eab5c Seeks to avoid bad macro expansion. 2018-10-18 22:36:25 -04:00
Thomas Harte
9bc09046c0 Attempts to ensure that sprites can go off the top of the screen. 2018-10-18 21:48:57 -04:00
Thomas Harte
512f085891 Ensures proper left clipping of sprites. 2018-10-18 21:14:16 -04:00
Thomas Harte
da00c832f5 Corrects colour fetching for multicolour text mode. 2018-10-18 20:38:00 -04:00
Thomas Harte
8ff265c3a1 Corrects multicolour text mode. 2018-10-18 20:25:42 -04:00
Thomas Harte
1fc88c4eff Corrects off-by-one error in line fetching coroutines. 2018-10-16 21:36:31 -04:00
Thomas Harte
58ca74c68a Resolves right-side TMS sprite droppages. 2018-10-16 21:25:08 -04:00
Thomas Harte
b4f871a2ef Corrects first line sprite row selection. 2018-10-16 21:16:29 -04:00
Thomas Harte
0f7bf6d6c6 Resolves attempt to output graphics on the line one before the display. 2018-10-16 21:02:31 -04:00
Thomas Harte
5dfe7d8596 Corrects most of TMS sprite drawing. 2018-10-16 20:49:04 -04:00
Thomas Harte
231009b901 Makes faulty attempt to reintroduce TMS-mode sprites. 2018-10-16 20:00:06 -04:00
Thomas Harte
1c5f939aea Reintroduces tiles and some element of sprites in regular TMS mode. 2018-10-14 21:52:13 -04:00
Thomas Harte
c1e6406fc9 Corrects sprite accumulation. 2018-10-14 19:56:09 -04:00
Thomas Harte
d66979c68f Switched to a very large number of buffers, and resolved stupid attempt to reassign a reference. 2018-10-14 18:19:11 -04:00
Thomas Harte
6c09abc6cb Makes a flawed attempt to reformulate this exactly as two separate processes on a common clock with an interchange buffer.
Specifically because closer inspection of the TMS modes shows it isn't quite valid to model output of one line as having fully completed prior to fetching of the next. So some sort of extra buffer is required. At which point it is most natural to continue with the logic that each fetch routine is oriented around the fetching process for a single line, and each output routine has the same view, suggesting separate read/write addresses.

Something is wrong though, as video data is being output too rapidly (I think) and with occasional sync issues (again: subject to investigation).
2018-10-14 16:23:45 -04:00
Thomas Harte
9e52ead09a Ensures sprite scanning doesn't improperly set collision flag; that slot 151 is filled. 2018-10-12 19:50:48 -04:00
Thomas Harte
9ab0c54426 Eliminates faulty attempt to satisfy SMSVDP vertical counter test. 2018-10-12 18:57:07 -04:00
Thomas Harte
f6af6778ab Moves scrolling latch to proper position and implements 4-window fetching offset. 2018-10-11 22:36:27 -04:00
Thomas Harte
6a94dda60d Selects potentially-correct interrupt times. 2018-10-11 21:42:09 -04:00
Thomas Harte
82b7944599 Fixes horizontal counter wrapping. 2018-10-11 20:37:29 -04:00
Thomas Harte
52e02db5c8 Introduces horizontal counter latching and reading.
Then makes a new guess at frame IRQ position. But gets it wrong. Hmmm.
2018-10-11 19:56:32 -04:00
Thomas Harte
9a933993f5 Added TODO. 2018-10-10 22:17:17 -04:00
Thomas Harte
062b2ae8d3 Corrects calculation of [NTSC, 192 line] current row. 2018-10-10 22:15:38 -04:00
Thomas Harte
9f69dbf31a Adds half-updating of RAM pointer.
This emulator now passes the first screen of the SMS VDP test.
2018-10-10 21:59:08 -04:00
Thomas Harte
63fb3f03d1 Corrects address loading upon accesses of registers other than 0. 2018-10-10 21:47:48 -04:00
Thomas Harte
2e379b0834 Adds latching of scroll values. 2018-10-10 21:28:18 -04:00
Thomas Harte
f00f6c8c23 Allows the frame interrupt to be placed anywhere in the frame. 2018-10-10 21:07:39 -04:00
Thomas Harte
50e23f4a2e Fixes 16px-high sprites. 2018-10-10 20:34:00 -04:00
Thomas Harte
acdc84e08c Improves test slightly, and fixes line interrupt reload value setting. 2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549 Introduces a first unit test for line interrupts and corrects backup behaviour. 2018-10-09 21:49:21 -04:00
Thomas Harte
dccf17e770 Makes a first serious attempt at Master System line interrupts. 2018-10-09 20:51:09 -04:00
Thomas Harte
2d8ab72e22 Fixed proper starting position for (interrupted) tile drawing. 2018-10-08 23:13:37 -04:00
Thomas Harte
748366c70e Corrects buffer overrun when the horizontal scroll lock is on. 2018-10-08 23:06:22 -04:00
Thomas Harte
7a74fe2ff7 Corrects tile plotting window and eliminates a redundant local. 2018-10-08 22:56:31 -04:00
Thomas Harte
e410302237 Switches to real SMS line output composition.
Including setting the sprite collision bit.
2018-10-08 22:43:10 -04:00
Thomas Harte
bca2161a05 Fixes TMS text mode for the new addressing order. 2018-10-07 21:09:01 -04:00