Thomas Harte
25956bd90f
Mildly improves temporary logging.
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A deckchair shuffle, at best.
2019-08-26 22:35:11 -04:00
Thomas Harte
1a60ced61b
Starts trying to deal with creating a whole volume from merely a partition.
2019-08-25 23:03:54 -04:00
Thomas Harte
081316c071
Adds some additional commentary as this takes shape.
2019-08-25 17:46:05 -04:00
Thomas Harte
eafbc12cc1
Ensures a clean entry into the command phase.
2019-08-25 17:43:14 -04:00
Thomas Harte
ca08716c52
Introduces real hard disk images to the nascent world of SCSI.
2019-08-25 17:03:41 -04:00
Thomas Harte
30cef1ee22
Adds write support.
2019-08-25 15:16:35 -04:00
Thomas Harte
5598802439
Makes the static analyser aware of mass-storage devices.
2019-08-25 15:10:09 -04:00
Thomas Harte
1c6720b0db
Adds new class to Xcode project.
2019-08-25 15:09:43 -04:00
Thomas Harte
404b088199
Adds a trivial mass-storage device, for Macintosh HFV volumes.
2019-08-25 15:09:27 -04:00
Thomas Harte
7d61df238a
Localises #include.
2019-08-25 15:09:04 -04:00
Thomas Harte
c86db12f1c
Starts implementing DMA support on the 5380.
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The Macintosh doesn't actually use the DMA signals, but uses pseudo-DMA mode so they nevertheless need to be appropriate.
2019-08-24 22:47:11 -04:00
Thomas Harte
ce2e85af8b
Adds missing bus state callouts.
2019-08-22 23:27:00 -04:00
Thomas Harte
2d82855f26
Attempts to provide a data out phase.
2019-08-22 23:16:58 -04:00
Thomas Harte
faec516a2c
Starts pushing towards figuring out a proper infrastructure for mass storage.
2019-08-21 23:22:58 -04:00
Thomas Harte
8e274ec5d0
Merge branch 'master' into SCSI
2019-08-21 22:38:18 -04:00
Thomas Harte
bb1a0a0b76
Sketches out further SCSI infrastructure.
2019-08-21 22:37:39 -04:00
Thomas Harte
252650808d
Starts seeking to unbind SCSI bus logic and command performance.
2019-08-19 22:47:01 -04:00
Thomas Harte
e3d9254555
Implements phase-match bit.
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Seemingly causing the command phase to proceed.
2019-08-18 23:15:54 -04:00
Thomas Harte
90cf99b626
Takes a wild swings at speeding up startup.
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With no success.
2019-08-18 22:40:16 -04:00
Thomas Harte
955e909e61
Attempts to nudge the command phase further towards functioning.
2019-08-18 22:39:27 -04:00
Thomas Harte
8339e2044c
Switches to proper SCSI terminology and better attempts a command phase.
2019-08-18 15:10:07 -04:00
Thomas Harte
0e0c789b02
Starts attempting to introduce a direct access device.
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Without having access to the SCSI-1 standard, a lot of this is guesswork.
2019-08-17 23:43:42 -04:00
Thomas Harte
7e001c1d03
Corrects data line loading.
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Also adds some extra temporary logging. Outstanding question: why is ATN not being signalled? Is SEL enough?
2019-08-17 21:30:59 -04:00
Thomas Harte
9047932b81
Corrected basic error. Arbitration now seems to succeed.
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This is seemingly followed by a pattern of signalling BUSY+SEL followed by just SEL with the various other potential device IDs in turn. To which nothing ever responds as currently implemented.
2019-08-15 23:28:30 -04:00
Thomas Harte
f668e4a54c
Makes an attempt at getting the 5380 past arbitration.
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Not entirely successful. Also gets a bit smarter with `final` on ClockingHint::Sources.
2019-08-15 23:14:40 -04:00
Thomas Harte
ce1c96d68c
Starts thinking out the mechanics of emulating a SCSI-1 bus.
2019-08-13 23:09:11 -04:00
Thomas Harte
0f67e490e8
Adjusts NCR address decoding to produce a more plausible initial interaction.
2019-08-11 22:43:25 -04:00
Thomas Harte
895c315fa5
Increases the Mac Plus too 4mb.
2019-08-11 21:41:12 -04:00
Thomas Harte
a90a74a512
Stubs in just enough of the 5380 to get a Mac Plus too boot.
2019-08-11 20:55:20 -04:00
Thomas Harte
3e1286cbef
Merge pull request #644 from MaddTheSane/patch-1
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Update CSMachine.mm
2019-08-11 19:25:16 -04:00
Thomas Harte
949c1e1668
Adds an empty shell for what will be my 5380 implementation.
2019-08-10 23:53:52 -04:00
Thomas Harte
bbd4e4d3dc
Enhances memory map fidelity to allow for ROM holes on the Mac Plus.
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This is how the ROM detects the difference between the Plus and the 512ke, it seems.
2019-08-10 23:53:34 -04:00
C.W. Betts
4c5f596533
Update CSMachine.mm
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No need to create a temporary NSNumber object to be passed to a variadic method.
2019-08-10 00:43:30 -06:00
Thomas Harte
4859d3781b
Merge pull request #643 from TomHarte/Mac512
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Simplifies just-in-time usage of the IWM, and the disk-speed accumulator
2019-08-07 21:51:07 -04:00
Thomas Harte
bac0461f7f
Switches the drive-speed accumulator to the delegate pattern.
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This allows the Macintosh to ensure that the IWM is kept up just-in-time with drive speed changes.
2019-08-07 21:39:23 -04:00
Thomas Harte
f26a200d78
Switches to a JustInTimeActor to wrap the IWM.
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Also simplifies potential future usage of the IWM template.
2019-08-07 21:28:02 -04:00
Thomas Harte
28ccb7b54e
Merge branch 'master' of github.com:TomHarte/CLK
2019-08-04 21:34:49 -04:00
Thomas Harte
b6e4c8209b
Switches to showing 'File -> Open...' at launch.
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As per the prevailing wind.
2019-08-04 21:34:30 -04:00
Thomas Harte
16548f0765
Merge pull request #642 from TomHarte/InterruptSampling
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Moves timing of interrupt sampling into prefetch queue advancement.
2019-08-04 21:20:22 -04:00
Thomas Harte
6a80832140
Moves timing of interrupt sampling into prefetch queue advancement.
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As per comment, that is definitely the only place it can occur; I don't know whether it always occurs there.
2019-08-04 21:06:34 -04:00
Thomas Harte
c6cf0e914b
Merge pull request #641 from TomHarte/DIVSTiming
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Substantially improves DIVS timing.
2019-08-04 20:46:50 -04:00
Thomas Harte
35b1a55c12
Corrects DIVS negative flag.
2019-08-04 20:36:33 -04:00
Thomas Harte
e3794c0c0e
Takes a second pass at DIVS timing, seeming to correct that side of things.
2019-08-04 20:33:43 -04:00
Thomas Harte
f88dc23c71
Corrects comment.
2019-08-04 20:30:41 -04:00
Thomas Harte
0e293e4983
Relocates RAM delay test in order to scrape out a minor performance win.
2019-08-03 21:46:45 -04:00
Thomas Harte
e334abfe20
Partitions the 68000 arithmetic tests, to allow easier per-instruction execution.
2019-08-03 17:44:47 -04:00
Thomas Harte
fd2fbe0e59
Merge pull request #640 from TomHarte/InterruptSignalling
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Corrects 68000 address lines during interrupt acknowledgement.
2019-08-03 15:42:15 -04:00
Thomas Harte
330b27d085
Merge branch 'master' into InterruptSignalling
2019-08-03 15:39:22 -04:00
Thomas Harte
478f2533b5
Corrects 68000 address bus during interrupt acknowledge.
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All unused bits should be 1, not 0.
2019-08-03 15:38:36 -04:00
Thomas Harte
b96972a4b9
Merge pull request #639 from InvisibleUp/master
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Allow for scons to run on Python 3
2019-08-03 08:51:45 -04:00