261 Commits

Author	SHA1	Message	Date
Thomas Harte	34eaf75352	Fixed WAIT_FOR_TIME macro.	2017-08-06 12:08:54 -04:00
Thomas Harte	29288b690e	Switched disk controllers to be instantiated explicitly in terms of cycles, created an Amstrad-specific subclass of the 8272 to record the direct programmatic availability of all disk motors bundled together, and otherwise adjusted to ensure the thing is clocked and that the motor is enabled and disabled appropriately. The 8272 is also now formally a subclass of the incoming MDM controller.	2017-08-06 09:45:16 -04:00
Thomas Harte	25fd3f7e50	Mildly increased work in here, still primarily oriented towards logging what I actually need to get done.	2017-08-05 22:26:59 -04:00
Thomas Harte	3e984e75b6	Strung up an empty shell that eventually should contain the 8272, and added appropriate IO decoding to the Amstrad.	2017-08-05 19:45:52 -04:00
Thomas Harte	26ce6cdab2	Permitted register 3 to dictate vertical sync length.	2017-08-04 08:56:36 -04:00
Thomas Harte	3ca9c38777	Attempted to move to more accurate bus reading — if control lines are set then all subsequent data inputs should act according to the current control lines; changes to port input should be reflected live upon readings, etc.	2017-08-02 19:45:58 -04:00
Thomas Harte	0267bc237f	Added the ability to set a port input, and relaxed bus state testing. I think my on-demand bus reactions here are inappropriate, so more work to do here probably.	2017-08-01 18:04:51 -04:00
Thomas Harte	e6854ff8db	Corrected typo: the input to an AY is BDIR, not BCDIR.	2017-08-01 17:06:57 -04:00
Thomas Harte	2d4e202be3	Completed dangling comment.	2017-08-01 17:01:36 -04:00
Thomas Harte	64da8e17d1	Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended.	2017-08-01 17:01:20 -04:00
Thomas Harte	08ad35efd9	It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.	2017-08-01 16:34:13 -04:00
Thomas Harte	58b98267fc	Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.	2017-08-01 16:15:19 -04:00
Thomas Harte	ace71280a0	Removed implementation file; this is only ever going to be a template.	2017-08-01 16:00:17 -04:00
Thomas Harte	1d99c116e7	Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.	2017-08-01 15:29:37 -04:00
Thomas Harte	ee27e16fb1	Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.	2017-08-01 15:19:25 -04:00
Thomas Harte	3b1db14817	Made a quick attempt at properly updating the refresh address.	2017-08-01 07:36:03 -04:00
Thomas Harte	e3f677fa37	I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.	2017-07-31 22:21:46 -04:00
Thomas Harte	5c68b6cc21	Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.	2017-07-31 22:16:08 -04:00
Thomas Harte	ffaa627820	Fixed frame restart when there is no adjustment period.	2017-07-31 22:13:45 -04:00
Thomas Harte	5a396f6787	Added an explicit cast.	2017-07-31 22:04:31 -04:00
Thomas Harte	cb0dc7b434	I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.	2017-07-31 22:01:54 -04:00
Thomas Harte	e28829bd1b	Corrected CRTC timing, gave it someone to talk to and a means with which to talk.	2017-07-31 20:14:46 -04:00
Thomas Harte	68ceeab610	Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.	2017-07-31 19:56:59 -04:00
Thomas Harte	4abd62e62b	Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.	2017-07-27 22:05:29 -04:00
Thomas Harte	1da24d10fd	Corrected a couple of build errors.	2017-07-27 08:05:14 -04:00
Thomas Harte	8361756dc4	Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.	2017-07-27 07:40:02 -04:00
Thomas Harte	1c2f68f129	Removed, as it's been relocated.	2017-07-25 20:43:05 -04:00
Thomas Harte	75d67ee770	Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.	2017-07-25 20:20:55 -04:00
Thomas Harte	a1e9a54765	Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.	2017-07-25 20:09:13 -04:00
Thomas Harte	545683df6f	Added some documentation, got explicit again about cycle/half-cycle intermingling, and added flush as what amounts to divide(1), for cleaner usage without a clock divider.	2017-07-25 19:50:40 -04:00
Thomas Harte	cfbd62a5dc	Attempted to fix implementation of divide, and marked everything as-yet unmarked as inline.	2017-07-25 07:43:39 -04:00
Thomas Harte	40339a12e1	Formalised the use of a cycles count with a divider, bringing a few additional plain-int users into the fold.	2017-07-25 07:15:31 -04:00
Thomas Harte	9be9bd9106	Neatened layout.	2017-07-24 22:52:35 -04:00
Thomas Harte	c1527cc9e2	Reduced back-and-forth between Cycles and ints within the Oric.	2017-07-24 22:46:31 -04:00
Thomas Harte	a1a3aab115	Fixed implicit sign conversion.	2017-07-24 22:40:15 -04:00
Thomas Harte	c77a83d86f	The 6560 is now a ClockReceiver. This reduces to zero the number of remaining instances of the text run_for_cycles in this codebase.	2017-07-24 22:38:35 -04:00
Thomas Harte	efdac2ce8c	The 6522 is now a ClockReceiver.	2017-07-24 22:29:09 -04:00
Thomas Harte	2912d7055b	The 6532 is now a ClockReceiver.	2017-07-24 21:57:24 -04:00
Thomas Harte	b7f88e8f61	Filter is now a ClockReciever, affecting all sound output devices.	2017-07-24 21:29:13 -04:00
Thomas Harte	8a2bdb8d22	Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.	2017-07-24 21:19:05 -04:00
Thomas Harte	b82bef95f3	Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.	2017-07-24 20:10:05 -04:00
Thomas Harte	8a0b0cb3d7	Extended both classes to allow copy assignment, copy construction and implicit zero-length construction.	2017-07-23 22:13:41 -04:00
Thomas Harte	1ba3f262a2	Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.	2017-07-22 21:46:50 -04:00
Thomas Harte	8755824c64	Added some documentation.	2017-07-22 17:25:53 -04:00
Thomas Harte	64865b3f41	Signedness fixes.	2017-07-21 21:23:34 -04:00
Thomas Harte	53f0e1896b	Made delay_time_ unsigned for safe comparison.	2017-07-21 21:21:23 -04:00
Thomas Harte	aaa60dab12	Fixed signedness of index.	2017-07-21 21:21:01 -04:00
Thomas Harte	12f7e1b804	Enshrined a default colour burst amplitude. Which now everybody relies on. The 102 figure is derived from the burst apparently being 40 IRE.	2017-07-07 23:35:14 -04:00
Thomas Harte	eb8a2de5d6	Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.	2017-05-15 07:38:59 -04:00
Thomas Harte	e270b726b3	Tweaked blue, increased saturation.	2017-05-13 22:01:02 -04:00