145 Commits

Author	SHA1	Message	Date
Thomas Harte	cabf1a052c	Fill in operand sizes and flags for the 68010 extensions.	2022-10-27 09:39:00 -04:00
Thomas Harte	83b9fc3318	Declare TRAPcc operand size.	2022-10-25 12:20:40 -04:00
Thomas Harte	9a56d053f8	Introduce/extend 68k enums to cover 68020 instruction set.	2022-10-22 15:20:30 -04:00
Thomas Harte	cb0e259339	Start the process of decoding 68020 operations.	2022-10-21 15:28:29 -04:00
Thomas Harte	ec728ad573	Fix ADD/SUBX carry.	2022-10-19 22:17:51 -04:00
Thomas Harte	bc9ddacb8d	Improve commentary.	2022-10-19 14:40:29 -04:00
Thomas Harte	979bf42541	Fix ASL overflow test.	2022-10-18 22:43:17 -04:00
Thomas Harte	d09473b66f	Move common negative and zero logic into Status.	2022-10-18 14:51:51 -04:00
Thomas Harte	b31b4a5d10	Reformulate NOT in terms of EOR, and clean up elsewhere.	2022-10-18 12:17:55 -04:00
Thomas Harte	5560a0ed39	Fix overflow test for ASL.	2022-10-18 11:47:36 -04:00
Thomas Harte	a1ae7c28b2	Add various insurances against undefined behaviour.	2022-10-18 11:30:40 -04:00
Thomas Harte	fb2b7969a2	Add TODO to self on undefined behaviour.	2022-10-17 23:14:14 -04:00
Thomas Harte	abb19e6670	Populate carry whenever count != 0, regardless of modulo.	2022-10-17 22:57:21 -04:00
Thomas Harte	555250dbd9	Don't trample on X before use.	2022-10-17 22:19:35 -04:00
Thomas Harte	8148397f62	Fill in comments, eliminate u/s_extend16 macros.	2022-10-17 15:37:13 -04:00
Thomas Harte	f095bba1ca	Eliminate bitwise macros.	2022-10-17 15:21:54 -04:00
Thomas Harte	ee3a3df0b5	Eliminate SBCD macro.	2022-10-17 15:12:38 -04:00
Thomas Harte	aff1caed15	Clean up formatting.	2022-10-17 15:05:23 -04:00
Thomas Harte	da03cd58c1	Add overt casting.	2022-10-17 15:04:28 -04:00
Thomas Harte	ce98ca4bdd	Pull RO[L/R][X]m out of their macro stupor.	2022-10-17 11:27:04 -04:00
Thomas Harte	cc55f0586d	Clean up ASL/ASR/LSL/LSRm.	2022-10-17 11:18:10 -04:00
Thomas Harte	47e8f3c0f1	Collapse [A/L]S[L/R].[bwl] into a template.	2022-10-16 22:21:20 -04:00
Thomas Harte	d5ceb934d2	Fix overflow flags, avoid bigger-word usage.	2022-10-16 21:52:00 -04:00
Thomas Harte	17c1e51231	Commute ROL/ROR to templates.	2022-10-16 12:19:09 -04:00
Thomas Harte	fee072b404	Commute ROXL and ROXR into a template.	2022-10-16 12:06:28 -04:00
Thomas Harte	0a9c392371	Remove unused bit_count.	2022-10-13 15:01:06 -04:00
Thomas Harte	06dbb7167b	Unify TST.	2022-10-11 21:31:14 -04:00
Thomas Harte	eff9a09b9f	Collapse MOVE and NEG[X] similarities.	2022-10-11 21:27:18 -04:00
Thomas Harte	1f19141746	Eliminate BiggerInt.	2022-10-11 16:19:47 -04:00
Thomas Harte	28093196b9	Convert DIVU/DIVS logic to a template.	2022-10-11 16:16:53 -04:00
Thomas Harte	eb206a08d9	Templatise MULU/MULS.	2022-10-11 16:02:20 -04:00
Thomas Harte	b2f005da1b	Collapse SR/CCR bitwise operations into a template.	2022-10-11 15:53:11 -04:00
Thomas Harte	8305a3b46a	Consolidate compare logic.	2022-10-11 12:57:02 -04:00
Thomas Harte	f3f23f90a3	Consolidate repetition in CLR.	2022-10-11 11:22:34 -04:00
Thomas Harte	77bc60bf86	Consolidate BCLR, BCHG and BSET into a macro.	2022-10-11 10:47:55 -04:00
Thomas Harte	ec5d57fefe	Eliminate 64-bit work.	2022-10-11 10:33:28 -04:00
Thomas Harte	58396f0c52	Perform a prima facie conversion of ADD/SUB[/X] from macros to templates.	2022-10-10 22:21:13 -04:00
Thomas Harte	02b6ea6c46	Factor out would-accept-interrupt test, per uncertainty re: level 7.	2022-06-03 08:31:56 -04:00
Thomas Harte	c3b436fe96	Use int64_t as an intermediary to avoid x86 exception on INT_MIN/-1.	2022-06-02 21:39:52 -04:00
Thomas Harte	659e4f6987	Include fixed cost of rolls. Which includes providing slightly more information to did_shift.	2022-06-01 20:30:51 -04:00
Thomas Harte	8ffaf1a8e4	Ensure did_divu/s are performed even upon divide by zero.	2022-05-29 21:18:19 -04:00
Thomas Harte	7788a109b0	Tweak more overtly to avoid divide by zero.	2022-05-29 20:51:50 -04:00
Thomas Harte	c97245e626	Fix CalcEA timing; make MOVEfromSR a read-modify-write.	2022-05-27 10:32:28 -04:00
Thomas Harte	9e3c2b68d7	Eliminate potential future implicit conversion warnings.	2022-05-24 11:05:24 -04:00
Thomas Harte	6a442e0136	MOVEM has an immediate first operand.	2022-05-20 20:34:51 -04:00
Thomas Harte	cb77519af8	Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.	2022-05-20 12:40:09 -04:00
Thomas Harte	ba8592ceae	At least on the 68000, Scc is read-modify-write.	2022-05-20 11:43:26 -04:00
Thomas Harte	452dd3ccfd	Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.	2022-05-20 11:20:23 -04:00
Thomas Harte	eeb6a088b8	Add a tag to avoid duplication.	2022-05-19 15:49:42 -04:00
Thomas Harte	e4c0a89889	Just use the four-bit register number directly.	2022-05-19 15:01:09 -04:00