Thomas Harte
1afcbba218
Clarify sign extension availability.
2022-03-05 16:44:26 -05:00
Thomas Harte
8a0902a83b
Adapts existing opcodes for 32-bit parsing.
2022-03-05 13:52:07 -05:00
Thomas Harte
dfb312fee6
Make column and row meanings overt.
2022-03-05 11:56:08 -05:00
Thomas Harte
11bb594fa2
Sets up [ignored] memory and data size prefixes.
2022-03-02 20:23:35 -05:00
Thomas Harte
8e3ae2c78f
Add opcode map as documentation.
2022-03-02 20:00:21 -05:00
Thomas Harte
4b4135e35a
Correct #undef.
2022-03-01 18:23:24 -05:00
Thomas Harte
d1148c4cab
Switch to constexpr function, for guaranteed semantics.
2022-03-01 17:30:41 -05:00
Thomas Harte
8ee62b4789
Simplify address size semantics.
...
Since it'll no longer be a mode-dependant toggle, but a fully-retained value.
2022-03-01 17:29:26 -05:00
Thomas Harte
5e7a142ff1
Fix is_write errors, update comment, add additional source for asserts.
2022-03-01 16:51:54 -05:00
Thomas Harte
2c816db45e
Refactor: (i) to expose effective address calculation; and (ii) to include address size in Instruction.
2022-03-01 09:36:37 -05:00
Thomas Harte
b920507f34
Double down on AddressT, add an assert on memory_mask.
2022-02-28 10:03:58 -05:00
Thomas Harte
afbc57cc0c
Incorporate displacement, switch macro flag.
2022-02-28 09:53:23 -05:00
Thomas Harte
9f12c009d6
Correct data size when accessing address registers.
2022-02-27 19:45:03 -05:00
Thomas Harte
84ac68a58b
Fix indirect memory read/write
2022-02-27 18:43:00 -05:00
Thomas Harte
27d1df4699
Introduce enough of a DataPointerResolver test to build but fail.
2022-02-27 18:27:58 -05:00
Thomas Harte
0d7a7dc7c9
Introduce DataPointerResolver, to codify the meaning of DataPointer and validate that enough information is present.
2022-02-27 11:25:02 -05:00
Thomas Harte
b8bff0e7f5
Double up eSP, eBP, eSI, eDI and AH, CH, DH, BH enums, as per Intel's encoding.
2022-02-24 05:16:15 -05:00
Thomas Harte
60bf1ef7ea
Rename SourceSIB to DataPointer, extend to allow for an absent base.
2022-02-23 08:28:20 -05:00
Thomas Harte
95976d8b58
Add missing #include.
2022-02-21 16:33:58 -05:00
Thomas Harte
ecb20cc29b
Improve tabbing.
2022-02-21 16:09:03 -05:00
Thomas Harte
b6183e86eb
Clarifies model tests by macro; adds the address size toggle.
2022-02-21 16:06:02 -05:00
Thomas Harte
229af0380c
This is normatively called the address size.
2022-02-21 15:52:16 -05:00
Thomas Harte
b968a662d3
Dump notes on intended Instruction layout, add memory size flag.
2022-02-21 15:48:58 -05:00
Thomas Harte
159e869fe6
Justifies the templatisation.
2022-02-21 15:33:08 -05:00
Thomas Harte
76814588b8
Template Instruction on its content size.
2022-02-21 12:36:03 -05:00
Thomas Harte
1934c7faa2
Switch Decoder into a template.
2022-02-21 12:21:57 -05:00
Thomas Harte
9e9e160c43
Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.
2022-02-21 11:45:46 -05:00
Thomas Harte
546b4edbf1
Ensure ScaleIndexBase can be used constexpr; add note-to-self on indexing table.
2022-02-20 19:22:28 -05:00
Thomas Harte
63d8a88e2f
Switch to holding the SIB as a typed ScaleIndexBase.
...
(and permit copy assignment)
2022-02-20 17:54:53 -05:00
Thomas Harte
75d2d64e7c
Albeit that it requires nuanced shift/roll semantics, eliminates CL constant.
...
Shifts and rolls are already slightly semantically special for being undefined for values greater than 8/16/32 — i.e. in some implementations they don't even use the entirety of CL, just the low five bits. Which makes me feel a little better.
The upside of no ambiguity between eCX size 1 and CL justifies the trade.
2022-02-20 17:52:19 -05:00
Thomas Harte
a5113998e2
Accept that IN and OUT are going to have special semantics, thereby kill ::AX and ::DX.
2022-02-20 17:15:01 -05:00
Thomas Harte
4d2e8cd71d
Adds a presently-unreachable step for SIB consumption.
2022-02-19 18:00:27 -05:00
Thomas Harte
30b355fd6f
Chips away further at the legacy register names.
2022-02-18 18:37:47 -05:00
Thomas Harte
12df7112da
Starts adjusting the concept of a Source.
2022-02-17 11:32:09 -05:00
Thomas Harte
cd5ca3f65b
Attempts a full decoding of the 80286 instruction set.
2022-02-10 17:13:50 -05:00
Thomas Harte
0bd63cf00f
Introduces the easy F page instructions.
2022-02-10 09:35:05 -05:00
Thomas Harte
7ceb3369eb
Attempts decoding of the 80186 set.
2022-02-09 17:51:48 -05:00
Thomas Harte
ae21726287
Splits 80186 additions from 80286; fills in a touch more.
2022-02-01 20:38:10 -05:00
Thomas Harte
a4da1b6eb0
Begins enumerating the 80286 and 80386 instructions.
2022-01-31 09:11:06 -05:00
Thomas Harte
85bfd2eba3
Remove further errant 'Awaiting's.
2022-01-31 08:22:07 -05:00
Thomas Harte
2d543590dc
Make a noun, for better consistency.
2022-01-31 08:14:33 -05:00
Thomas Harte
2574407afb
Relocates MinIntTypeValue to Numeric.
2021-06-22 19:33:02 -04:00
Thomas Harte
135134acfd
Adds a shell for video emulation.
2021-03-18 12:47:48 -04:00
Cacodemon345
82717b39bb
Fix compilation on GCC 10
2021-03-13 01:27:29 +06:00
Thomas Harte
cbf5a79ee8
Takes a swing at improper key repeat.
2021-02-28 16:46:09 -05:00
Thomas Harte
5d1970d201
Adds a hacky different guess at how register access might work.
2021-02-19 21:46:18 -05:00
Thomas Harte
2e9065b34c
Increases number of fixed initial values.
2021-02-18 22:48:53 -05:00
Thomas Harte
2a45e7a8d4
Slows timer X, to what may or may not be correct.
2021-02-15 16:40:27 -05:00
Thomas Harte
f8f0ff0fae
Add timer X counting.
...
Still no interrupts.
2021-02-15 16:29:25 -05:00
Thomas Harte
f5dcff2f29
Honours interrupt vector.
2021-02-15 15:05:56 -05:00
Thomas Harte
eccf5ca043
Makes first effort to wire up the ADB vertical blank input.
...
However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-14 22:20:58 -05:00
Thomas Harte
c284b34003
Resolves inability of ADB microcontroller to read its own ROM (!)
2021-02-13 17:53:40 -05:00
Thomas Harte
2c4dcf8843
Edges towards implementing an ADB device.
2021-02-12 21:50:24 -05:00
Thomas Harte
e83b2120ce
Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.
2021-02-10 21:46:56 -05:00
Thomas Harte
3c7f9a43ad
Merge branch 'AppleIIgs' of github.com:TomHarte/CLK into AppleIIgs
2021-02-08 18:43:27 -05:00
Thomas Harte
82312d3b59
Provide a more convincing version of port output.
2021-02-08 18:14:08 -05:00
Thomas Harte
93a80a30d3
With correct divider appears to get reset requests posted.
2021-02-07 23:05:01 -05:00
Thomas Harte
77b1efd176
Sets sensible 'reset' values.
2021-02-07 21:53:57 -05:00
Thomas Harte
acfab1dfb3
Starts to make some effort at timers.
2021-02-06 21:02:44 -05:00
Thomas Harte
819e9039ab
Corrects printed target address for ZeroPageRelative.
2021-02-04 20:54:31 -05:00
Thomas Harte
b8c6d4b153
Rips out my high-level ADB microcontroller protocol implementation.
...
Adds just enough that the main computer validates the ADB controller as present and talking.
2021-01-30 17:53:27 -05:00
Thomas Harte
5eddc92846
Implements direction registers.
2021-01-28 21:06:11 -05:00
Thomas Harte
f50e8b5106
If I'm going to maintain the max_address approach, & is 'correct'.
...
% +1 would be 'more correct', but I think this approach is probably misguided.
2021-01-27 18:31:11 -05:00
Thomas Harte
dcc2fe0990
Improves M50470 entry-point detection, adds test output.
2021-01-26 21:29:17 -05:00
Thomas Harte
56111c75ae
Makes first efforts towards disassembly.
2021-01-26 19:52:30 -05:00
Thomas Harte
cc90935abd
Starts to provide just a touch of reflection.
2021-01-26 19:22:00 -05:00
Thomas Harte
413e42e1b6
Attempts to fix BBC.
...
But thereby stops all ADB output.
2021-01-25 22:34:03 -05:00
Thomas Harte
fc4bda0047
Experimentally flipping interpretation of the output bit gives something closer to coherent.
2021-01-25 22:02:39 -05:00
Thomas Harte
c8beb59172
Attempts properly to track ADB bus activity.
...
Output is not yet a valid ADB stream. Work to do.
2021-01-25 17:43:22 -05:00
Thomas Harte
8789ffda15
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-24 22:30:42 -05:00
Thomas Harte
e8e604dc3c
Attempts to wire up M50470 and GLU.
...
Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 18:07:05 -05:00
Thomas Harte
57e0fdfadc
Ensures ADB microcontroller is clocked.
...
And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
2021-01-23 22:55:12 -05:00
Thomas Harte
36aebe0ff9
Posts cycle lengths.
2021-01-23 21:58:52 -05:00
Thomas Harte
051d2b83f4
Corrects TSX lookup.
2021-01-23 15:45:21 -05:00
Thomas Harte
17b12120eb
Corrects bit-selection shifts.
2021-01-21 23:13:00 -05:00
Thomas Harte
6e9ce50569
Corrects duration-based iteration.
2021-01-21 23:05:43 -05:00
Thomas Harte
adef2e9b4e
Starts formalising end conditions.
2021-01-21 22:36:44 -05:00
Thomas Harte
0fafbf5092
Completes M50740 instruction set.
2021-01-21 19:08:38 -05:00
Thomas Harte
c10c161d39
Implements ADC and SBC.
2021-01-21 18:53:24 -05:00
Thomas Harte
04024ca159
Adds BIT.
2021-01-20 21:41:43 -05:00
Thomas Harte
64d556f60f
Implements shifts and rotates.
2021-01-20 21:39:13 -05:00
Thomas Harte
8564e7406b
Corrects index-mode CMP, LDA.
2021-01-20 21:32:46 -05:00
Thomas Harte
ebdb58d790
Seemingly advances to the first indefinite loop.
2021-01-20 21:18:52 -05:00
Thomas Harte
cf8afc70b2
Takes a swing at BBC, BBS.
2021-01-20 20:52:04 -05:00
Thomas Harte
4f02e8fbaf
Knocks off the low-hanging instruction fruit.
2021-01-20 20:41:35 -05:00
Thomas Harte
6e618a6bb7
Adds a list of missing instructions.
...
Not looking too bad; subject to not yet having a strategy for interrupts, timing, nothing yet implemented for timers, IO ports...
2021-01-20 20:37:35 -05:00
Thomas Harte
df1bc18fb3
Pushes ahead to what will be my first interaction with the T flag.
2021-01-20 20:27:09 -05:00
Thomas Harte
9f12ce2fb8
Corrects RTS, adds the remainder of the direct flag manipulations.
2021-01-20 20:16:55 -05:00
Thomas Harte
b9672c0669
Gets beyond a prima facie convincing JSR/RET.
2021-01-20 18:21:44 -05:00
Thomas Harte
e58608b25a
Gets as far as executing a first loop.
2021-01-20 18:15:24 -05:00
Thomas Harte
e502d76371
Corrects immediate instruction length, muddles through to having to parse a second program segment.
...
Albeit with JSR not yet properly implemented.
2021-01-19 22:12:18 -05:00
Thomas Harte
b0c790f3c6
Adds enough flags seemingly to reach an ASL.
2021-01-19 21:54:15 -05:00
Thomas Harte
aa478cd222
Stops trying to force bit ID into the addressing mode.
2021-01-19 21:51:01 -05:00
Thomas Harte
c78c121159
Succeeds at executing a single instruction.
2021-01-18 20:16:01 -05:00
Thomas Harte
e71e506883
This assert is redundant; not worth an extra #include.
2021-01-18 17:56:40 -05:00
Thomas Harte
a601ac0cab
Corrects performer population, lookup, calls.
2021-01-18 17:53:14 -05:00
Thomas Harte
9b92753e0a
In theory this should 'execute' up to the first unconditional branch.
...
Where execution means: do very little.
2021-01-18 17:11:11 -05:00
Thomas Harte
ec0018df79
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 16:59:49 -05:00
Thomas Harte
8b19c523cf
Starts to bend towards getting some performers in motion.
2021-01-18 16:45:52 -05:00
Thomas Harte
5ace61f9b9
Continues walking very slowly towards cached execution.
2021-01-18 11:20:45 -05:00
Thomas Harte
8a74f5911c
Minor reorganisation to finish the day.
2021-01-17 21:56:15 -05:00
Thomas Harte
4982430a29
Takes a run at most of the remaining addressing modes.
2021-01-17 21:52:16 -05:00
Thomas Harte
dea79c6dea
Adds missing #include.
2021-01-17 20:56:22 -05:00
Thomas Harte
ad03858c6e
Switches performers to member functions. Very slightly starts work on M50740 performers.
2021-01-17 20:53:11 -05:00
Thomas Harte
54b26c7991
Bends to using 8-bit lookups for M50740 instructions.
2021-01-17 20:03:36 -05:00
Thomas Harte
17c3a3eb4b
Seeks to switch to maintaining a bank of performers.
...
My thinking here is that for really simple processors there'll be 256 or less, meaning that they can be stored by simple uint8_t; for every other processor I can currently think of it'll likely be uint16_t.
Either way, that's a much better outcome than using plain pointers, which on architectures I currently build for will always be 8 bytes. For the simple processors I can get eight times as much into the cache; for the others four times.
2021-01-17 19:38:23 -05:00
Thomas Harte
5f413a38df
Switches all American-style dates.
...
I'd failed to configure my new computer appropriately, it seems.
2021-01-16 22:09:19 -05:00
Thomas Harte
8860d0ff51
Starts to establish the CachingExecutor.
2021-01-16 22:06:16 -05:00
Thomas Harte
8bd471fa3c
Corrects recursive call.
2021-01-16 21:50:48 -05:00
Thomas Harte
cd6ac51aa6
Muddles along to generating functions.
...
Albeit right now without a body.
2021-01-16 21:45:44 -05:00
Thomas Harte
10caa1a1fb
Steps gingerly towards execution.
2021-01-16 20:51:02 -05:00
Thomas Harte
722e0068ca
Adds additional exposition.
2021-01-16 20:10:20 -05:00
Thomas Harte
8f2eea8819
Corrects AccessType::Read.
2021-01-16 20:04:48 -05:00
Thomas Harte
3b2d65fa16
Adds access type declaration.
2021-01-16 20:04:01 -05:00
Thomas Harte
3dc36b704a
Starts on the next piece: parsers.
2021-01-16 19:54:40 -05:00
Thomas Harte
37a20e125c
Completes the M50740 decoder.
...
Completely untested.
2021-01-15 22:47:52 -05:00
Thomas Harte
2910faf963
Adds missing #include.
2021-01-15 22:33:14 -05:00
Thomas Harte
1acb8c3c42
Completes the opcode map.
2021-01-15 22:24:37 -05:00
Thomas Harte
f667dd223f
Advances to 50% of the opcode map.
2021-01-15 22:05:34 -05:00
Thomas Harte
e0d90f69ec
Fills in the first quarter of the opcode map.
2021-01-15 21:58:46 -05:00
Thomas Harte
d82187bee2
Decides to shove bit number into AddressingMode.
2021-01-15 21:50:05 -05:00
Thomas Harte
3c20e1f037
Adds files for the M50740 and corrects namespace errors elsewhere.
2021-01-15 21:30:30 -05:00
Thomas Harte
9c2c918760
Better sorts by function, corrects TEST description.
2021-01-15 21:07:02 -05:00
Thomas Harte
47d20699d8
Completes list, ensures POP acts as documented.
2021-01-15 20:48:31 -05:00
Thomas Harte
e8ce70dccb
Chips further away at documentation.
2021-01-15 18:52:59 -05:00
Thomas Harte
fa4938f29c
Establishes the reason I'm sort-of documenting these.
2021-01-15 18:27:55 -05:00
Thomas Harte
ddb4bb1421
Better plans project layout.
2021-01-15 18:16:01 -05:00
