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13,218 Commits 3 Branches 145 Tags
5aa9168dd681bed75c4c58a9d64eb325f970f85e
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1391 Commits

Author SHA1 Message Date
Thomas Harte 5aa9168dd6 Make overflow private. 2025-10-28 20:49:59 -04:00
Thomas Harte b3f01fe314 Move carry into private storage. 2025-10-28 20:43:57 -04:00
Thomas Harte e688d87c22 Move negative and zero into private storage. 2025-10-28 18:23:16 -04:00
Thomas Harte 332fb2f384 Make decimal flag private. 2025-10-28 17:34:31 -04:00
Thomas Harte 5332bcd6b4 Clarify set/get difference; make interrupt flag storage private. 2025-10-28 17:32:10 -04:00
Thomas Harte 55c59e6164 Start hiding Flags implementation. 2025-10-28 17:24:53 -04:00
Thomas Harte 58e1880773 Eliminate 'addr' side effects. 2025-10-27 22:14:48 -04:00
Thomas Harte c8c4c99f09 Incorporate IRQ timing test; accept that it must be tested within the access macro. 2025-10-27 21:32:52 -04:00
Thomas Harte bc5b7a6725 Unpublish WriteableReader. 2025-10-27 17:01:29 -04:00
Thomas Harte 7b4e71e6dd Just use the preprocessor then. Yuck. 2025-10-27 13:10:24 -04:00
Thomas Harte a32202ab72 Be more overt in trying to avoid "use of undeclared identifier". 2025-10-27 12:52:57 -04:00
Thomas Harte 3dd07b6ac1 To simplify debugging, add non-constructing path. 
This won't have any effect on generated code.
 2025-10-27 12:41:17 -04:00
Thomas Harte 12d912b627 Add insurance against bus handler not writing. 2025-10-27 12:37:38 -04:00
Thomas Harte 967c3f6dba Ensure NMI isn't perpetual. 2025-10-26 21:56:35 -04:00
Thomas Harte cba96aee37 Honour interrupt flag. 2025-10-25 17:02:48 -04:00
Thomas Harte 17325834b5 Implement is_resetting. 2025-10-25 17:02:27 -04:00
Thomas Harte 4df49d9f18 Round out interrupt signalling. 2025-10-25 08:54:25 -04:00
Thomas Harte 8b04608d68 Implement STP and WAI. 2025-10-24 23:47:30 -04:00
Thomas Harte 2bac276870 Populate type_of. 2025-10-24 23:42:40 -04:00
Thomas Harte 213f9850e7 Add WDC65C02 decoder. 2025-10-24 23:41:55 -04:00
Thomas Harte 378bffbf84 Implement BBR/BBS. 2025-10-24 23:37:18 -04:00
Thomas Harte c291d5313d Fix PLX. 2025-10-24 22:22:05 -04:00
Thomas Harte e81233c586 Implement JMP (abs,x). 2025-10-24 22:16:36 -04:00
Thomas Harte b946029394 Correct 65c02 JMPAbsoluteIndirect. 2025-10-24 21:57:53 -04:00
Thomas Harte fe79a1231d Add extra cycle to immediate decimal arithmetic. 2025-10-24 21:39:14 -04:00
Thomas Harte 76a5872d17 Install extra cycle for 65c02 decimal arithmetic. 2025-10-24 21:24:05 -04:00
Thomas Harte 0d72c75e15 Give modify stalls to fast NOPs. 2025-10-24 16:51:07 -04:00
Thomas Harte 2e0e89c494 Implement fast modify path; fix more NOPs. 2025-10-24 16:43:57 -04:00
Thomas Harte 7d6b7a5874 Adjust 0x?b NOPs. 2025-10-24 15:57:54 -04:00
Thomas Harte 48f8ddf53a 65c02: make AbsoluteIndexed modify cycle harmless. 2025-10-24 15:55:45 -04:00
Thomas Harte 9aae07b737 Implement zero indirect addressing mode. 2025-10-24 15:53:55 -04:00
Thomas Harte d7abdc8017 Transfer ownership of final PC increment, to accomodate 65c02 misreads. 2025-10-24 15:49:17 -04:00
Thomas Harte cb81156835 65c02: distinguish 'fast' NOPs from regular. 2025-10-24 13:52:32 -04:00
Thomas Harte 1fd8d94e2e Import further NOPs. 2025-10-24 13:33:10 -04:00
Thomas Harte e4fe127444 Fix 65c02 modify cycles: read/read/write, not read/write/write. 2025-10-24 13:30:10 -04:00
Thomas Harte aeabd5f113 Patch in TSB and TRB. 2025-10-24 12:33:13 -04:00
Thomas Harte 58f7d4065c 65c02: support single-cycle NOP. 2025-10-24 12:29:53 -04:00
Thomas Harte 60f25a3ba4 Add some of the easier overrides. 2025-10-24 12:21:53 -04:00
Thomas Harte d267571dc6 Add spot to fill in Synertek mappings. 2025-10-24 12:13:10 -04:00
Thomas Harte 5dc00a2092 Update #undef list. 2025-10-24 12:00:22 -04:00
Thomas Harte b20d489bf0 Remove SHA/SHX/etc. 2025-10-24 11:58:55 -04:00
Thomas Harte df39870587 Factor out index decision. 2025-10-24 11:53:55 -04:00
Thomas Harte f742eab4be Reduce to a generic case. 2025-10-23 21:54:50 -04:00
Thomas Harte e9c8c61dcf Reformulate to be slightly more conditional, but substantially deduplicate code. 2025-10-23 21:52:31 -04:00
Thomas Harte e5f09002e9 Extract bit operators. 2025-10-23 20:47:55 -04:00
Thomas Harte d42f005e17 Improve consistency. 2025-10-23 20:43:15 -04:00
Thomas Harte 24e060abee Elide ADC logic. 2025-10-23 19:54:07 -04:00
Thomas Harte 8b6d763442 Reduce duplication within ARR. 2025-10-23 19:42:36 -04:00
Thomas Harte e239745f63 Fix typo. 2025-10-23 19:35:40 -04:00
Thomas Harte cfef2b4e19 Eliminate 16-bit arithmetic from SBX. 2025-10-23 19:32:50 -04:00