Thomas Harte
5d6e479338
Implements RMB and SMB, and fixes SBC (zero).
2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5
Implements TSB and TRB, and adds the extra BIT instructions.
2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e
Implements STZ.
2018-08-10 21:17:02 -04:00
Thomas Harte
8b50ab2593
Corrects (zero) behaviour.
2018-08-10 21:12:55 -04:00
Thomas Harte
95164b79c9
Attempted implementation of (zp) addressing mode.
2018-08-09 21:51:14 -04:00
Thomas Harte
6f838fe190
Implements INA and DEA.
2018-08-08 22:30:19 -04:00
Thomas Harte
bb680b40d8
Implements the 65C02's JMPs.
2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994
Implements the 65C02 NOPs.
2018-08-08 20:00:14 -04:00
Thomas Harte
e46bde35f5
Implements BBS and BBR.
2018-08-07 21:52:17 -04:00
Thomas Harte
32338bea4d
Implements BRA.
2018-08-06 22:37:30 -04:00
Thomas Harte
5c881bd19d
Implements PLX, PLY, PHX and PHY.
2018-08-06 22:00:23 -04:00
Thomas Harte
1a44ef0469
Introduces Klaus Dorman's 65C02 tests. All failing.
2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51
Fixes test target.
2018-08-06 21:15:13 -04:00
Thomas Harte
633af4d404
The operations table is now per-instance.
2018-08-06 20:47:14 -04:00
Thomas Harte
76a73c835c
Forces 6502 consumers to declare which model — the original, 65C02 or 65SC02.
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All present machines use a regular 6502.
2018-08-06 20:06:07 -04:00
Thomas Harte
0b14850467
Corrects some comments.
2018-06-24 23:02:36 -04:00
Thomas Harte
9a91ae38c1
Differentiates reasons for a read to be four cycles.
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Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
2018-06-20 21:34:21 -04:00
Thomas Harte
ad9b0cd4e3
Eliminates all endashes.
2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10
Eliminates all emdashes in cross-platform code.
2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
45be1c19df
Resolves undefined behaviour of a signed shift left.
2018-03-22 21:59:39 -04:00
Thomas Harte
0e73ba4b3e
Introduces proper 5/3 SCF/CCF behaviour for the Z80.
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While also `const`ing a bunch of things.
2018-03-09 09:47:00 -05:00
Thomas Harte
f0f9d5a6af
Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
2018-03-08 20:30:22 -05:00
Thomas Harte
74dfe56d2b
Expands documentation of NMI setting.
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Given that it was previously incorrect, explains logic behind request_status_ and last_request_status_ setting. Also takes the opportunity to ensure that NMI is 'sampled' at the same time as IRQ; whether the next thing should be the NMI routine now occurs one cycle before the end of any instruction. That's an assumption for now. Testing to come.
2018-03-02 11:10:02 -05:00
Thomas Harte
b02e4fbbf6
Corrects NMI receipt to be genuinely edge triggered.
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Previously a caller that signalled NMI set multiple times would trigger multiple NMIs.
2018-03-01 22:04:56 -05:00
Thomas Harte
23c47e21de
Proceeds the ColecoVision to booting.
2018-02-24 18:14:38 -05:00
Thomas Harte
7dfbe4bb93
Ensures proper Boolean startup values for IFF1 and IFF2.
2017-11-29 20:32:55 -05:00
Thomas Harte
5aef81cf24
Commutes cross-platform #pragma marks to //MARK:s.
2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651
Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
2017-11-11 15:28:40 -05:00
Thomas Harte
cb0f58ab7a
Corrects order-of-initialisation errors in the CPC (again), TextureBuilder, TextureTarget, Z80, MFM parser and binary tape player.
2017-11-10 22:57:03 -05:00
Thomas Harte
4cbc87a17d
Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
2017-11-10 22:20:44 -05:00
Thomas Harte
c0055a5a5f
Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code.
2017-11-09 22:04:49 -05:00
Thomas Harte
6e1d69581c
Eliminates a variety of end-of-line spaces.
2017-11-07 22:54:22 -05:00
Thomas Harte
ad9df4bb90
Commutes uint8_t *, uint16_t *, uint32_t *, size_t, off_t and long to functional-style casts.
2017-10-21 22:30:15 -04:00
Thomas Harte
e983854e71
Converts all uint8_t and uint16_t casts to the functional style.
2017-10-21 21:50:53 -04:00
Thomas Harte
ab2bcb939f
Separates 6502Base into its constituent parts.
2017-09-04 11:08:33 -04:00
Thomas Harte
45499050b6
Separates Z80Base.cpp into its component classes.
2017-09-04 11:04:01 -04:00
Thomas Harte
a1e200cc65
Further strips back the amount exposed in Z80-related headers.
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Almost all opcode table generation macros and code now resides neatly in the world of .CPP.
2017-09-01 22:19:16 -04:00
Thomas Harte
e6ac939ae0
Reintroduces missing noexcept specifier.
2017-09-01 20:51:31 -04:00
Thomas Harte
b034d4e6f8
Refactors the Z80 to separate out interface and implementation.
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Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way.
2017-09-01 20:50:24 -04:00
Thomas Harte
de218611e4
Corrects possible confusion as documentation recommends Cycles(0) as default, but then gives Cycles(1).
2017-09-01 20:49:24 -04:00
Thomas Harte
b306776ba9
Removes from 6502.hpp all remaining implementation details, making it purely an interface document.
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Though those details remain visible to files including 6502.hpp through necessity.
2017-09-01 19:46:29 -04:00
Thomas Harte
4af333d5ec
Tidies the 6502 template and folder hierarchy.
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Specifically: there's now just the one .h file at the top level, giving a clear indication of what a user should read. That separates implementation from interface. It also devolves a lot more to the base class because doing so makes debug builds less of a hassle. The all-RAM 6502 has been shuffled off into a subfolder, to indicate that it's not something you necessarily need know about. Also general documentation improvements have been applied: incorrect citing of the recurring-template pattern has been removed and the meaning of the two BusHandler methods has now accrued at the bus handler.
2017-08-31 22:10:27 -04:00
Thomas Harte
fab6908129
Corrects the all-RAM Z80 to declare that it needs the wait line to be implemented.
2017-08-26 23:18:11 -04:00
Thomas Harte
57bfec285f
Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
2017-08-26 23:08:57 -04:00
Thomas Harte
fa19e2d9c2
Removes some detritus.
2017-08-24 22:00:21 -04:00
Thomas Harte
95d360251d
Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
2017-08-24 21:32:33 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
Thomas Harte
e1aded0d95
Allows Z80 users to opt out of support for the bus request line. Which both now do.
2017-08-21 20:43:12 -04:00
