Thomas Harte
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1365fca161
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Avoid phoney write modifies.
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2022-05-27 21:42:55 -04:00 |
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Thomas Harte
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d17d77714f
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Remove outdated TODO.
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2022-05-27 15:40:06 -04:00 |
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Thomas Harte
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e8dd8215ba
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Tweak per empirical results.
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2022-05-27 15:39:02 -04:00 |
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Thomas Harte
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e11990e453
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Make an attempt at DIVS timing.
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2022-05-27 15:38:54 -04:00 |
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Thomas Harte
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165ebe8ae3
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Add time calculation for MULU and MULS.
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2022-05-27 15:38:14 -04:00 |
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Thomas Harte
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e746637bee
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Fill in dynamic cost of shifts.
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2022-05-27 15:38:08 -04:00 |
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Thomas Harte
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0e6370d467
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Tweak per empirical results.
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2022-05-27 15:37:40 -04:00 |
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Thomas Harte
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512cd333e5
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Make an attempt at DIVS timing.
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2022-05-27 14:56:04 -04:00 |
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Thomas Harte
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f599a78cad
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Add time calculation for MULU and MULS.
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2022-05-27 14:41:42 -04:00 |
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Thomas Harte
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7601dab464
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Fill in timing calculation for DIVU.
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2022-05-27 14:30:03 -04:00 |
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Thomas Harte
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a8623eab4a
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Fill in dynamic cost of shifts.
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2022-05-27 11:12:10 -04:00 |
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Thomas Harte
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c367ddff1b
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Merge branch '68000Mk2' into InMacintosh
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2022-05-27 10:34:11 -04:00 |
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Thomas Harte
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67b340fa5e
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Fix interrupt request address.
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2022-05-27 10:33:36 -04:00 |
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Thomas Harte
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c97245e626
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Fix CalcEA timing; make MOVEfromSR a read-modify-write.
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2022-05-27 10:32:28 -04:00 |
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Thomas Harte
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79e2c17f93
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Fix interrupt request address.
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2022-05-26 20:20:28 -04:00 |
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Thomas Harte
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5937737bb7
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Merge branch '68000Mk2' into InMacintosh
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2022-05-26 19:37:44 -04:00 |
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Thomas Harte
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5f030edea4
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Simplify transaction.
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2022-05-26 19:37:30 -04:00 |
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Thomas Harte
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88e33353a1
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Fix instruction and time counting, and initial state.
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2022-05-26 09:17:37 -04:00 |
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Thomas Harte
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f3c0c62c79
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Switch register-setting interface.
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2022-05-26 07:52:14 -04:00 |
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Thomas Harte
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866787c5d3
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Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.
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2022-05-25 20:22:38 -04:00 |
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Thomas Harte
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367ad8079a
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Add a call to set register state with population of the prefetch.
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2022-05-25 20:22:05 -04:00 |
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Thomas Harte
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64491525b4
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Work further to guess at caller's intention for set_state.
Probably I should just eliminate the initial reset, somehow.
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2022-05-25 17:01:18 -04:00 |
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Thomas Harte
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68b184885f
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Reapply only the status.
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2022-05-25 16:54:25 -04:00 |
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Thomas Harte
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06f3c716f5
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Make better effort to establish initial state.
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2022-05-25 16:47:41 -04:00 |
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Thomas Harte
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22714b8c7f
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Capture state at instruction end, for potential inspection.
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2022-05-25 16:32:26 -04:00 |
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Thomas Harte
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80c1bedffb
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Eliminate false prefetch for BSR.
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2022-05-25 16:32:02 -04:00 |
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Thomas Harte
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56ad6d24ee
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Fix ANDI/ORI/EORI to CCR/SR timing.
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2022-05-25 16:20:26 -04:00 |
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Thomas Harte
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4ad0e04c23
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Fix macro for n being an expression.
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2022-05-25 16:05:45 -04:00 |
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Thomas Harte
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f9d1c554b7
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Fix for the actual number of cycles in a standard reset.
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2022-05-25 16:05:28 -04:00 |
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Thomas Harte
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ee58301a46
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Add RaiseException macro.
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2022-05-25 15:45:09 -04:00 |
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Thomas Harte
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f2a7660390
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Merge branch 'master' into 68000Mk2
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2022-05-25 15:40:10 -04:00 |
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Thomas Harte
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d4c7ce2d6f
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Merge pull request #1035 from TomHarte/68000TestIssues
Add details on gaps in coverage.
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2022-05-25 15:39:42 -04:00 |
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Thomas Harte
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4961e39fb6
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Mention DIVU/DIVS flags.
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2022-05-25 15:39:00 -04:00 |
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Thomas Harte
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0bedf608c0
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Add details on gaps in coverage.
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2022-05-25 15:36:27 -04:00 |
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Thomas Harte
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1ab831f571
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Add the option to log a list of all untested instructions.
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2022-05-25 13:17:01 -04:00 |
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Thomas Harte
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b90f1a48ce
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Merge branch '68000Mk2' into InMacintosh
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2022-05-25 13:02:44 -04:00 |
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Thomas Harte
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72425fc2e1
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Fix bus data size of MOVE.b xx, -(An).
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2022-05-25 13:00:36 -04:00 |
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Thomas Harte
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a5f2dfbc0c
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Initialise registers to 0 for better testability.
TODO: is this the real initial state?
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2022-05-25 11:47:42 -04:00 |
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Thomas Harte
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5db6a937cb
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Have TRAP and TRAPV push the next instruction address to the stack.
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2022-05-25 11:47:21 -04:00 |
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Thomas Harte
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9709b9b1b1
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Standard exceptions don't raise the interrupt level.
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2022-05-25 11:37:39 -04:00 |
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Thomas Harte
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2c6b9b4c9d
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Switch comparative trace tests to 68000 Mk2.
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2022-05-25 11:32:00 -04:00 |
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Thomas Harte
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463fbb07f9
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Adapt remaining 68000 tests to use Mk2.
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2022-05-25 10:55:17 -04:00 |
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Thomas Harte
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b6e473a515
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Adapt remaining 68000 tests to use Mk2.
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2022-05-25 10:55:03 -04:00 |
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Thomas Harte
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24f7b5806c
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Merge branch '68000Mk2' into InMacintosh
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2022-05-25 08:15:41 -04:00 |
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Thomas Harte
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5872e0ea4a
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Resolve MOVE.l xx, -(An) write target.
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2022-05-25 08:15:18 -04:00 |
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Thomas Harte
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04d2d6012a
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Merge branch '68000Mk2' into InMacintosh
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2022-05-24 16:08:56 -04:00 |
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Thomas Harte
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f43d27541b
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Avoid attempt to establish operand flags for undefined opcodes.
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2022-05-24 15:53:12 -04:00 |
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Thomas Harte
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c8d3d980ba
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Avoid attempt to establish operand flags for undefined opcodes.
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2022-05-24 15:52:53 -04:00 |
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Thomas Harte
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f93bf06b99
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Merge branch '68000Mk2' into InMacintosh
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2022-05-24 15:51:22 -04:00 |
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Thomas Harte
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0f7cb2fa5a
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Attempt to honour the trace flag.
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2022-05-24 15:47:47 -04:00 |
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