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1082 Commits

Author SHA1 Message Date
Thomas Harte 72425fc2e1 Fix bus data size of MOVE.b xx, -(An). 2022-05-25 13:00:36 -04:00
Thomas Harte a5f2dfbc0c Initialise registers to 0 for better testability. 
TODO: is this the real initial state?
 2022-05-25 11:47:42 -04:00
Thomas Harte 5db6a937cb Have TRAP and TRAPV push the next instruction address to the stack. 2022-05-25 11:47:21 -04:00
Thomas Harte 9709b9b1b1 Standard exceptions don't raise the interrupt level. 2022-05-25 11:37:39 -04:00
Thomas Harte 5872e0ea4a Resolve MOVE.l xx, -(An) write target. 2022-05-25 08:15:18 -04:00
Thomas Harte f43d27541b Avoid attempt to establish operand flags for undefined opcodes. 2022-05-24 15:53:12 -04:00
Thomas Harte 0f7cb2fa5a Attempt to honour the trace flag. 2022-05-24 15:47:47 -04:00
Thomas Harte 01e93ba916 Make an attempt at bus/address error. 2022-05-24 15:42:50 -04:00
Thomas Harte 780954f27b Add TRAP, TRAPV. 2022-05-24 15:14:46 -04:00
Thomas Harte 6f048de973 Pull unrecognised instruction handling into the usual switch table. 2022-05-24 12:42:34 -04:00
Thomas Harte 0dfaa7d9cf Interrupt fixes: supply proper address, raise level, fetch from vector. 2022-05-24 12:16:06 -04:00
Thomas Harte eab720f6ea Ensure proper transition from unrecognised instructions. 2022-05-24 12:16:00 -04:00
Thomas Harte a7e8aef9d3 Add MOVEA, be slightly more careful about next_operand_. 2022-05-24 11:30:09 -04:00
Thomas Harte df54f1f1b7 Update TODO. 2022-05-24 11:06:05 -04:00
Thomas Harte 9e3c2b68d7 Eliminate potential future implicit conversion warnings. 2022-05-24 11:05:24 -04:00
Thomas Harte 3349bcaaed Attempt interrupt support. 2022-05-24 10:53:59 -04:00
Thomas Harte 3a4fb81242 Add a dummy STOP state. 2022-05-24 10:25:40 -04:00
Thomas Harte 1df3ad0671 Ensure TAS responds to VPA, BERR. 2022-05-24 09:17:58 -04:00
Thomas Harte 523cdd859b Add bus and address error, and VPA checks. 2022-05-24 09:08:31 -04:00
Thomas Harte b037c76da6 Add public interface for everything except HALT and BUS REQ/etc. 
... neither of which are used by machines I currently implement.
 2022-05-23 20:55:01 -04:00
Thomas Harte 9cac4ca317 Add MOVE to/from USP. 2022-05-23 20:42:41 -04:00
Thomas Harte 34e5f39571 Ensure that running exactly up to a boundary gives the bus handler the next microcycle to contemplate. 2022-05-23 15:11:33 -04:00
Thomas Harte e0a279344c Codify the existence of special cases, implement NOP and RESET. 2022-05-23 15:09:46 -04:00
Thomas Harte e2f4db3e45 Shuffle more of the flow controller methods into their proper place. 2022-05-23 12:06:14 -04:00
Thomas Harte c1837af84a Add notes to self on work remaining. 2022-05-23 11:02:31 -04:00
Thomas Harte a87f6a28c9 Fix LINK A7. 2022-05-23 10:43:17 -04:00
Thomas Harte 98325325b1 Fix UNLINK A7. 2022-05-23 10:27:44 -04:00
Thomas Harte 26bf66e3f8 Fix shifts and rolls. 2022-05-23 10:09:46 -04:00
Thomas Harte 363cd97154 Resolve double definition of did_shift. 2022-05-23 10:07:24 -04:00
Thomas Harte c6b3281274 Attempt the shifts and rolls. 2022-05-23 09:29:19 -04:00
Thomas Harte 1e8adc2bd9 Fix MOVEP to R. 2022-05-23 09:00:37 -04:00
Thomas Harte c73021cf3c Implement MOVE. 2022-05-23 08:46:06 -04:00
Thomas Harte 1b3acf9cd8 Eliminate assumption. 2022-05-23 08:18:37 -04:00
Thomas Harte c8ede400eb Fix RTE. 2022-05-22 21:17:28 -04:00
Thomas Harte 269263eecf Implement RTE, RTS, RTR. 2022-05-22 21:16:38 -04:00
Thomas Harte faef5633f8 Ensure MOVE from SR has an effective address to write to. 2022-05-22 20:52:00 -04:00
Thomas Harte 7d1f1a3175 Implement MOVE [to/from] [CCR/SR]. 2022-05-22 19:45:22 -04:00
Thomas Harte 4e34727195 Fully implement TAS. 2022-05-22 16:14:03 -04:00
Thomas Harte 1dd6ed6ae3 Implement TAS Dn, with detour for other TASes. 2022-05-22 16:08:30 -04:00
Thomas Harte 3b68b9a83b Implement PEA. 2022-05-22 11:27:38 -04:00
Thomas Harte 4279ce87ea Implement LEA. 2022-05-22 08:29:12 -04:00
Thomas Harte 3c1c4f89e9 Add MULU/S functionality, though not timing. 2022-05-22 08:02:32 -04:00
Thomas Harte 4a6512f5d5 Reduce dispatch boilerplate. 2022-05-22 07:39:16 -04:00
Thomas Harte 284f23c6ea Implement JMP. 2022-05-22 07:16:38 -04:00
Thomas Harte 11a9a5c126 Use common macros for the two forms of Perform. 2022-05-22 07:08:14 -04:00
Thomas Harte 4993801741 Add missing prefetch to BSET, BCHG, BCLR. 2022-05-21 21:05:05 -04:00
Thomas Harte 4b35899a12 Bcc: properly establish offset. 2022-05-21 20:59:34 -04:00
Thomas Harte 1304e930eb DBcc is two-operand. 2022-05-21 20:06:03 -04:00
Thomas Harte 94288d5a94 Excludes DBcc from standard operand fetch. 2022-05-21 19:53:28 -04:00
Thomas Harte 3811ab1b82 Fix the two 8bit-with-displacement effective address Calc steps. 2022-05-21 16:20:01 -04:00