2579 Commits

Author	SHA1	Message	Date
Thomas Harte	10b9b13673	Disable divide-by-zero PC test in lieu of better documentation.	2022-06-03 08:27:20 -04:00
Thomas Harte	aaac777651	Merge branch 'master' into 68000Mk2	2022-06-02 17:08:41 -04:00
Thomas Harte	e7b3705060	Merge pull request #1007 from TomHarte/IPFFileFormat ... Adds partial support for the IPF file format.	2022-06-02 12:58:47 -04:00
Thomas Harte	90d720ca28	Don't test undocumented flags.	2022-06-02 12:30:39 -04:00
Thomas Harte	6dd89eb0d7	Adjust my expectation as to length.	2022-06-02 12:11:54 -04:00
Thomas Harte	e1abf431cb	Don't test undefined flags.	2022-05-30 16:23:51 -04:00
Thomas Harte	8e0fa3bb5f	DIV # with a divide by zero should be 44 cycles.	2022-05-29 21:22:45 -04:00
Thomas Harte	9eea471e72	Resolve infinite recursion.	2022-05-29 20:39:22 -04:00
Thomas Harte	2a40e419fc	Fix CHK tests: timing and expected flags.	2022-05-29 15:26:56 -04:00
Thomas Harte	5f030edea4	Simplify transaction.	2022-05-26 19:37:30 -04:00
Thomas Harte	88e33353a1	Fix instruction and time counting, and initial state.	2022-05-26 09:17:37 -04:00
Thomas Harte	f3c0c62c79	Switch register-setting interface.	2022-05-26 07:52:14 -04:00
Thomas Harte	866787c5d3	Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.	2022-05-25 20:22:38 -04:00
Thomas Harte	64491525b4	Work further to guess at caller's intention for set_state. ... Probably I should just eliminate the initial reset, somehow.	2022-05-25 17:01:18 -04:00
Thomas Harte	68b184885f	Reapply only the status.	2022-05-25 16:54:25 -04:00
Thomas Harte	06f3c716f5	Make better effort to establish initial state.	2022-05-25 16:47:41 -04:00
Thomas Harte	22714b8c7f	Capture state at instruction end, for potential inspection.	2022-05-25 16:32:26 -04:00
Thomas Harte	f9d1c554b7	Fix for the actual number of cycles in a standard reset.	2022-05-25 16:05:28 -04:00
Thomas Harte	f2a7660390	Merge branch 'master' into 68000Mk2	2022-05-25 15:40:10 -04:00
Thomas Harte	4961e39fb6	Mention DIVU/DIVS flags.	2022-05-25 15:39:00 -04:00
Thomas Harte	0bedf608c0	Add details on gaps in coverage.	2022-05-25 15:36:27 -04:00
Thomas Harte	1ab831f571	Add the option to log a list of all untested instructions.	2022-05-25 13:17:01 -04:00
Thomas Harte	2c6b9b4c9d	Switch comparative trace tests to 68000 Mk2.	2022-05-25 11:32:00 -04:00
Thomas Harte	463fbb07f9	Adapt remaining 68000 tests to use Mk2.	2022-05-25 10:55:17 -04:00
Thomas Harte	4b07c41df9	Ensure alignment of storage.	2022-05-24 11:29:28 -04:00
Thomas Harte	a87f6a28c9	Fix LINK A7.	2022-05-23 10:43:17 -04:00
Thomas Harte	98325325b1	Fix UNLINK A7.	2022-05-23 10:27:44 -04:00
Thomas Harte	26bf66e3f8	Fix shifts and rolls.	2022-05-23 10:09:46 -04:00
Thomas Harte	c6b3281274	Attempt the shifts and rolls.	2022-05-23 09:29:19 -04:00
Thomas Harte	1e8adc2bd9	Fix MOVEP to R.	2022-05-23 09:00:37 -04:00
Thomas Harte	c73021cf3c	Implement MOVE.	2022-05-23 08:46:06 -04:00
Federico Berti	1a26d4e409	Update nbcd_pea.json ... Add missing bracket	2022-05-23 12:14:00 +01:00
Thomas Harte	269263eecf	Implement RTE, RTS, RTR.	2022-05-22 21:16:38 -04:00
Thomas Harte	4e21cdfc63	Enable NEGX/CLR tests.	2022-05-22 20:55:21 -04:00
Thomas Harte	faef5633f8	Ensure MOVE from SR has an effective address to write to.	2022-05-22 20:52:00 -04:00
Thomas Harte	7d1f1a3175	Implement MOVE [to/from] [CCR/SR].	2022-05-22 19:45:22 -04:00
Thomas Harte	4e34727195	Fully implement TAS.	2022-05-22 16:14:03 -04:00
Thomas Harte	1dd6ed6ae3	Implement TAS Dn, with detour for other TASes.	2022-05-22 16:08:30 -04:00
Thomas Harte	cb4d6710df	Switch to a more direct indication of progress.	2022-05-22 11:27:58 -04:00
Thomas Harte	284f23c6ea	Implement JMP.	2022-05-22 07:16:38 -04:00
Thomas Harte	4b35899a12	Bcc: properly establish offset.	2022-05-21 20:59:34 -04:00
Thomas Harte	94288d5a94	Excludes DBcc from standard operand fetch.	2022-05-21 19:53:28 -04:00
Thomas Harte	c869eb1eec	Correct omission: wasn't testing the final PC. ... Plenty of new errors incoming.	2022-05-21 15:56:27 -04:00
Thomas Harte	176c8355cb	The tests in chk.json now pass.	2022-05-21 14:32:58 -04:00
Thomas Harte	e46a3c4046	Implement JSR.	2022-05-21 10:29:36 -04:00
Thomas Harte	256da43fe5	Fix MOVEM other than postinc and predec.	2022-05-20 20:47:54 -04:00
Thomas Harte	a818650027	Add a faulty attempt at MOVEM.	2022-05-20 18:48:19 -04:00
Thomas Harte	c7c12f9638	After a quick check, eori_andi_ori also now passes.	2022-05-20 14:47:11 -04:00
Thomas Harte	ee942c5c17	Fix PC-relative fetches.	2022-05-20 14:42:51 -04:00
Thomas Harte	d157819c49	Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch. ... (which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)	2022-05-20 14:29:14 -04:00