6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-27 15:50:56 +00:00
Code Issues Projects Releases Wiki Activity
3,930 Commits 8 Branches 121 Tags 496 MiB
abca38a548
Commit Graph

253 Commits

Author SHA1 Message Date
Thomas Harte
244b5ba3c2 Added a proper termination condition for Zexall and, for now, a Mhz counter. 2017-05-30 18:32:38 -04:00
Thomas Harte
960de7bd7b Marginally reduced test machine costs based on usage. 2017-05-30 11:59:07 -04:00
Thomas Harte
4d4695032c Discovered that Zexall is just really slow. Disabled the address sanitiser, and started working towards a verifiable end. 2017-05-29 21:46:00 -04:00
Thomas Harte
6d22f6fcd5 Having decided the bus operation error on 10 is probably in the test cases, decided to allow myself to skip that one comparison. Back to zero failing cases, and with no more useful information to derive from the FUSE test set for the time being. 2017-05-29 17:17:17 -04:00
Thomas Harte
8bfaa487ce Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit). 2017-05-29 17:13:24 -04:00
Thomas Harte
267b2add9a Adjusted for where FUSE nominally places timestamps. Down to 92 failures. 2017-05-29 16:44:07 -04:00
Thomas Harte
d290e3d99e Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!) 2017-05-29 16:35:00 -04:00
Thomas Harte
a6a4c5a936 Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures. 2017-05-29 15:57:27 -04:00
Thomas Harte
ed7b07c8b1 Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct. 2017-05-29 11:54:27 -04:00
Thomas Harte
d83dd17738 [DD/FD]36 turns out to be a timing error: offset calculation overlaps with value fetch. So the FUSE test was cutting off my implementation early. Fixed. 2017-05-29 11:40:56 -04:00
Thomas Harte
9ade0dcae3 One failure was just PUSH AF due to throwing away the 5 & 3 flags at the start. Switched to throwing them away at comparison. 2017-05-29 11:06:23 -04:00
Thomas Harte
a329d85697 Instituted memory value checks, flushing out seven new failures. 2017-05-29 11:01:45 -04:00
Thomas Harte
c322410783 Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation. 2017-05-29 10:52:54 -04:00
Thomas Harte
b67331e018 Fixing the OUT repetition group reduces the code to one failing test. 2017-05-29 10:48:53 -04:00
Thomas Harte
ad56a9215c Implemented IN[I/D]x. 18 failures remaining. 2017-05-29 10:12:33 -04:00
Thomas Harte
c56a5344b9 Implemented CP[I/D]x. 2017-05-29 08:54:00 -04:00
Thomas Harte
409c82ce73 Implemented RLD and RRD. 34 failures remaining. 2017-05-28 16:46:27 -04:00
Thomas Harte
6e83b7d6df Attempted to add a proper exit condition for Zexall. 2017-05-28 15:13:47 -04:00
Thomas Harte
5a4d448cc1 Corrected logical flags; now down to 68 failures, all of them on the ED page. 2017-05-28 15:09:58 -04:00
Thomas Harte
6b66c8f304 Implemented inputs and outputs, determined how to answer port requests to please FUSE and hence reduced failures to 84. 2017-05-28 14:50:51 -04:00
Thomas Harte
035df316aa FUSE seems to have inconsistent ideas about where b3 and b5 come from in more-complicated BIT instructions. So I'm not testing them for now. Within that reality, reduced to 102 failures. 2017-05-27 23:54:53 -04:00
Thomas Harte
c7cb47a1d8 Readded and then disabled my temporary one-test-only patch. Failures are currently at 237. 2017-05-27 21:10:25 -04:00
Thomas Harte
98423c6e41 Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues. 2017-05-27 16:19:15 -04:00
Thomas Harte
33c3fa21e3 Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672. 2017-05-27 15:54:24 -04:00
Thomas Harte
9bc2b48d9b Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures. 2017-05-26 23:23:33 -04:00
Thomas Harte
e4e71a1e5f Switched back to descriptive failures, but put a cap on them. 2017-05-25 21:08:24 -04:00
Thomas Harte
fba5af280e Shortened failure message, at least for now. 2017-05-25 21:05:47 -04:00
Thomas Harte
2cadc706e2 Now runs FUSE tests, albeit testing only a subset of the results. But enough to get started. 2017-05-25 21:00:33 -04:00
Thomas Harte
3c6f63abcc Started towards running the FUSE tests. Just need to deal with the memory segments. 2017-05-25 19:12:59 -04:00
Thomas Harte
00cd7e7e9c After hitting my head against the wall of trying to use [NS]Scanner as a parser some more, have given up and transcoded the two tests files to JSON. 2017-05-25 18:20:13 -04:00
Thomas Harte
055c860b43 Sealed off RegisterState as immutable, and started trying to parse the .expected file. 2017-05-23 22:32:36 -04:00
Thomas Harte
454c8628c3 Implemented an additional constructor for RegisterStates, pulling it out into file-level scope and implementing Equatable. 2017-05-23 22:05:33 -04:00
Thomas Harte
a23a6db4d6 Tidied up, creating a holder for RegisterState and giving it deserialisation logic. This makes sense because a register state will also need to be taken from the outputScanner, and from the machine. 2017-05-23 08:13:24 -04:00
Thomas Harte
6575091a78 Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly. 2017-05-22 21:50:34 -04:00
Thomas Harte
9e25d014d2 Made an attempt to log bus activity for comparison with FUSE results. 2017-05-22 19:49:38 -04:00
Thomas Harte
41d5dd8679 Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured. 2017-05-22 19:24:11 -04:00
Thomas Harte
22afa509ca Got to a parsing and towards an attempt to run FUSE tests. 2017-05-22 19:14:46 -04:00
Thomas Harte
3fb3cc8269 Got explicit about encodings. 2017-05-21 22:53:06 -04:00
Thomas Harte
e3e461d7cb Added a test class for running the FUSE tests. With nothing much in it. 2017-05-21 22:49:24 -04:00
Thomas Harte
c16fccb317 Fixed file names. 2017-05-21 22:43:07 -04:00
Thomas Harte
b9cffdf2bd Imported the FUSE tests. 2017-05-21 22:42:20 -04:00
Thomas Harte
d910405648 Added enough infrastructure to be able to react to the two CP/M calls this cares about. 2017-05-19 21:53:39 -04:00
Thomas Harte
62b432c046 Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes. 2017-05-19 21:20:28 -04:00
Thomas Harte
a3dafa9056 Abbreviated uses of enumerations. 2017-05-17 21:44:08 -04:00
Thomas Harte
64d6ee1be5 Adjusted slightly to adapt to latest Swift warnings. 2017-05-17 07:49:48 -04:00
Thomas Harte
1378ab7278 Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access. 2017-05-17 07:36:06 -04:00
Thomas Harte
87a021ec2d Made further attempt to get as fas as having the Z80 attempt to do something. 2017-05-16 22:19:40 -04:00
Thomas Harte
189317b80c Added enough of a Z80 test machine to bridge up into Swift. 2017-05-16 22:05:42 -04:00
Thomas Harte
4f0775cc7c Imported the Zexall.com tester, as a first thing to throw at the Z80 to be. 2017-05-16 21:37:09 -04:00
Thomas Harte
df80c37adb Renamed TestMachine to TestMachine6502 since there's going to be multiple of them. 2017-05-15 08:18:57 -04:00
Thomas Harte
0808e9b6fb Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair. 2017-05-14 22:08:15 -04:00
Thomas Harte
a6897ebde0 Added an attempt to distinguish the MegaBoy (now with proper capitalisation) and a test for it. 2017-03-13 20:43:12 -04:00
Thomas Harte
582da14a14 Added an enumerated type and detection of Pitfall 2. 2017-03-13 08:15:36 -04:00
Thomas Harte
8e147444d5 Added a readme, as is traditional for folders I'm excluding from Git. 2017-03-12 22:16:12 -04:00
Thomas Harte
2c07cce282 Had the wrong paging scheme listed for Robot Tank and Thwocker. Better to get this right before trying to come up with a test for the Activision stack scheme. 2017-03-12 21:03:10 -04:00
Thomas Harte
597bd97b01 Corrected two more table errors. 2017-03-12 15:46:25 -04:00
Thomas Harte
38de5300e5 Elevator Action seemingly uses a Super Chip. 2017-03-12 15:43:42 -04:00
Thomas Harte
146f3ea0f5 Fixed: Crystal Castles is 16kb. 2017-03-12 15:39:07 -04:00
Thomas Harte
78213f1e95 Fixed a couple more table entries, introduced per-size tests (plus a catch-all), to speed up the development/testing cycle. 2017-03-12 15:35:36 -04:00
Thomas Harte
de347ad7c8 Improved CBS RAM Plus and Super Chip detection exclusion, reducing error count to 15. 2017-03-12 14:03:17 -04:00
Thomas Harte
a4bba8a92e Made a couple of lookup table fixes and corrected RAM region detection windows; failures now down to 19. 2017-03-11 23:18:30 -05:00
Thomas Harte
fcacfc2726 Tidied up spacing, slightly. 2017-03-11 23:01:42 -05:00
Thomas Harte
bab464e765 I'm far from confident, but this should reduce the deviations close to those that result from mistakes by the static analyser, rather than table errors. 2017-03-11 22:58:11 -05:00
Thomas Harte
2879763c34 Reduced to 84 failures through more accurate tabulation. 2017-03-11 21:52:52 -05:00
Thomas Harte
ea2ea30193 Fleshed entire table out with most common values. Exceptions now to fix. 2017-03-11 21:11:25 -05:00
Thomas Harte
608569cc48 Typed out all the 'A's that I am aware of. So about 5% done. 2017-03-11 20:58:38 -05:00
Thomas Harte
c7e973aab4 Extended test set a little, corrected current failures. 2017-03-11 20:51:25 -05:00
Thomas Harte
443d57bc32 Slimmed output and added first six tests. Acid Drop fails since I'm not yet declaring Atari 16k and Atari 32k. 2017-03-11 20:43:19 -05:00
Thomas Harte
57ec756f5b Started speccing out a unit test for Atari ROM analysis. 2017-03-11 20:33:58 -05:00
Thomas Harte
d3257c345a Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place. 2017-03-04 17:00:28 -05:00
Thomas Harte
e09b76bf32 Fixed 'same value, then immediate increment, then proper counting increments' behaviour and ensured it takes one cycle to commit a value. Adjusted tests to match. 2017-03-04 15:57:54 -05:00
Thomas Harte
dd17459687 Added my first failing test: delay is incorrect when resetting outside of the play area. 2017-02-12 20:42:49 -05:00
Thomas Harte
cd90118a0f Added two, extraordinarily simple tests. 2017-02-12 20:32:53 -05:00
Thomas Harte
a568172758 Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs. 2016-12-28 18:29:37 -05:00
Thomas Harte
99993a1b24 Since it's about to become important that objective results match, added a couple of objective-result tests for the CRC generator. 2016-12-27 19:03:46 -05:00
Thomas Harte
d606bd7ce5 Added saturation test, fixed code as indicated. 2016-12-24 23:29:37 -05:00
Thomas Harte
09ff9d6a26 Introduced a couple more floating-point conversion tests, fixed errors uncovered. 2016-12-24 23:21:19 -05:00
Thomas Harte
e25195a718 Added a single test for Storage::Time, discovering that I had the wrong sign on float conversions. 2016-12-24 22:59:01 -05:00
Thomas Harte
7028f57336 Simplified a little further. 2016-12-22 18:13:10 -05:00
Thomas Harte
e4e0347638 Attempted to consolidate some of the repetition. 2016-12-21 22:17:00 -05:00
Thomas Harte
72ca06cf8d Added some extra tests, performed some basic tidying. Probably should do more. 2016-12-21 19:54:19 -05:00
Thomas Harte
6a0c7f22ee Added a few more tests. All passing. 2016-12-20 21:46:34 -05:00
Thomas Harte
03579f33f1 Fixed multi-coverage insertion, via an appropriate test. 2016-12-20 21:38:32 -05:00
Thomas Harte
7eca910cc5 Fixed insertion location finding logic, working on the relevant test. 2016-12-20 21:14:05 -05:00
Thomas Harte
c180340474 Added two more passing tests and one that crashes. 2016-12-20 19:25:58 -05:00
Thomas Harte
823ab9bc34 Completed initial non-trivial test, fixing revealed errors. 2016-12-20 19:15:36 -05:00
Thomas Harte
6bdde542c5 Edging towards functioning automatic tests, fixed right-period adjustment and slightly decreased searching cost while in the process of adding a test. 2016-12-20 07:52:14 -05:00
Thomas Harte
1df478d250 Removed dead header file. 2016-12-18 23:04:16 -05:00
Thomas Harte
e081f224b6 Implemented a very basic PCMTrack test, nevertheless revealing an oversight in PCMSegmentEventSource related to improperly counting to the index hole if the final bit is set. Took that as a message that I should comment and document the event source. 2016-12-18 22:53:24 -05:00
Thomas Harte
f9a5595dad Added seeking tests, correcting such errors as uncovered. 2016-12-18 10:19:24 -05:00
Thomas Harte
3116a2cf4c Realised I was actually testing PCMSegmentEventSource, not PCMSegment; implemented a spread of tests; hence fixed PCMSegmentEventSource. 2016-12-17 21:47:13 -05:00
Thomas Harte
254cc41fd6 Made an attempt to separate and isolate the stuff of creating flux events from a PCMSegment, eventually to factor that out of PCMTrack and make it available also to PCMPatchedTrack. 2016-12-17 21:13:57 -05:00
Thomas Harte
313db75303 Ensured the patchable track owns its underlying track. 2016-12-17 18:17:22 -05:00
Thomas Harte
3017062e89 Maybe TDD is the way to get over my activity block on this thing? Fixed the existing ArrayBuilder tests so that the tests target builds again, added an extremely trivial PCMTrack test, heading towards PCMPatchedTrack tests. 2016-12-17 17:05:49 -05:00
Thomas Harte
d17751787a The remainder of this test isn't necessarily safe to perform if the array length isn't as expected. But in that case the test has already failed, so it's not worth worrying about a partial validation. 2016-12-03 16:06:15 -05:00
Thomas Harte
be60eaa120 Added a test for pointer continuity over a submit. Which fails. 2016-11-19 19:48:16 +08:00
Thomas Harte
274ec9efb8 Added a test for interceding submit. 2016-11-19 08:59:21 +08:00
Thomas Harte
22cb8ecd75 Started building some tests of the array builder. 2016-11-19 08:27:08 +08:00
Thomas Harte
dda0c8af30 Fixed tests. 2016-11-05 12:58:56 -04:00
Thomas Harte
70973eb850 Fixed accreditation of BCDTest. 2016-11-01 22:40:48 -04:00
Thomas Harte
23376257dc Let's try this not as markup. 2016-11-01 22:36:07 -04:00
Thomas Harte
bddc540c0d Partitioned and added text for AllSuiteA and Klaus Dormann's tests. 2016-11-01 22:35:15 -04:00
Thomas Harte
ca3e1c3204 Added an appropriate licence and credit for Wolfgang Lorenz's suite. 2016-11-01 22:26:12 -04:00
Thomas Harte
4b347b9993 Made a trivial XCTAssert unit test substitution. 2016-10-30 20:30:32 -04:00
Thomas Harte
534b3d085d Improved test reporting, attempted to resolve timing errors just introduced (i.e. to differentiate break/continue where a cycle may or may not be spent). 2016-10-27 08:41:44 -04:00
Thomas Harte
f7d2e988b6 Mildly enhanced unit test, while I'm curious. 2016-10-11 22:22:53 -04:00
Thomas Harte
c097886d00 Installed hoglet's BCDTest as a formal part of the test suite; removed some redundant semicolons in the Wolfgang Lorenz tests while I was here. 2016-10-04 07:52:44 -04:00
Thomas Harte
fa7c64bb5d Eventually reached an implementation of ADC that continues to satisfy all the formalised unit tests while also satisfying the manual BCDTest, that I need to find a way to formalise. I fixed the unit tests for Swift 3 while here, and attempted to do some unrelated NIB stuff with no real success. 2016-10-03 22:03:39 -04:00
Thomas Harte
7c65c69e0f Migrated to Swift 3. 2016-09-15 22:12:12 -04:00
Thomas Harte
015cea494d Switched to a much-more straightforward PLL. I think I'm just fiddling now rather than moving forwards. Probably time to move on? 2016-07-28 11:32:14 -04:00
Thomas Harte
e061e849d4 Had a second bash at the PLL. Probably I should read some of the literature. 2016-07-27 16:24:24 -04:00
Thomas Harte
74817f6664 With a history of three pulses, this can track up a 10% sine variation in a 1010101 stream. So I guess this'll do for now? 2016-07-14 19:54:48 -04:00
Thomas Harte
ac1bc588dd Improved factoring and increased window of testing, causing both the fast and slow tests to show framing errors. 2016-07-14 07:12:02 -04:00
Thomas Harte
d1fe07f14d Added test of perfect DPLL input timing. 2016-07-12 21:42:23 -04:00
Thomas Harte
d8334edf4a Started trying to clean up, including commuting the C1540 source file name to match its class name but mainly by adding documentation. 2016-07-10 07:46:20 -04:00
Thomas Harte
656cd211d7 Was transmitting bit levels backwards (probably?); 1540 now acknowledges byte received. 2016-07-09 18:06:49 -04:00
Thomas Harte
01746f0512 This is probably a valid test. But I'm not completely sure. Time to figure out what's happening on the 1540 end. 2016-07-09 18:01:04 -04:00
Thomas Harte
cd84c35552 Whoops, one bit too short. 2016-07-09 17:51:46 -04:00
Thomas Harte
cd362b46b3 This is a valid attempt to send a whole byte, I think. 2016-07-09 17:51:04 -04:00
Thomas Harte
3560babd7e Got back to a failing test, now while trying to transmit a whole byte. Good stuff! 2016-07-09 17:39:51 -04:00
Thomas Harte
66caa3c6dc Fixed setup of bridge class. 2016-07-09 17:23:43 -04:00
Thomas Harte
bf03985ea4 Here's an instantly failing test... 2016-07-09 17:22:10 -04:00
Thomas Harte
da6fe2e983 This should be enough of a shell to write some actual tests. 2016-07-09 15:47:53 -04:00
Thomas Harte
865eb421cd Quick on-disk tidy up. 2016-07-09 15:44:55 -04:00
Thomas Harte
7cc4bf3fe7 Hit and hope is getting me nowhere. Time to unit test this thing. 2016-07-09 15:40:25 -04:00
Thomas Harte
b322baff2f Added CLI/SEI pair test. 2016-06-29 19:42:39 -04:00
Thomas Harte
db7c6430b5 Fixed Klaus Dormann termination condition. 2016-06-29 19:16:34 -04:00
Thomas Harte
6419d9c485 Added a single IRQ test case, discovering that I'm two cycles short. Whoops! 2016-06-28 21:29:43 -04:00
Thomas Harte
d5e50f5ea0 Got a bit more explicit about how ports are identified on the 6522. 2016-06-26 12:30:01 -04:00
Thomas Harte
25a5455d33 Completed bridge interface. 2016-06-20 21:07:01 -04:00
Thomas Harte
fe17d1778c Expanded 6532 tests substantially, beefing up implementation to match. 2016-06-20 21:02:42 -04:00
Thomas Harte
d5aaad396e Added a TODO on my lack of knowledge. 2016-06-19 20:13:31 -04:00
Thomas Harte
7cf6008e7c Started some very basic RIOT unit tests; corrected to pass. 2016-06-19 20:12:47 -04:00
Thomas Harte
f4915c5ad6 Fixed test and added basic implementation of data direction. 2016-06-18 17:17:03 -04:00
Thomas Harte
eea850cd12 Added a deliberately failing data direction test. 2016-06-18 16:40:01 -04:00
Thomas Harte
2282b59768 Added a quick latching test, and shortened test messages, albeit that they're still displeasingly boilerplate. 2016-06-18 16:10:46 -04:00
Thomas Harte
5d26cd85a3 Wrote test case for what appears to be correct timer behaviour if those were acting in isolation. Ensured implementation matches test case. 2016-06-18 14:30:23 -04:00
Thomas Harte
394902f409 Switched to clocking the 6522 by the half-cycle. Very trivial test now passes. 2016-06-18 13:57:10 -04:00
Thomas Harte
06fb2ff1c7 Started endeavouring to sketch out the boilerplate for writing a 6522 test harness. Added a default implementation of synchronise to the 6522 too, since not everybody is going to want one. 2016-06-18 09:28:46 -04:00
Thomas Harte
9b64f64db7 Attempted to normalise some style decisions.` 2016-04-24 22:32:24 -04:00
Thomas Harte
675070c5dd Very, _very_ minor: switched to normal C++ constructor syntax for simple variable initialisation. 2015-12-06 16:53:37 -05:00
Thomas Harte
cc98534f94 Added test for NOP, discovering the undocumented ones to be the incorrect length. 2015-08-13 07:32:50 +01:00
Thomas Harte
6616265d93 Fixed collision tests, added a few more timing tests. 2015-08-13 03:33:45 +01:00
Thomas Harte
dd0f17130a Found and fixed some timing errors in absolute indexed and in (indirect), y addressing modes: neither is able in write or read-modify-write modes to shave a cycle as then can when reading. 2015-08-13 02:58:39 +01:00
Thomas Harte
975836c30f Added a quick snippet test, discovering that I've cut a cycle from read/modify/writes. 2015-08-13 02:18:41 +01:00
Thomas Harte
503d684af0 Added a couple of timing tests, both of which seem to pass for now. 2015-08-13 01:55:23 +01:00
Thomas Harte
e8f70398c1 Added one basic timing test, for now: implied nop should be two cycles. 2015-08-13 01:06:56 +01:00
Thomas Harte
d19f8ed507 Removed the implicit reset upon 6502 startup, adding a reset line. Hence all tests now pass again. Added an empty shell for timing tests, the all-RAM 6502 now counting bus cycles. 2015-08-13 00:51:06 +01:00
Thomas Harte
53dd5c8f16 Trying to fix my RDY line emulation. Switched to PAL timings, at least temporarily, since it's starting to make a difference. 2015-07-31 16:44:53 -04:00
Thomas Harte
20c2d98b9a Converted remaining spaces to real tabs. 2015-07-30 20:51:32 -04:00