Thomas Harte
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ae5b81c0ab
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Add MSX 2 to the ROM catalogue.
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2023-01-10 18:17:17 -05:00 |
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Thomas Harte
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6bd261b222
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Add storage for secondary paging.
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2023-01-10 18:07:31 -05:00 |
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Thomas Harte
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53bb17c848
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Use model as a compile-time MSX configurator.
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2023-01-10 14:55:57 -05:00 |
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Thomas Harte
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73549eb38c
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Document quite a bit more, to refresh my memory.
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2023-01-10 14:40:03 -05:00 |
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Thomas Harte
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ef67205ce8
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Set pixel count per mode.
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2023-01-08 21:31:00 -05:00 |
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Thomas Harte
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794adf470b
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Break assumption that cycles = pixels; fix pixel clocking.
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2023-01-08 21:25:22 -05:00 |
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Thomas Harte
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e8aab1fd2a
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Restore proper VDP selection.
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2022-12-31 21:54:14 -05:00 |
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Thomas Harte
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ffb0b2ce0b
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Eliminate runtime duplication of personality.
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2022-12-31 21:50:57 -05:00 |
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Thomas Harte
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7d6eac2895
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Template the TMS on its personality.
Template parameter currently unused, but preparatory to other improvements.
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2022-12-31 15:08:33 -05:00 |
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Thomas Harte
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ee22a98c17
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Add note to future self.
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2022-12-27 20:23:25 -05:00 |
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Thomas Harte
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28b4f51cb3
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Add a SCSI activity indicator.
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2022-11-16 11:31:10 -05:00 |
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Thomas Harte
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2f78a1c7af
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Add SCSI controller inclusion logic.
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2022-09-15 12:17:50 -04:00 |
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Thomas Harte
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dc35ec8fa0
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Merge branch 'master' into AppleIISCSI
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2022-09-15 12:05:58 -04:00 |
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Thomas Harte
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36c3cb1f70
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Deal with pre-ROM03 case, now that it's easy.
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2022-09-13 16:31:06 -04:00 |
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Thomas Harte
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6773a321c1
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Switch to portable direct bitwise logic.
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2022-09-13 16:02:49 -04:00 |
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Thomas Harte
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ffdf44ad4f
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Switch to overt use of std::fill.
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2022-09-13 15:39:17 -04:00 |
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Thomas Harte
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cbfd8e18e8
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Eliminate repetitive magic constants.
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2022-09-02 15:54:16 -04:00 |
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Thomas Harte
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8dc1aca67c
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Add TODO shout-outs.
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2022-08-31 21:20:08 -04:00 |
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Thomas Harte
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df29a50738
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Attempt to support the DMA interface.
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2022-08-31 15:33:48 -04:00 |
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Thomas Harte
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7996fe6dab
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'Clock' the SCSI bus (i.e. make it aware of passing time).
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2022-08-30 16:40:25 -04:00 |
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Thomas Harte
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4df2a29a1f
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Add storage to the bus.
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2022-08-24 15:23:50 -04:00 |
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Thomas Harte
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6010c971a1
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Provide a volume to the SCSI card if one is received.
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2022-08-23 15:11:56 -04:00 |
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Thomas Harte
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ea4bf5f31a
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Provide card's SCSI ID.
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2022-08-23 15:05:36 -04:00 |
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Thomas Harte
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f4c242d5e9
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Attempt to offer centralised C8 region decoding.
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2022-08-23 14:50:44 -04:00 |
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Thomas Harte
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0595773355
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Invents a new virtual select line for extended handling card ROM areas.
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2022-08-23 14:41:45 -04:00 |
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Thomas Harte
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f89ca84902
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Add missing include.
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2022-08-22 21:44:33 -04:00 |
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Thomas Harte
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246bd5a6ac
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Merge branch 'master' into AppleIISCSI
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2022-08-22 17:09:57 -04:00 |
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Thomas Harte
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3c2d01451a
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Remove dead comment.
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2022-08-22 17:01:52 -04:00 |
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Thomas Harte
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c2c81162a1
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Sketch out some of the easy stuff.
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2022-08-22 16:48:51 -04:00 |
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Thomas Harte
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3d234147a6
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Add in collected specs.
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2022-08-22 10:22:19 -04:00 |
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Thomas Harte
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8e7f53751d
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Add Apple II SCSI ROM to the catalogue.
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2022-08-21 22:03:52 -04:00 |
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Thomas Harte
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bfc77f1606
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Add workaround that further isolates whatever bug Spindizzy reveals.
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2022-08-19 16:38:42 -04:00 |
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Thomas Harte
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a6b8285d9c
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Factor out the blitter sequencer.
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2022-08-19 16:38:15 -04:00 |
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Thomas Harte
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837acdcf60
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Experimentally decline immediate blits.
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2022-08-16 21:51:13 -04:00 |
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Thomas Harte
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7289192130
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Fix refresh slots: they're taken, not open.
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2022-08-16 21:51:02 -04:00 |
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Thomas Harte
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bb54ac14b8
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Prove that new output errors are [probably] external to the Blitter.
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2022-08-15 11:10:17 -04:00 |
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Thomas Harte
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856e3d97bf
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Merge branch 'master' into SerialisedBlitter
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2022-08-15 10:54:36 -04:00 |
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Thomas Harte
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94231ca3e3
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Put word-sizing responsibility on the caller.
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2022-08-10 16:41:45 -04:00 |
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Thomas Harte
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e2a8b26b57
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Display properly from greater RAM sizes.
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2022-08-10 16:36:11 -04:00 |
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Thomas Harte
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6d1c954623
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Make ST RAM size selectable, default to 1MB.
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2022-08-10 12:00:06 -04:00 |
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Thomas Harte
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bdb35b6191
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Add an easier hook for debugging.
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2022-08-08 21:00:28 -04:00 |
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Thomas Harte
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892580c183
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Clarify test.
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2022-08-08 15:57:36 -04:00 |
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Thomas Harte
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d4b7d73fc4
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Further reduces lines to one access per slot, max.
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2022-08-07 19:19:00 -04:00 |
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Thomas Harte
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867769f6e7
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Reduces line drawing to two accesses per slot.
Still a fiction, but a better one.
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2022-08-07 19:15:03 -04:00 |
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Thomas Harte
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3781b5eb0e
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Provide further context.
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2022-08-06 14:40:12 -04:00 |
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Thomas Harte
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318cea4ccd
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Attempt a full bus-transaction comparison.
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2022-08-06 10:06:49 -04:00 |
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Thomas Harte
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45892f3584
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Add optional transaction records to the Blitter.
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2022-08-06 09:51:20 -04:00 |
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Thomas Harte
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612413cb1c
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Remove redundant state.
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2022-08-04 10:06:14 -04:00 |
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Thomas Harte
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511ec5a736
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Apply modulos at end of final line.
Possibly I need to rethink the sequence logic?
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2022-07-30 21:35:26 -04:00 |
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Thomas Harte
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4fb9dec381
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Fix use of bool.
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2022-07-30 21:02:44 -04:00 |
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