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10,728 Commits 8 Branches 121 Tags 497 MiB
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35 Commits

Author SHA1 Message Date
Thomas Harte
2b56b7be0d Simplify namespace syntax. 2023-05-10 16:02:18 -05:00
Thomas Harte
55af6681af Avoid unnecessary get_port_input calls. 2021-11-24 17:15:48 -05:00
Thomas Harte
4fc25fb798 Adds basic shift input. 2021-11-07 05:18:54 -08:00
Thomas Harte
29e5ecc282 Add TODOs rather than complete stop on shift register acccesses. 2021-11-02 18:19:31 -07:00
Thomas Harte
5ffe71346c Eliminate interrupt magic constants. 2021-10-29 19:04:06 -07:00
Thomas Harte
eb157f15f3 Adds index hole interrupt. 2021-10-09 04:08:59 -07:00
Thomas Harte
f8380d2d4c Add 8250 feature of 'count, regardless'. 2021-08-08 22:32:41 -04:00
Thomas Harte
b4ec9d70da Adds the CNT input. 2021-08-03 22:19:41 -04:00
Thomas Harte
6210605bc7 Transfers full TOD responsibility onto the chip-specific templates. 2021-08-03 19:10:09 -04:00
Thomas Harte
0245b040b0 Splits TOD storage by model. 
TOD storage will probably end up being a full-on class.
 2021-08-03 18:50:58 -04:00
Thomas Harte
ef58ce6277 Gets a bit more rigorous about the clocking stage. 
Albeit without advancing relative to the test.
 2021-08-02 21:04:00 -04:00
Thomas Harte
15de5e98c4 Adds [partial] test for whether counters are linked. 2021-08-02 20:17:37 -04:00
Thomas Harte
38848ca2db Rationalises reload logic and cuts storage. 
Failure point is now chaining, I think.
 2021-08-02 20:14:01 -04:00
Thomas Harte
77c627e822 Ensure that reading the interrupt flags really clears the master bit. 
Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.
 2021-08-02 07:47:08 -04:00
Thomas Harte
c640132699 Reinstates clocking. 2021-08-01 21:35:08 -04:00
Thomas Harte
57dd38aef2 Reintroduces reload-on-off, adds interrupt delay. 2021-08-01 21:09:02 -04:00
Thomas Harte
460a6cb6fe Attempts a more literal implementation. 2021-08-01 18:14:10 -04:00
Thomas Harte
3d160ce85f Add another potential warning. 2021-07-30 18:21:38 -04:00
Thomas Harte
759007ffc1 Attempts to route CIA interrupts. 2021-07-28 19:36:30 -04:00
Thomas Harte
37a55c3a77 Corrects 6526 interrupt control write. 
This seems to imply that the 6526 should be interrupting too.
 2021-07-28 19:26:02 -04:00
Thomas Harte
bcb7bb5cce Improves logging further. 
To investigate the new perpetual loop.
 2021-07-26 17:02:30 -04:00
Thomas Harte
34d4420e8c Correct reading of top byte of counter 2. 2021-07-25 20:41:15 -04:00
Thomas Harte
fcd6b7b0ea Takes further aim at the conters. 
I think test cases are needed, probably.
 2021-07-24 16:06:49 -04:00
Thomas Harte
ceca32ceb3 Takes a guess at one-shot mode. 2021-07-24 15:53:18 -04:00
Thomas Harte
77a8ddb95c Edges towards working counters. 2021-07-23 22:43:47 -04:00
Thomas Harte
c733a4dbf8 Beefs up interrupt awareness. 2021-07-23 21:58:52 -04:00
Thomas Harte
d898a43dff Implements time-of-day counters, provisionally. 
Interrupts to do.
 2021-07-23 21:24:07 -04:00
Thomas Harte
6123349b79 Stubs in control registers and disables exit-on-miss. 
I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.
 2021-07-22 19:28:01 -04:00
Thomas Harte
56b62a5e49 Adds a dummy interrupt control register. 2021-07-22 16:09:32 -04:00
Thomas Harte
a030d9935e Adds port input. 2021-07-18 20:25:04 -04:00
Thomas Harte
c425dec4d5 Makes some attempt to get as far as the overlay being disabled. 2021-07-18 17:17:41 -04:00
Thomas Harte
67d53601d5 Latch and return data direction. 
Albeit with no port-handling effect yet.
 2021-07-18 12:23:47 -04:00
Thomas Harte
622cca0acf Adds sufficient address decoding to print a more helpful exit message. 2021-07-18 12:13:56 -04:00
Thomas Harte
48999c03a5 Adds concept of time, captured port handler. 2021-07-18 11:49:10 -04:00
Thomas Harte
377cc7bdcd Start to introduce a 6526/8250. 2021-07-18 11:36:13 -04:00