Thomas Harte
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c2253c1e0f
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Fixed multiplier: the dot clock I've used to instantiate the CRT is the pixel clock, not the character clock.
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2017-07-31 22:17:46 -04:00 |
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Thomas Harte
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5c68b6cc21
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Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.
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2017-07-31 22:16:08 -04:00 |
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Thomas Harte
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ffaa627820
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Fixed frame restart when there is no adjustment period.
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2017-07-31 22:13:45 -04:00 |
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Thomas Harte
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f742fd5d4a
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Made basic attempt to get something on screen: white where the display is enabled, black for the border.
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2017-07-31 22:13:20 -04:00 |
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Thomas Harte
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69b99fe127
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Transferred ownership of the CRT to the CRTC bus handler, to give it easy access.
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2017-07-31 22:04:52 -04:00 |
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Thomas Harte
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5a396f6787
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Added an explicit cast.
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2017-07-31 22:04:31 -04:00 |
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Thomas Harte
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cb0dc7b434
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I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
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2017-07-31 22:01:54 -04:00 |
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Thomas Harte
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e28829bd1b
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Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
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2017-07-31 20:14:46 -04:00 |
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Thomas Harte
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68ceeab610
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Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
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2017-07-31 19:56:59 -04:00 |
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Thomas Harte
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68dca9d047
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Made a first attempt at ROM paging, with pretty much the same scheme that'll be needed for 128kb support.
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2017-07-31 19:37:28 -04:00 |
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Thomas Harte
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d88ca151f4
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Added a first attempt at output port decoding. Just logging for now.
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2017-07-31 19:25:10 -04:00 |
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Thomas Harte
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3c90218c3d
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With a very basic stab at something a bit like the memory map (sans paging), execution begins.
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2017-07-31 19:15:43 -04:00 |
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Thomas Harte
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afd409c883
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Ensured that ROM images are loaded and passed to the Amstrad CPC.
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2017-07-31 18:44:49 -04:00 |
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Thomas Harte
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26b6c03a2a
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Re-enabled the address sanitiser as a development tool.
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2017-07-31 07:30:07 -04:00 |
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Thomas Harte
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9c04d851e4
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Added the basics necessary to get the CPU ticking over, at a nominal 4Mhz but with the wait states that I currently believe to be accurate.
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2017-07-31 07:29:50 -04:00 |
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Thomas Harte
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1d6fe11906
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Added an instance of Outputs::CRT::CRT. So progress is now: select CDT, up comes a blank window.
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2017-07-31 07:16:51 -04:00 |
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Thomas Harte
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c0f1313830
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Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.
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2017-07-30 22:05:29 -04:00 |
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Thomas Harte
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fb51fadf00
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Merge branch 'master' into CPC
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2017-07-30 21:29:31 -04:00 |
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Thomas Harte
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55fd9122d0
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Slightly relaxed vertical sync testing.
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2017-07-30 21:19:42 -04:00 |
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Thomas Harte
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5b5720fac0
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Added to the static analyser the most basic through-path for Amstrad CPC content.
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2017-07-30 21:15:20 -04:00 |
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Thomas Harte
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d25d7d7d40
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Added the Amstrad CPC as a named target and declared support for its CDT file format.
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2017-07-29 21:56:33 -04:00 |
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Thomas Harte
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ba4f2d8917
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Merge branch 'master' into VerticalSync
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2017-07-29 21:45:22 -04:00 |
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Thomas Harte
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a2aec39633
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Merge pull request #167 from TomHarte/VerticalSync
Adjusts vertical sync detection
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2017-07-29 21:44:47 -04:00 |
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Thomas Harte
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0bf4fdc9af
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Simplified slightly.
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2017-07-29 21:37:59 -04:00 |
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Thomas Harte
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ed8c73eb14
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Ensured lengthy constant sync can't appear to be two sync pulses, regardless of other interruption.
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2017-07-29 18:25:04 -04:00 |
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Thomas Harte
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3528a7f78b
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Made an attempt at triggering vertical sync the expected number of time after it begins, regardless of total length.
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2017-07-29 17:33:52 -04:00 |
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Thomas Harte
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54bcc40192
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With an eye towards being more accurate as to vertical sync recognition: acknowledged that the detection period varies between PAL and NTSC.
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2017-07-29 14:53:53 -04:00 |
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Thomas Harte
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4b5e9ffb83
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Ensured is_at_end_ is initially cleared by default.
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2017-07-27 22:22:43 -04:00 |
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Thomas Harte
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a7f5f035a6
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Merge pull request #166 from TomHarte/NoRefs
Standardises on `const [Half]Cycles`
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2017-07-27 22:07:05 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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1fb158b297
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Merge pull request #165 from TomHarte/HalfCycleTyper
Brings `Typer` into the new `run_for` orthodoxy
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2017-07-27 21:56:02 -04:00 |
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Thomas Harte
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968d2bb8ba
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Brought Typer into the new run_for orthodoxy, making it easier to clock consistently regardless of unit. Which necessitated adding a negative operator for WrappedInts.
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2017-07-27 21:53:45 -04:00 |
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Thomas Harte
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92a3dfe44a
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Merge pull request #164 from TomHarte/NoInt
Revokes the operator bool() on WrappedInt and simplifies/generalises HalfClockReceiver
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2017-07-27 21:41:04 -04:00 |
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Thomas Harte
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9ef232157b
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Revoked the operator bool() on WrappedInt as providing an indirect means for implicit but incorrect assignment to unwrapped ints. Got explicit about run_for intention and simplified HalfClockReceiver slightly by building a lossy and a flushing conversion to Cycles into HalfCycles. Adapted the all-RAM Z80 properly to return HalfCycles.
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2017-07-27 21:38:50 -04:00 |
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Thomas Harte
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b9f4f7a530
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Merge pull request #163 from TomHarte/WaitSampling
Adjusts the timing of the Z80's wait line sampling to be on a half clock and better regularises 'action' partial bus cycles
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2017-07-27 21:19:29 -04:00 |
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Thomas Harte
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761afad118
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Corrected timestamp return, and its testing by the 6502 timing tests.
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2017-07-27 21:19:16 -04:00 |
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Thomas Harte
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8848ebbd4f
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Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81.
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2017-07-27 21:10:14 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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25fd95044c
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Merge pull request #154 from TomHarte/Memptr
Introduces a subset of necessary test cases for the Z80 memptr register, and corrects implementation to match
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2017-07-27 08:10:22 -04:00 |
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Thomas Harte
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1da24d10fd
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Corrected a couple of build errors.
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2017-07-27 08:05:14 -04:00 |
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Thomas Harte
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60e374dca3
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Merge branch 'master' into Memptr
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2017-07-27 07:54:25 -04:00 |
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Thomas Harte
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7a65f91575
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Merge pull request #162 from TomHarte/ClockReceiverHolder
Completes revocation of ClockReceiver
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2017-07-27 07:43:12 -04:00 |
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Thomas Harte
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6f8b558724
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Revoked dead #include.
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2017-07-27 07:41:59 -04:00 |
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Thomas Harte
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1a88b62bf7
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Merge branch 'master' into ClockReceiverHolder
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2017-07-27 07:41:20 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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273299028e
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Merge pull request #161 from TomHarte/Z80WaitSampling
Doubles the timing precision used by the Z80 up to HalfCycles
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2017-07-27 07:39:36 -04:00 |
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Thomas Harte
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847e49ccdf
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Corrected timestamp reporting by the all-RAM Z80.
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2017-07-26 19:47:39 -04:00 |
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Thomas Harte
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81a3899381
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Adjusted the Z80 formally to communicate in terms of half cycles rather than whole.
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2017-07-26 19:42:00 -04:00 |
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Thomas Harte
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9257a3f6d7
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Added test for 16-bit arithmetic, and fixed implementation.
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2017-07-26 19:04:52 -04:00 |
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Thomas Harte
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728143247d
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Added a test for RLD and RRD. Which already passes.
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2017-07-26 18:56:35 -04:00 |
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