59 Commits

Author	SHA1	Message	Date
Thomas Harte	cb77519af8	Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.	2022-05-20 12:40:09 -04:00
Thomas Harte	e4c0a89889	Just use the four-bit register number directly.	2022-05-19 15:01:09 -04:00
Thomas Harte	3db2de7478	Works 68000 mk2 into the comparative tests. ... ... revealing that I've leant a little too hard on __LINE__.	2022-05-16 20:04:13 -04:00
Thomas Harte	ff8e4754d7	Ensure STOP exits the run loop.	2022-05-14 19:17:32 -04:00
Thomas Harte	27c4d19455	Support STOP.	2022-05-14 11:35:35 -04:00
Thomas Harte	77b56c50e6	Ensure you can't trace into divide-by-zero, etc.	2022-05-13 14:02:56 -04:00
Thomas Harte	002a8c061f	Trim the public interface of Executor.	2022-05-13 13:55:37 -04:00
Thomas Harte	4299334e24	Clean up some TODOs, eliminate one further conditional.	2022-05-13 11:17:57 -04:00
Thomas Harte	4d03c73222	Ensure that the first instruction of privilege/line1010/etc exceptions isn't traced.	2022-05-13 11:08:22 -04:00
Thomas Harte	6c854e8ecc	Simplify is_supervisor semantics.	2022-05-13 07:53:40 -04:00
Thomas Harte	2e796f31d4	Support interrupts; documentation to come.	2022-05-12 20:52:24 -04:00
Thomas Harte	f3c1b1f052	Name flags, remove closing underscores on exposed data fields.	2022-05-12 08:19:41 -04:00
Thomas Harte	96af3d5ec5	Fix infinite inner/outer loop.	2022-05-11 10:26:12 -04:00
Thomas Harte	69ba14e34e	Support the trace flag.	2022-05-11 09:39:15 -04:00
Thomas Harte	943c924382	Add missing: MOVE to/from USP, RESET.	2022-05-11 07:52:23 -04:00
Thomas Harte	ab8e1fdcbf	Take a swing at access faults and address errors.	2022-05-10 16:20:30 -04:00
Thomas Harte	7445c617bc	Start removing 68000-specific timing calculations.	2022-05-09 20:32:02 -04:00
Thomas Harte	2ca1eb4cf8	Move set_pc into the operation-specific group.	2022-05-09 16:20:15 -04:00
Thomas Harte	0af8660181	Remove add_pc and decline_branch in favour of operation-specific signals.	2022-05-09 16:19:25 -04:00
Thomas Harte	539932dc56	Provide function codes. TODO: optionally.	2022-05-09 09:18:02 -04:00
Thomas Harte	e35de357fa	Route reads and writes through a common path.	2022-05-08 17:17:46 -04:00
Thomas Harte	bf8c97abbb	Permit TRAP, TRAPV and CHK to push the next PC rather than the current.	2022-05-07 20:32:39 -04:00
Thomas Harte	ad6cf5e401	Pull out magic constant, simplify sp and TAS.	2022-05-07 20:20:24 -04:00
Thomas Harte	2b3900fd14	Fix LINK A7.	2022-05-07 08:15:26 -04:00
Thomas Harte	1defeca1ad	Implement RTS, RTR, RTE.	2022-05-06 12:30:49 -04:00
Thomas Harte	ac6a9ab631	Fix TAS Dn.	2022-05-06 12:23:04 -04:00
Thomas Harte	8176bb6f79	Expose issues with TST and TAS.	2022-05-06 12:18:56 -04:00
Thomas Harte	9c266d4316	Proceed to unimplemented TST.	2022-05-06 11:33:57 -04:00
Thomas Harte	190a351a29	Fix address writeback.	2022-05-06 09:56:01 -04:00
Thomas Harte	607ddd2f78	Preserve MOVEM order in Operation.	2022-05-06 09:45:06 -04:00
Thomas Harte	fed79a116f	Be overt about the size being described here.	2022-05-06 09:22:38 -04:00
Thomas Harte	5db0ea0236	Add note for my tomorrow self.	2022-05-05 21:11:02 -04:00
Thomas Harte	06fe320cc0	Correct source counting, but this leaves the operands still being the wrong way around.	2022-05-05 21:06:53 -04:00
Thomas Harte	f7991e18de	Makes a failed attempt to implement MOVEM to registers.	2022-05-05 20:32:21 -04:00
Thomas Harte	d7d0a5c15e	Implement MOVEM to memory.	2022-05-05 18:51:29 -04:00
Thomas Harte	47f4bbeec6	Switch to a contiguous block of 16 registers.	2022-05-05 15:31:59 -04:00
Thomas Harte	9ab70b340c	Route MOVEM appropriately.	2022-05-05 12:42:57 -04:00
Thomas Harte	70cdc2ca9f	Fix MOVEP to register. ... Advance to lack of MOVEM.	2022-05-05 12:37:47 -04:00
Thomas Harte	67462c2f92	Rewire MOVEP.	2022-05-05 12:27:36 -04:00
Thomas Harte	4a4e786060	Hit a realisation: write-back isn't going to work with MOVEP as formulated.	2022-05-05 09:26:26 -04:00
Thomas Harte	5d1d94848c	Take a bash at LINK and UNLK.	2022-05-04 08:26:11 -04:00
Thomas Harte	052ba80fd7	Add enough wiring to complete but fail EXT and JMP/JSR.	2022-05-03 15:49:55 -04:00
Thomas Harte	af973138df	Correct decoding of Bcc.b, satisfying Bcc and BSR tests.	2022-05-03 15:32:54 -04:00
Thomas Harte	5a87506f3d	Fix Bcc, making decision that add_pc is relative to start of instruction.	2022-05-03 15:21:42 -04:00
Thomas Harte	d8b3748d24	Fix Scc size, DBcc behaviour.	2022-05-03 14:40:51 -04:00
Thomas Harte	b3cf13775b	Consume operand_flags into Instruction.hpp.	2022-05-03 11:09:57 -04:00
Thomas Harte	1bb809098c	Switch — messily — to a more compact way of indicating sequence.	2022-05-03 09:04:54 -04:00
Thomas Harte	011506f00d	Add basic exceptions.	2022-05-02 21:27:58 -04:00
Thomas Harte	25ab478461	Fix immediate byte and word fetches.	2022-05-02 20:17:44 -04:00
Thomas Harte	7efe30f34c	Fix (d8, _, Xn) calculation.	2022-05-02 15:09:59 -04:00