Federico Berti
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1a26d4e409
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Update nbcd_pea.json
Add missing bracket
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2022-05-23 12:14:00 +01:00 |
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Thomas Harte
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c8ede400eb
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Fix RTE.
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2022-05-22 21:17:28 -04:00 |
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Thomas Harte
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269263eecf
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Implement RTE, RTS, RTR.
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2022-05-22 21:16:38 -04:00 |
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Thomas Harte
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4e21cdfc63
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Enable NEGX/CLR tests.
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2022-05-22 20:55:21 -04:00 |
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Thomas Harte
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faef5633f8
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Ensure MOVE from SR has an effective address to write to.
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2022-05-22 20:52:00 -04:00 |
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Thomas Harte
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7d1f1a3175
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Implement MOVE [to/from] [CCR/SR].
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2022-05-22 19:45:22 -04:00 |
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Thomas Harte
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4e34727195
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Fully implement TAS.
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2022-05-22 16:14:03 -04:00 |
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Thomas Harte
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1dd6ed6ae3
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Implement TAS Dn, with detour for other TASes.
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2022-05-22 16:08:30 -04:00 |
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Thomas Harte
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cb4d6710df
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Switch to a more direct indication of progress.
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2022-05-22 11:27:58 -04:00 |
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Thomas Harte
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3b68b9a83b
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Implement PEA.
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2022-05-22 11:27:38 -04:00 |
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Thomas Harte
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4279ce87ea
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Implement LEA.
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2022-05-22 08:29:12 -04:00 |
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Thomas Harte
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3c1c4f89e9
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Add MULU/S functionality, though not timing.
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2022-05-22 08:02:32 -04:00 |
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Thomas Harte
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4a6512f5d5
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Reduce dispatch boilerplate.
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2022-05-22 07:39:16 -04:00 |
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Thomas Harte
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284f23c6ea
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Implement JMP.
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2022-05-22 07:16:38 -04:00 |
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Thomas Harte
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11a9a5c126
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Use common macros for the two forms of Perform.
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2022-05-22 07:08:14 -04:00 |
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Thomas Harte
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4993801741
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Add missing prefetch to BSET, BCHG, BCLR.
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2022-05-21 21:05:05 -04:00 |
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Thomas Harte
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4b35899a12
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Bcc: properly establish offset.
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2022-05-21 20:59:34 -04:00 |
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Thomas Harte
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1304e930eb
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DBcc is two-operand.
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2022-05-21 20:06:03 -04:00 |
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Thomas Harte
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94288d5a94
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Excludes DBcc from standard operand fetch.
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2022-05-21 19:53:28 -04:00 |
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Thomas Harte
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3811ab1b82
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Fix the two 8bit-with-displacement effective address Calc steps.
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2022-05-21 16:20:01 -04:00 |
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Thomas Harte
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c869eb1eec
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Correct omission: wasn't testing the final PC.
Plenty of new errors incoming.
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2022-05-21 15:56:27 -04:00 |
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Thomas Harte
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f97d2a0eb9
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Add DIVU/DIVS, at least as far as getting the correct numeric result.
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2022-05-21 15:56:09 -04:00 |
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Thomas Harte
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176c8355cb
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The tests in chk.json now pass.
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2022-05-21 14:32:58 -04:00 |
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Thomas Harte
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2258434326
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Ensure proper return addresses are calculated for JSR.
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2022-05-21 14:28:44 -04:00 |
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Thomas Harte
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e46a3c4046
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Implement JSR.
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2022-05-21 10:29:36 -04:00 |
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Thomas Harte
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0e4cfde657
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Fix MOVEM predec.
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2022-05-21 08:17:39 -04:00 |
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Thomas Harte
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4bd9c36922
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Fix postincrement mode.
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2022-05-20 21:01:23 -04:00 |
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Thomas Harte
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256da43fe5
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Fix MOVEM other than postinc and predec.
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2022-05-20 20:47:54 -04:00 |
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Thomas Harte
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6a442e0136
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MOVEM has an immediate first operand.
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2022-05-20 20:34:51 -04:00 |
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Thomas Harte
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a818650027
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Add a faulty attempt at MOVEM.
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2022-05-20 18:48:19 -04:00 |
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Thomas Harte
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9d79e64f5c
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Add a mere calculate effective address pathway.
Plus a lot of waffle to try to justify the further code duplication.
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2022-05-20 16:23:52 -04:00 |
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Thomas Harte
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c7c12f9638
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After a quick check, eori_andi_ori also now passes.
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2022-05-20 14:47:11 -04:00 |
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Thomas Harte
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ee942c5c17
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Fix PC-relative fetches.
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2022-05-20 14:42:51 -04:00 |
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Thomas Harte
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d157819c49
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Implement the various to-[SR/CCR] actions, which do a 'repeat' prefetch.
(which isn't exactly a repeat, at least in the SR cases, because the function code might have changed)
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2022-05-20 14:29:14 -04:00 |
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Thomas Harte
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2d91fb5441
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Implement MOVEP.
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2022-05-20 14:22:32 -04:00 |
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Thomas Harte
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81431a5453
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Attempt BTST, BCHG, BCLR and BSET.
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2022-05-20 12:58:45 -04:00 |
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Thomas Harte
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6d7ec07216
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Uncover another three already-working test files.
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2022-05-20 12:44:57 -04:00 |
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Thomas Harte
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b4978d1452
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Implement BSR, adding one more test file to the working set.
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2022-05-20 12:40:35 -04:00 |
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Thomas Harte
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cb77519af8
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Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.
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2022-05-20 12:40:09 -04:00 |
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Thomas Harte
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45e9648b8c
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Implement Bcc.
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2022-05-20 12:04:43 -04:00 |
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Thomas Harte
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ce32957d9d
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Shuffle two more into the working column.
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2022-05-20 11:53:12 -04:00 |
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Thomas Harte
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ba8592ceae
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At least on the 68000, Scc is read-modify-write.
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2022-05-20 11:43:26 -04:00 |
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Thomas Harte
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4327af3760
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DBcc: add write-back.
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2022-05-20 11:37:18 -04:00 |
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Thomas Harte
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860cc63e21
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Attempt DBcc.
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2022-05-20 11:32:06 -04:00 |
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Thomas Harte
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452dd3ccfd
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Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
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2022-05-20 11:20:23 -04:00 |
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Thomas Harte
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e5c1621382
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Add missing fallthrough , patterns for all ADDs and SUBs.
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2022-05-20 07:02:02 -04:00 |
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Thomas Harte
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af3518dc1f
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Implement various ADD, SUB patterns.
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2022-05-19 20:50:37 -04:00 |
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Thomas Harte
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6cfc0e80d9
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Don't test the unrecognised instruction exception.
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2022-05-19 19:45:38 -04:00 |
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Thomas Harte
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1ee9c585ca
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Fix segue into second operand.
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2022-05-19 19:38:42 -04:00 |
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Thomas Harte
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efe5a5ac26
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Signal will_perform even for invalid instructions.
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2022-05-19 18:50:43 -04:00 |
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