6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-07-04 18:29:40 +00:00
Code Issues Projects Releases Wiki Activity
9,908 Commits 10 Branches 118 Tags 495 MiB
d1f929e6f7
Commit Graph

9908 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Thomas Harte
d1f929e6f7 Just do a multiply and divide. Easy. 2023-01-21 14:19:52 -05:00
Thomas Harte
c9643c4145 Log memory control meaningfully. 2023-01-21 14:13:02 -05:00
Thomas Harte
e289e6e757 Catch and map Yamaha palette entries. 
It's one less thing in the uncaptured log.
 2023-01-21 14:12:46 -05:00
Thomas Harte
a726c9d97a Enable indirect register writes. 2023-01-20 23:14:57 -05:00
Thomas Harte
c77e7c268f 1 = disable, 0 = enable. 2023-01-20 23:08:41 -05:00
Thomas Harte
9c57bfd58d Attempt to log dropped indirect writes. 2023-01-20 23:07:14 -05:00
Thomas Harte
4efda108c6 Transcribe the Yamaha 9938 register meanings. 2023-01-20 23:00:33 -05:00
Thomas Harte
191cf4829b Attempt real blank reporting. 2023-01-20 22:29:49 -05:00
Thomas Harte
9b7a925816 Give clearer names to the two pointers. 2023-01-20 20:29:15 -05:00
Thomas Harte
392b0acb58 Pull everything out of master_system_ struct. 
Now that it's inherently collected in the relevant `Storage`.
 2023-01-19 15:09:16 -05:00
Thomas Harte
4b7606894e Move Master System state, and start simplifying. 2023-01-19 14:09:31 -05:00
Thomas Harte
1fb94d15ab No need for this-> ugliness in Base methods. 2023-01-19 12:32:42 -05:00
Thomas Harte
348c42bdea Start trying to bluff my way through extended status. 2023-01-18 22:23:19 -05:00
Thomas Harte
e450e53c4e Temporarily copy and paste my way to further logging. 2023-01-18 14:59:30 -05:00
Thomas Harte
355ee7fbc7 Adjust factoring of read and write per expanded V9938 scope. 2023-01-18 12:36:57 -05:00
Thomas Harte
339086d597 The Yamaha chips have more ports. 2023-01-17 22:29:17 -05:00
Thomas Harte
f0b1c34db2
Merge pull request #1116 from TomHarte/RP5C01 
More fully implement the RP-5C01.
 2023-01-17 22:25:17 -05:00
Thomas Harte
7b25fe5f61 Make read consistent. 2023-01-17 21:18:56 -05:00
Thomas Harte
194b5bc36a Attempt to deal with hours correctly. 2023-01-17 21:12:00 -05:00
Thomas Harte
0951c50e40 Further explain. 2023-01-17 20:14:32 -05:00
Thomas Harte
9588c9bee2 Merge branch 'RP5C01' of github.com:TomHarte/CLK into RP5C01 2023-01-17 18:53:30 -05:00
Thomas Harte
6f973fc605 Attempt some use of NumericCoder. 2023-01-17 18:53:26 -05:00
Thomas Harte
eb51ed9ae8 Shift ownership of initial values. 2023-01-17 17:36:15 -05:00
Thomas Harte
83cf4497dd Split encode and decode for clearer naming. 2023-01-17 17:33:52 -05:00
Thomas Harte
f6e601daff Introduce a template for numeric coding. 2023-01-17 13:26:11 -05:00
Thomas Harte
bb6ceafe0e Implement the easy writes. 2023-01-16 22:31:03 -05:00
Thomas Harte
55e73cb812 Implement most of reading. 2023-01-16 22:25:20 -05:00
Thomas Harte
f0db676a10 Be consistent in use of C parts. 2023-01-16 20:29:32 -05:00
Thomas Harte
32b29bd63b Transcribe all missing registers. 2023-01-16 20:26:27 -05:00
Thomas Harte
bfe94eb268 Seed date and time with current. 2023-01-16 20:11:42 -05:00
Thomas Harte
20ec192129
Merge pull request #1114 from TomHarte/SecondarySlots 
Add support for secondary MSX slots.
 2023-01-16 20:01:21 -05:00
Thomas Harte
055e9cdf8d Differentiate unmapped and mapped-for-handler. 2023-01-16 19:52:40 -05:00
Thomas Harte
a5b9bdc18c Eliminate speculative apply_mapping. 2023-01-16 11:53:04 -05:00
Thomas Harte
eb51ff5cdf Add RAM paging. 2023-01-16 11:52:08 -05:00
Thomas Harte
1769c24531 Avoid ambiguous naming. 2023-01-16 11:43:43 -05:00
Thomas Harte
1a58ddaa67 Increase notes for future self. 2023-01-15 23:12:36 -05:00
Thomas Harte
183cb519e7 Give autonomy to secondary slots. 2023-01-15 22:51:17 -05:00
Thomas Harte
68361913ee Substitute VDP for the MSX 2. 2023-01-14 22:05:59 -05:00
Thomas Harte
ced002125e Make a basic attempt at RAM. 2023-01-14 14:58:12 -05:00
Thomas Harte
1e17fc71ab Add an RP-5C01 to the MSX 2. 2023-01-14 14:52:07 -05:00
Thomas Harte
f57c2a961f Add to further project files. 2023-01-14 14:20:29 -05:00
Thomas Harte
48a4355592 Start sketching out an RP5C01. 2023-01-14 14:17:28 -05:00
Thomas Harte
3bc38d35c9 Fix include order. 2023-01-14 14:16:56 -05:00
Thomas Harte
4d67360702 Merge branch 'master' into SecondarySlots 2023-01-13 22:23:54 -05:00
Thomas Harte
18def0c97d Correct extension ROM visibility. 2023-01-13 22:22:58 -05:00
Thomas Harte
84cb7df1be
Merge pull request #1115 from TomHarte/DynamicCull 
Restore repeated lookup of timed machine under macOS.
 2023-01-13 22:08:29 -05:00
Thomas Harte
97d93ad55c Restore repeated lookup of timed machine. 
This restores culling of abandoned parallel machines during dynamic analysis.
 2023-01-13 22:02:56 -05:00
Thomas Harte
5f85074caa Restore repeated lookup of timed machine. 
This restores culling of abandoned parallel machines during dynamic analysis.
 2023-01-13 22:02:15 -05:00
Thomas Harte
f0a4d1d8ec Wire up did-page notifications. 2023-01-13 21:54:59 -05:00
Thomas Harte
fb0241cf6e Be overt about alignment. 2023-01-13 14:30:17 -05:00