Thomas Harte
acd9df6745
Fix segment/offset sizes for far calls.
2022-03-09 15:23:43 -05:00
Thomas Harte
f96c051932
Record PUSH immediate operation size.
2022-03-09 14:24:57 -05:00
Thomas Harte
67b2e40fae
Fixed: INs and OUTs remain single byte.
2022-03-09 10:51:16 -05:00
Thomas Harte
081a2acd61
Fix shift group operand size.
2022-03-09 09:33:25 -05:00
Thomas Harte
de79acc790
Fix RegAddr/AddrRegs and group 2 decoding.
2022-03-09 08:38:34 -05:00
Thomas Harte
a125bc7242
Fill in more of test32bitSequence.
2022-03-08 20:16:19 -05:00
Thomas Harte
ebed4cd728
Introduce failing 32-bit parsing test.
2022-03-08 19:57:10 -05:00
Thomas Harte
926a373591
Extend SIB test, correct decoder.
2022-03-08 15:03:37 -05:00
Thomas Harte
0cbb481fa4
Add a formal SIB test.
2022-03-08 14:56:27 -05:00
Thomas Harte
a954f23642
Attempt 32-bit modregrm + SIB parsing.
2022-03-08 14:39:49 -05:00
Thomas Harte
e7aaf4dd2e
Add LDS, LES, LSS test.
2022-03-06 12:10:25 -05:00
Thomas Harte
8a0902a83b
Adapts existing opcodes for 32-bit parsing.
2022-03-05 13:52:07 -05:00
Thomas Harte
8080d1d961
Extend test case slightly.
2022-03-01 20:22:43 -05:00
Thomas Harte
8ee62b4789
Simplify address size semantics.
...
Since it'll no longer be a mode-dependant toggle, but a fully-retained value.
2022-03-01 17:29:26 -05:00
Thomas Harte
5e7a142ff1
Fix is_write errors, update comment, add additional source for asserts.
2022-03-01 16:51:54 -05:00
Thomas Harte
d8601ef01f
Add missing hex specifier. Test now passes.
2022-02-28 09:54:29 -05:00
Thomas Harte
afbc57cc0c
Incorporate displacement, switch macro flag.
2022-02-28 09:53:23 -05:00
Thomas Harte
9f12c009d6
Correct data size when accessing address registers.
2022-02-27 19:45:03 -05:00
Thomas Harte
84ac68a58b
Fix indirect memory read/write
2022-02-27 18:43:00 -05:00
Thomas Harte
27d1df4699
Introduce enough of a DataPointerResolver test to build but fail.
2022-02-27 18:27:58 -05:00
Thomas Harte
0d7a7dc7c9
Introduce DataPointerResolver, to codify the meaning of DataPointer and validate that enough information is present.
2022-02-27 11:25:02 -05:00
Thomas Harte
60bf1ef7ea
Rename SourceSIB to DataPointer, extend to allow for an absent base.
2022-02-23 08:28:20 -05:00
Thomas Harte
dc37b692cf
Switch to templated test function.
2022-02-23 04:33:28 -05:00
Thomas Harte
76814588b8
Template Instruction on its content size.
2022-02-21 12:36:03 -05:00
Thomas Harte
1934c7faa2
Switch Decoder into a template.
2022-02-21 12:21:57 -05:00
Thomas Harte
9e9e160c43
Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.
2022-02-21 11:45:46 -05:00
Thomas Harte
a5113998e2
Accept that IN and OUT are going to have special semantics, thereby kill ::AX and ::DX.
2022-02-20 17:15:01 -05:00
Thomas Harte
c257b91552
Update tests to preference away from [A/B/C/D]L.
2022-02-18 16:32:28 -05:00
Thomas Harte
1c3935eb40
Add README.md
...
As a warning.
2021-12-07 18:19:51 -05:00
Thomas Harte
610c85a354
Correct test logic.
...
All tests now pass.
2021-11-25 04:11:20 -05:00
Thomas Harte
012084b37b
Fix exclusive fill, sizing, eliminate ECS call-ins.
...
The clock test now proceeds further, but still doesn't seem to pass.
2021-11-24 17:25:32 -05:00
Thomas Harte
8ef9a932aa
Adds inclusive fill test; fixes inclusive fills.
2021-11-07 14:26:13 -08:00
Thomas Harte
2c1f2edcf2
Introduce failing 'clock' test case.
...
i.e. a few seconds of the Workbench 1.0 clock application.
2021-10-31 16:12:51 -07:00
Thomas Harte
9e6ffaad7d
Introduce test case for fill mode.
2021-10-31 14:12:26 -07:00
Thomas Harte
edb75e69cb
Implement bitplane modulos.
2021-10-29 11:29:22 -07:00
Thomas Harte
5ebc59dd1f
Introduce additional test cases.
2021-10-26 20:58:38 -07:00
Thomas Harte
4d7ce3792f
Use additional test cases.
2021-10-25 21:48:43 -07:00
Thomas Harte
dc8701a929
Introduce some additional Blitter test cases.
2021-10-25 21:40:20 -07:00
Thomas Harte
15ed4a0d09
Introduce failing test case for sector decoding.
2021-10-16 10:48:32 -07:00
Thomas Harte
aa6b0f07b7
Correct filename.
2021-10-16 05:37:46 -07:00
Thomas Harte
6b0dd19442
Name file appropriately: the logo comes from Kickstart.
2021-10-09 08:02:15 -07:00
Thomas Harte
da286d5ae8
Switch spaces to tabs.
2021-10-04 05:27:25 -07:00
Thomas Harte
ad90c6b6ce
Now that this is getting close, don't stop at the first error.
2021-09-29 22:19:34 -04:00
Thomas Harte
0c998d60cb
Correct test logic for line draws that repeatedly write to the same address.
2021-09-28 21:45:55 -04:00
Thomas Harte
1dfc36f311
Flip loop, add modulo mappings.
2021-09-26 18:15:32 -04:00
Thomas Harte
1c03ff1d37
Fix bltdptl to bltbptl misstatement; remove pre-DMA writes.
2021-09-26 18:14:50 -04:00
Thomas Harte
19dd2f92bd
Implements test case. Failing at present, naturally.
2021-09-25 21:52:41 -04:00
Thomas Harte
acfaa016a0
Adds a capture of traffic leading up to the Workbench boot logo.
...
Around which to construct a test case.
2021-09-25 18:10:07 -04:00
Thomas Harte
fa800bb809
Introduces code for minterm application.
2021-09-20 19:13:23 -04:00
Thomas Harte
e402e690b0
Assume and test that divide-by-zero posts the PC of the offending instruction.
2021-08-07 17:51:00 -04:00
Thomas Harte
b4ec9d70da
Adds the CNT input.
2021-08-03 22:19:41 -04:00
Thomas Harte
738999a8b7
Further expands list of applied tests.
2021-08-03 22:08:50 -04:00
Thomas Harte
34c1cc5693
Adds entry points for all remaining tests.
...
Failing now: the TB123s, which are TOD related, both CIA2 tests, and CIA1TAB (which I think needs me to implement Port B output toggling).
2021-08-03 17:19:35 -04:00
Thomas Harte
f0ef45f0ca
Introduces two further tests.
2021-08-03 16:58:51 -04:00
Thomas Harte
f576baf214
I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests.
2021-07-30 21:21:16 -04:00
Thomas Harte
94907b51aa
Remove redundant parameter.
2021-07-06 20:47:49 -04:00
Thomas Harte
0085265d13
Test for a longer period; fix expected tone 1 count.
2021-07-06 20:46:22 -04:00
Thomas Harte
8e0893bd42
Clarifies control flow.
2021-07-06 20:28:32 -04:00
Thomas Harte
704dc9bdcb
Improves test, to assert that state toggles happen at interrupts.
2021-07-06 20:25:32 -04:00
Thomas Harte
3e6b804896
Switches to linked 1/50/1000 Hz timers, and per-interrupt state toggling.
2021-07-06 20:12:44 -04:00
Thomas Harte
f371221dba
Add a quick test of tone generator 1.
2021-07-02 23:57:11 -04:00
Thomas Harte
27b0579ec6
Avoid stack-error test case.
...
Also test that the interrupt is generated on the downward stroke.
2021-07-02 23:55:43 -04:00
Thomas Harte
283092cfbc
With a unit test in aid, corrects some lingering TimedInterruptSource issues.
2021-07-02 23:41:19 -04:00
Thomas Harte
fbf1adef05
Introduces unit test and thereby seemingly fixes get_next_sequence_point.
...
There's still improper output in the actual machine though, so maybe something else is afoot?
2021-06-18 17:44:17 -04:00
Thomas Harte
f27e331462
Updates autotests to new RomFetcher world.
2021-06-06 20:34:55 -04:00
Thomas Harte
37dcf61130
Add timing tests, fix +3 discrepancy.
2021-04-23 22:29:57 -04:00
Thomas Harte
a1511f9600
Establishes that the 48/128kb contention patterns can be derived from my partial machine cycles alone.
2021-04-14 20:15:40 -04:00
Thomas Harte
68a04f4e6a
Adds IN/OUT I/D [R] to complete tests.
2021-04-13 22:00:24 -04:00
Thomas Harte
0d61902b10
Adds CP[I/D/IR/DR] tests.
2021-04-13 20:03:11 -04:00
Thomas Harte
3eec210b30
Adds LDI/LDD/LDIR/LDDR tests.
2021-04-13 20:00:29 -04:00
Thomas Harte
2e70b5eb9f
Advances to EX (SP), HL, leaving only [LD/CP/IN/OT][I/D]{R}.
2021-04-13 19:45:29 -04:00
Thomas Harte
8a3bfb8672
Adds an IN/OUT test.
2021-04-13 17:55:51 -04:00
Thomas Harte
06f1e64177
Advances to IO.
2021-04-12 21:41:20 -04:00
Thomas Harte
b42780173a
Establishes that there really is no Read4 and Read4Pre distinction.
...
Will finish these unit tests, then clean up.
2021-04-12 20:54:10 -04:00
Thomas Harte
36c8821c4c
Reaches the halfway point in tests.
2021-04-12 17:29:03 -04:00
Thomas Harte
9347fe5f44
Advances to next failing test: LD (ii+n), n.
2021-04-12 17:11:58 -04:00
Thomas Harte
e82367def3
Switches to test-conformant behaviour for (IX/IY+n) opcode fetches.
2021-04-11 23:01:00 -04:00
Thomas Harte
47c5a243aa
Restructures, the better to explore errors.
2021-04-10 21:32:42 -04:00
Thomas Harte
070e359d82
Introduces failing test for BIT b, (ii+n).
2021-04-10 18:00:23 -04:00
Thomas Harte
400f54e508
Introduces failing test for bit b, (hl).
2021-04-10 12:04:48 -04:00
Thomas Harte
e0736435f8
Makes assumption that the address bus just holds its value during an internal operation.
2021-04-10 12:00:53 -04:00
Thomas Harte
b09c5538c6
Adds failing test for simple (ii+n) tests.
2021-04-09 21:28:35 -04:00
Thomas Harte
ce3d2913bf
Advances to 9 source table rows tested out of 37.
2021-04-09 20:38:17 -04:00
Thomas Harte
87202a2a27
Add two further tests, add checking of collected data size for all tests.
2021-04-09 18:32:03 -04:00
Thomas Harte
818a4dff25
Corrects ADD HL, dd test.
...
Or, at least, likely corrects. The bus cycle breakdown in the Z80 data sheet implies these accesses should come after completion of the refresh cycle, not during its long tail, so I think +1 is correct.
2021-04-08 22:23:15 -04:00
Thomas Harte
9e506c3206
Adds failing ADD hl, dd test.
2021-04-08 22:19:22 -04:00
Thomas Harte
50f53f7d97
Adds INC/DEC rr and LD SP, HL tests.
2021-04-08 22:14:53 -04:00
Thomas Harte
73fbd89c85
Correct opcodes, ability to terminate on a single-cycle contention.
2021-04-08 22:09:33 -04:00
Thomas Harte
f74fa06f2d
Introduces failing test for LD [A/I/R], [A/I/R].
2021-04-08 20:28:55 -04:00
Thomas Harte
ee989ab762
Fills in the rest of the simple two-byte instructions.
2021-04-08 20:13:52 -04:00
Thomas Harte
818655a9b6
Starts on two-bus-cycle instructions, correcting validators.
2021-04-08 20:01:46 -04:00
Thomas Harte
57a7e0834f
Corrects sampling of MREQ.
2021-04-08 19:21:35 -04:00
Thomas Harte
cd787486d2
Tests all of the single-byte, no-access opcodes.
2021-04-07 22:07:52 -04:00
Thomas Harte
67fd6787a6
Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.
2021-04-07 21:57:40 -04:00
Thomas Harte
094d623485
Updates unit tests.
2021-04-05 21:33:04 -04:00
C.W. Betts
5758693b7d
Minor pokes to the test files code.
2021-03-19 02:19:49 -06:00
Thomas Harte
e5076b295b
Corrects namespace.
2021-01-21 18:58:11 -05:00
Thomas Harte
3c20e1f037
Adds files for the M50740 and corrects namespace errors elsewhere.
2021-01-15 21:30:30 -05:00
Thomas Harte
15bedc74d4
Merge branch 'master' into AppleIIgs
2021-01-15 21:15:10 -05:00
Thomas Harte
ddb4bb1421
Better plans project layout.
2021-01-15 18:16:01 -05:00
