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e82367def3
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285 Commits

Author SHA1 Message Date
Thomas Harte
e82367def3 Switches to test-conformant behaviour for (IX/IY+n) opcode fetches. 2021-04-11 23:01:00 -04:00
Thomas Harte
9cde7c12ba Shifts responsibility for refresh into the fetch-decode-execute sequence. 2021-04-11 22:50:24 -04:00
Thomas Harte
015556cc91 Switch (ii+n) to Read4Pre. 2021-04-11 10:26:14 -04:00
Thomas Harte
b397059d5e Moves read time in Read4Pre. 2021-04-10 17:54:20 -04:00
Thomas Harte
e0736435f8 Makes assumption that the address bus just holds its value during an internal operation. 2021-04-10 12:00:53 -04:00
Thomas Harte
eacffa49f5 Exposes IR during 'internal' operations. 2021-04-08 22:22:26 -04:00
Thomas Harte
29cf80339a Corrects too-short buffer. 2021-04-08 22:15:03 -04:00
Thomas Harte
57a7e0834f Corrects sampling of MREQ. 2021-04-08 19:21:35 -04:00
Thomas Harte
25b8c4c062 Provide clearer failure case. 2021-04-03 21:04:44 -04:00
Thomas Harte
1be88a5308 Remove first draft. 2021-04-02 07:39:22 -04:00
Thomas Harte
294280a94e Spells out everything except interrupt acknowledge. 2021-04-02 07:38:06 -04:00
Thomas Harte
32aebfebe0 Starts spelling out meaning of the Z80's partial machine cycles. 2021-04-02 07:37:56 -04:00
Thomas Harte
76299a2add Include AF' in Z80 state. 2021-03-29 22:58:52 -04:00
Thomas Harte
8641494809 Resolve various test-case warnings. 2020-09-27 15:10:29 -04:00
Thomas Harte
945a9da94f Adds further [[fallthrough]]s. 2020-06-19 23:44:20 -04:00
Thomas Harte
2477752fa4 Adds further [[fallthrough]] attributes. 2020-06-19 23:36:51 -04:00
Thomas Harte
267006782f Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
Thomas Harte
512a52e88d Increases const correctness, marks some additional constructors as constexpr, switches std::atomic construction style. 2020-05-20 23:34:26 -04:00
Thomas Harte
8b76d4007e Starts adding State for the 68000. 2020-05-14 22:46:40 -04:00
Thomas Harte
c5b746543b Factors the half mask into steps count. 2020-05-14 00:09:01 -04:00
Thomas Harte
11d936331d Attempts to preserve scheduled_program_counter_. 2020-05-13 23:58:04 -04:00
Thomas Harte
3709aa7555 Edges almost up to an initially complete implementation. 2020-05-13 22:04:04 -04:00
Thomas Harte
7c9d9ee048 Adds basic Z80 state. 2020-05-13 20:15:22 -04:00
Thomas Harte
25996ce180 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
Thomas Harte
b971e2a42c Adds get_is_resetting to the Z80, eliminating the CPC's custom version. 2020-02-29 19:58:25 -05:00
Thomas Harte
01faffd5bf Corrects memptr behaviour of OTIR/OTDR and INIR/INDR. 
This seemingly perfects memptr.
 2020-02-27 20:55:43 -05:00
Thomas Harte
26de5be07c Corrects memptr behaviour of LDIR/LDDR and CPIR/CPDR. 2020-02-27 20:44:53 -05:00
Thomas Harte
87474d5916 Corrects memptr behaviour of OUT (C), 0. 2020-02-27 20:38:27 -05:00
Thomas Harte
06163165d9 Corrects memptr effect of LD rr, (nn). 2020-02-26 22:22:54 -05:00
Thomas Harte
ec82c075be Fixes memptr for IN C, (C). 2020-02-26 22:19:37 -05:00
Thomas Harte
3b0df172a7 Corrects memptr behaviour of JP nn. 2020-02-26 22:02:15 -05:00
Thomas Harte
7058dbc3cc Corrects memptr for LD HL, (nn). 2020-02-26 21:54:49 -05:00
Thomas Harte
b64de89d2d Corrects JR memptrs. 2020-02-26 21:47:34 -05:00
Thomas Harte
8878396339 Corrects DJNZ memptr behaviour. 2020-02-26 21:42:31 -05:00
Thomas Harte
3097c4ccae Improves MEMPTR testing and some results. 2020-02-24 23:32:18 -05:00
Thomas Harte
7959d243f6 Adds single-stepping. Of a kind. 2020-02-24 23:31:42 -05:00
Thomas Harte
79dd402bc8 Consolidates different test port input selection. 2020-02-23 16:12:28 -05:00
Thomas Harte
3f3229851b Implements MEMPTR for IN. 2020-02-23 00:32:33 -05:00
Thomas Harte
1c154131f9 Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate. 2019-10-29 22:36:29 -04:00
Thomas Harte
8a14f5d814 Updates to Xcode11 recommended project settings. 
The updated compiler also flagged a potential issue with CPU::Z80::Register not being a namespace re: 'Refresh' versus CPU::Z80::PartialMachineCycle. I don't entirely see it, but this fixes the problem.

I also finally figured out what the compiler was trying to tell me about ROMRequester.xib.
 2019-09-22 12:13:56 -04:00
Thomas Harte
fa226bb1b9 Seeks to reduce enquiry costs. 2019-07-17 15:09:26 -04:00
Thomas Harte
40b2fe7339 Merge branch 'master' into 68000 2019-04-26 00:02:35 -04:00
Raphaël Zumer
71ac26944d Correct typos in Z80.hpp 2019-04-19 17:44:52 -04:00
Thomas Harte
4aeb9a7c56 Genericises RegisterPair. 2019-03-09 21:16:11 -05:00
Thomas Harte
d97348dd38 Eliminates dangling uses of printf. 2019-03-02 18:07:05 -05:00
Thomas Harte
0b14850467 Corrects some comments. 2018-06-24 23:02:36 -04:00
Thomas Harte
9a91ae38c1 Differentiates reasons for a read to be four cycles. 
Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
 2018-06-20 21:34:21 -04:00
Thomas Harte
ad9b0cd4e3 Eliminates all endashes. 2018-05-13 15:43:03 -04:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
45be1c19df Resolves undefined behaviour of a signed shift left. 2018-03-22 21:59:39 -04:00