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Author	SHA1	Message	Date
Adrian Conlon	796042acdf	Simplfy intel processor interations	2025-08-04 19:47:40 +01:00
Adrian Conlon	52ea4b3acd	Last trivial Z80 update	2025-08-04 18:19:40 +01:00
Adrian Conlon	9d208de9bb	Explicitly state order of operations in code, rather than relying upon RAII etc. (for speed. Much faster)	2025-08-04 15:47:26 +01:00
Adrian Conlon	319190b7a5	More Z80 cycle simplifications and fixes	2025-08-03 21:55:24 +01:00
Adrian Conlon	6a32d0269d	Fix the Z80 checker, so that all cycle actions are checked.	2025-08-03 21:54:05 +01:00
Adrian Conlon	3ccd9c45ca	Adjusted for the latest single-step Z80 tests. Simplify memory update access.	2025-08-02 17:49:18 +01:00
Adrian Conlon	bfc2355337	Correct RRD/RLD timing and XHTL ordering (according to latest Z80 single step tests)	2025-08-02 12:26:53 +01:00
Adrian Conlon	6143a9d285	Hack to allow single step tests to completely work: disable IO area triggers.	2025-08-01 22:59:00 +01:00
Adrian Conlon	bb63211f17	Fix event names	2025-08-01 22:57:38 +01:00
Adrian Conlon	60ef099208	Tidy some inconsistencies in various emulation	2025-08-01 15:01:20 +01:00
Adrian Conlon	a252a74d2d	Tidy some inconsistencies in z80 emulation	2025-08-01 14:59:40 +01:00
Adrian Conlon	2f338c6c46	Tidy register increment/decrement a little.	2025-07-25 16:32:30 +01:00
Adrian Conlon	c271b28495	Simplify bus addressing	2025-07-05 09:46:59 +01:00
Adrian Conlon	3bbf300e05	Simplify switching processor pin handling	2025-06-22 21:07:02 +01:00
Adrian Conlon	3105930027	Fix BBR/BBS timings in 65C02	2025-06-19 13:27:05 +01:00
Adrian Conlon	caca3467d9	More unit test stuff. New tests generated by copilot	2025-05-13 09:52:12 +01:00
Adrian Conlon	12053fd076	Tidy 6809 tests namespace	2025-05-12 21:39:42 +01:00
Adrian Conlon	a5eed89b26	Tidy up all the 6809 stuff	2025-05-12 21:08:39 +01:00
Adrian Conlon	6e1fc14530	Start tidying up 6809 implementation/testst	2025-05-12 19:15:34 +01:00
Adrian Conlon	adbd16daa2	Get M6809 unit tests running again	2025-05-12 12:19:27 +01:00
Adrian Conlon	e7b025e66e	Some speed-up refactoring of the Z80 core	2025-05-12 10:17:39 +01:00
Adrian Conlon	8331b4818e	Couple of small Register16 adjustments	2025-05-11 21:30:15 +01:00
Adrian Conlon	36e983526e	Add increment/decrement operations to the Register16 class	2025-05-11 19:24:40 +01:00
Adrian Conlon	60d000905f	Remove a bunch of analysis warnings	2025-05-08 22:03:27 +01:00
Adrian Conlon	fc2b0470a3	Remove test patterns	2025-05-08 22:01:19 +01:00
Adrian Conlon	19c18445d6	Remove a couple of pointless "Word"isms	2025-05-08 19:46:43 +01:00
Adrian Conlon	d92926c15b	Quite a fun low level rearrangement of the 16-bit register class.	2025-05-08 19:46:08 +01:00
Adrian Conlon	9e0006187e	Port access in Intel processors is 16 rather than 8 bit addressed	2025-05-08 13:00:30 +01:00
Adrian Conlon	eda9519068	Correct some analysis issues	2025-05-07 21:30:19 +01:00
Adrian Conlon	79c15602eb	Small refactor	2025-05-07 21:27:01 +01:00
Adrian Conlon	293c735ec5	Simplify indirect memory access	2025-05-07 11:56:23 +01:00
Adrian Conlon	1a09473b5a	Read port refactoring	2025-05-06 23:05:51 +01:00
Adrian Conlon	a6051a64ab	More IO simplifications	2025-05-06 22:51:30 +01:00
Adrian Conlon	62f42ef46f	Refactored a little, but no functional changes	2025-05-06 21:41:32 +01:00
Adrian Conlon	db1da4f506	Remove extra line	2025-05-06 21:39:47 +01:00
Adrian Conlon	95783d37aa	Reset/power refactoring for z80	2025-05-06 15:37:24 +01:00
Adrian Conlon	d58095a9d0	Power-on and reset consistency fixes	2025-05-06 11:52:33 +01:00
Adrian Conlon	e1696721f6	Simplifications and refactorings in th intel processors	2025-05-05 21:06:39 +01:00
Adrian Conlon	37431d08bc	Correct LD?R/CP?R block methods. 4 problem instuctions now.	2025-05-04 17:47:19 +01:00
Adrian Conlon	045907e273	Fix INI/IND flag handling. 8 problems remaining	2025-05-04 17:22:23 +01:00
Adrian Conlon	6d84c3a41f	Get SCF/CCF X/Y flags working correctly. 10 problems reported now.	2025-05-04 16:00:08 +01:00
Adrian Conlon	93e09c192f	Share instruction fetch and halt implementations	2025-05-04 11:41:28 +01:00
Adrian Conlon	2336222c97	Push more core processor handling into base classes.	2025-05-04 10:53:23 +01:00
Adrian Conlon	47374e591d	With my correct implementation of HALT, I need the fetch to take place during a halted state	2025-05-04 08:56:22 +01:00
Adrian Conlon	e4494e943a	PC only proceeds when HALT pin is raised	2025-05-04 00:36:01 +01:00
Adrian Conlon	853569b2ca	Isolate REFRESH pin functionality	2025-05-04 00:35:14 +01:00
Adrian Conlon	cbe871d365	Isolate program counter increment/decrement (to be used for HALT processing)	2025-05-03 23:25:06 +01:00
Adrian Conlon	2501bdfd28	More block timing issues corrected. 16 issues remaining	2025-05-03 22:46:02 +01:00
Adrian Conlon	6d8a00876f	Fix a bunch of "block" instruction timings. 16 problems remaining.	2025-05-03 19:51:36 +01:00
Adrian Conlon	a0d45eace1	Fix display of registers (from alternate set) when viewing z80 problems	2025-05-03 19:18:03 +01:00