2015-07-12 12:27:24 +00:00
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;
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2015-10-02 17:28:17 +00:00
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; PCE definitions. By Groepaz/Hitmen.
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2015-07-12 12:27:24 +00:00
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;
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2014-11-29 13:18:48 +00:00
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2015-10-02 17:28:17 +00:00
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; FIXME: Screen dimensions can change according to the selected video mode.
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2015-08-29 13:58:57 +00:00
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screenrows = (224/8)
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charsperline = 61
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CH_HLINE = 1
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CH_VLINE = 2
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2014-11-29 13:18:48 +00:00
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2015-10-02 17:28:17 +00:00
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; HuC6270 -- Video Display Controller (VDC)
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2014-11-29 13:18:48 +00:00
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2015-08-29 13:58:57 +00:00
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VDC_MAWR = 0 ; Memory Address Write Register
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VDC_MARR = 1 ; Memory Address Read Register
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2015-11-17 14:14:15 +00:00
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VDC_VWR = 2 ; VRAM Write Register
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VDC_VRR = 2 ; VRAM Read Register
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2015-09-07 10:55:36 +00:00
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VDC_UNK03 = 3 ; (unknown)
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VDC_UNK04 = 4 ; (unknown)
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VDC_CR = 5 ; Control Register
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VDC_RCR = 6 ; Raster Counter Register
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VDC_BXR = 7 ; Background X-Scroll Register
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VDC_BYR = 8 ; Background Y-Scroll Register
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VDC_MWR = 9 ; Memory-access Width Register
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VDC_HSR = 10 ; Horizontal Sync Register
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VDC_HDR = 11 ; Horizontal Display Register
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2015-10-02 17:28:17 +00:00
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VDC_VSR = 12 ; Vertical sync Register
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VDC_VDR = 13 ; Vertical Display register
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2015-09-07 10:55:36 +00:00
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VDC_VCR = 14 ; Vertical display END position register
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VDC_DCR = 15 ; (DMA) Control Register
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VDC_SOUR = 16 ; (DMA) Source Register
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VDC_DESR = 17 ; (DMA) Destination Register
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VDC_LENR = 18 ; (DMA) Length Register
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VDC_SATB = 19 ; Sprite Attribute Table
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2014-11-29 13:18:48 +00:00
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2015-07-15 11:18:12 +00:00
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; VDC port
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2015-09-29 16:39:58 +00:00
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; Note: The zero-page addressing mode is redirected to page $20.
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2015-11-17 14:14:15 +00:00
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; We avoid it by using mirror locations that are outside of the zero page.
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2015-07-15 11:18:12 +00:00
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2015-09-29 16:39:58 +00:00
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VDC_CTRL := $0200
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VDC_DATA_LO := $0202
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VDC_DATA_HI := $0203
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2014-11-29 13:18:48 +00:00
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2015-10-02 17:28:17 +00:00
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; HuC6260 -- Video Color Encoder (VCE)
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2014-11-29 13:18:48 +00:00
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; The DAC has a palette of 512 colours.
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2015-11-17 14:14:15 +00:00
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; The bitmap of that data is 0000000gggrrrbbb (Green, Red, Blue).
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2015-10-02 14:50:22 +00:00
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; You can read and write the DAC registers.
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2014-11-29 13:18:48 +00:00
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2015-10-02 17:28:17 +00:00
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VCE := $0400 ; base
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2015-07-14 15:22:47 +00:00
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2015-10-02 17:28:17 +00:00
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VCE_CTRL := $0400 ; write $00 to reset
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VCE_ADDR_LO := $0402 ; LSB of byte offset into palette
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VCE_ADDR_HI := $0403 ; MSB of byte offset into palette
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VCE_DATA_LO := $0404 ; LSB of 16-bit palette data
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VCE_DATA_HI := $0405 ; MSB of 16-bit palette data
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2014-11-29 13:18:48 +00:00
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2015-10-02 14:50:22 +00:00
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; Programmable Sound Generator (PSG)
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2015-07-14 15:22:47 +00:00
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2015-10-02 17:28:17 +00:00
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PSG := $0800 ; base
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2015-07-14 15:22:47 +00:00
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2015-10-02 17:28:17 +00:00
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PSG_CHAN_SELECT := $0800
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PSG_GLOBAL_PAN := $0801
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PSG_FREQ_LO := $0802
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PSG_FREQ_HI := $0803
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PSG_CHAN_CTRL := $0804
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PSG_CHAN_PAN := $0805
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PSG_CHAN_DATA := $0806
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PSG_NOISE := $0807
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PSG_LFO_FREQ := $0808
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PSG_LFO_CTRL := $0809
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2015-09-04 12:14:17 +00:00
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2015-10-02 14:50:22 +00:00
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; Timer
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2015-07-14 15:22:47 +00:00
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2015-10-02 17:28:17 +00:00
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TIMER := $0C00 ; base
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2015-07-14 15:22:47 +00:00
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2015-10-02 17:28:17 +00:00
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TIMER_COUNT := $0C00
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TIMER_CTRL := $0C01
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2014-11-29 13:18:48 +00:00
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2015-10-02 17:28:17 +00:00
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JOY_CTRL := $1000
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2014-11-29 13:18:48 +00:00
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2015-10-02 17:28:17 +00:00
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IRQ_MASK := $1402
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IRQ_STATUS := $1403
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2014-11-29 13:18:48 +00:00
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2015-10-02 17:28:17 +00:00
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CDR_MEM_DISABLE := $1803
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CDR_MEM_ENABLE := $1807
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2014-11-29 14:35:20 +00:00
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2015-11-17 14:14:15 +00:00
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; Write to a VDC register.
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.macro VREG arg1, arg2
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2015-07-12 12:27:24 +00:00
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st0 #arg1
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st1 #<(arg2)
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st2 #>(arg2)
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.endmacro
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