2005-10-10 06:00:30 +00:00
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//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-10-10 06:00:30 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent interfaces used by SelectionDAG
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// instruction selection generators.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Selection DAG Type Constraint definitions.
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//
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// Note that the semantics of these constraints are hard coded into tblgen. To
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// modify or add constraints, you have to hack tblgen.
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//
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class SDTypeConstraint<int opnum> {
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int OperandNum = opnum;
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}
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// SDTCisVT - The specified operand has exactly this VT.
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2005-12-09 22:58:42 +00:00
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class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
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2005-10-10 06:00:30 +00:00
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ValueType VT = vt;
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}
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2005-12-09 22:58:42 +00:00
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class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
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2005-10-10 06:00:30 +00:00
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// SDTCisInt - The specified operand is has integer type.
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class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
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// SDTCisFP - The specified operand is has floating point type.
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2005-12-09 22:58:42 +00:00
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class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
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2005-10-10 06:00:30 +00:00
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// SDTCisSameAs - The two specified operands have identical types.
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class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
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int OtherOperandNum = OtherOp;
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}
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// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
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// smaller than the 'Other' operand.
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class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
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int OtherOperandNum = OtherOp;
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}
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2005-10-14 04:55:10 +00:00
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class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
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int BigOperandNum = BigOp;
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}
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2006-03-20 05:40:45 +00:00
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/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
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2007-07-16 14:29:03 +00:00
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/// vector types, and that ThisOp is the result of
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2008-06-06 12:08:01 +00:00
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/// MVT::getIntVectorWithNumElements with the number of elements
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/// that ThisOp has.
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2006-03-20 05:40:45 +00:00
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class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
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: SDTypeConstraint<ThisOp> {
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int OtherOpNum = OtherOp;
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}
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2008-02-09 01:37:05 +00:00
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/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
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/// type as the element type of OtherOp, which is a vector type.
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2008-05-31 02:11:25 +00:00
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class SDTCisEltOfVec<int ThisOp, int OtherOp>
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2008-02-09 01:37:05 +00:00
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: SDTypeConstraint<ThisOp> {
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int OtherOpNum = OtherOp;
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}
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2005-10-10 06:00:30 +00:00
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//===----------------------------------------------------------------------===//
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// Selection DAG Type Profile definitions.
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//
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// These use the constraints defined above to describe the type requirements of
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// the various nodes. These are not hard coded into tblgen, allowing targets to
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// add their own if needed.
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//
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// SDTypeProfile - This profile describes the type requirements of a Selection
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// DAG node.
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class SDTypeProfile<int numresults, int numoperands,
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list<SDTypeConstraint> constraints> {
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int NumResults = numresults;
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int NumOperands = numoperands;
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list<SDTypeConstraint> Constraints = constraints;
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}
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// Builtin profiles.
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2005-12-11 07:45:04 +00:00
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def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
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2006-01-05 02:07:49 +00:00
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def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
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2005-12-11 07:45:04 +00:00
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def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
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2005-12-04 08:13:17 +00:00
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def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
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2005-10-25 21:03:14 +00:00
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def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
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2006-03-16 01:29:53 +00:00
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def SDTUnaryOp : SDTypeProfile<1, 1, []>; // bitconvert
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2005-10-10 06:00:30 +00:00
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def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
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]>;
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2005-12-05 02:37:26 +00:00
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def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
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]>;
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2005-10-10 06:00:30 +00:00
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def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
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]>;
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2006-03-09 17:47:22 +00:00
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def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
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SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
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]>;
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2005-12-13 22:55:22 +00:00
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def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
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]>;
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2005-10-10 06:00:30 +00:00
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def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
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SDTCisSameAs<0, 1>, SDTCisInt<0>
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]>;
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2005-10-14 06:40:20 +00:00
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def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
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SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
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]>;
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def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
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SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
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]>;
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2005-10-10 06:00:30 +00:00
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def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
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SDTCisSameAs<0, 1>, SDTCisFP<0>
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]>;
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2005-10-14 04:55:10 +00:00
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def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
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SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
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]>;
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def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
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SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
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]>;
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2005-11-01 03:07:25 +00:00
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def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
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SDTCisFP<0>, SDTCisInt<1>
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]>;
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def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
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SDTCisInt<0>, SDTCisFP<1>
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]>;
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2005-10-10 06:00:30 +00:00
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def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
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SDTCisVTSmallerThanOp<2, 1>
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]>;
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2005-10-26 17:00:25 +00:00
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def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
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SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
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]>;
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2005-11-02 02:37:18 +00:00
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def SDTSelect : SDTypeProfile<1, 3, [ // select
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SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
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]>;
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2005-12-11 18:43:13 +00:00
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def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
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2005-12-11 08:35:54 +00:00
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SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
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SDTCisVT<5, OtherVT>
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]>;
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2005-12-04 08:13:17 +00:00
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def SDTBr : SDTypeProfile<0, 1, [ // br
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SDTCisVT<0, OtherVT>
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]>;
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2006-01-01 22:16:43 +00:00
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def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
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SDTCisInt<0>, SDTCisVT<1, OtherVT>
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]>;
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2006-04-22 18:53:45 +00:00
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def SDTBrind : SDTypeProfile<0, 1, [ // brind
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SDTCisPtrTy<0>
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]>;
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2008-01-15 22:02:54 +00:00
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def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
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2005-12-04 08:13:17 +00:00
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2005-12-08 04:28:48 +00:00
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def SDTLoad : SDTypeProfile<1, 1, [ // load
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2005-12-09 22:58:42 +00:00
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SDTCisPtrTy<1>
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2005-12-08 04:28:48 +00:00
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]>;
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2005-12-10 00:48:20 +00:00
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def SDTStore : SDTypeProfile<0, 2, [ // store
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2005-12-10 01:59:36 +00:00
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SDTCisPtrTy<1>
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2005-12-10 00:48:20 +00:00
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]>;
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2006-11-08 23:02:11 +00:00
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def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
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SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
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]>;
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2006-03-20 05:40:45 +00:00
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def SDTVecShuffle : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
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]>;
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2008-02-09 01:37:05 +00:00
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def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
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SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
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]>;
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2008-02-11 04:19:36 +00:00
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def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
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SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
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2008-02-09 01:37:05 +00:00
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]>;
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2006-03-20 05:40:45 +00:00
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2008-03-08 00:58:38 +00:00
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def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
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SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
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]>;
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def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
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2008-02-16 01:24:58 +00:00
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SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
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SDTCisInt<0>
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]>;
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2008-02-21 06:45:13 +00:00
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def STDAtomic3 : SDTypeProfile<1, 3, [
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SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
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]>;
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def STDAtomic2 : SDTypeProfile<1, 2, [
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SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
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]>;
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2008-02-16 01:24:58 +00:00
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2007-11-13 09:19:02 +00:00
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class SDCallSeqStart<list<SDTypeConstraint> constraints> :
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SDTypeProfile<0, 1, constraints>;
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class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
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SDTypeProfile<0, 2, constraints>;
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2005-10-10 06:00:30 +00:00
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//===----------------------------------------------------------------------===//
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// Selection DAG Node Properties.
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//
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// Note: These are hard coded into tblgen.
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//
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class SDNodeProperty;
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def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
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def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
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2005-12-04 08:13:17 +00:00
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def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
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2006-01-09 18:28:21 +00:00
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def SDNPOutFlag : SDNodeProperty; // Write a flag result
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def SDNPInFlag : SDNodeProperty; // Read a flag operand
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def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
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2008-01-06 08:36:04 +00:00
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def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
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2008-01-10 04:44:32 +00:00
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def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
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2008-01-10 05:48:23 +00:00
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def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
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2008-06-25 08:15:39 +00:00
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def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
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2005-10-10 06:00:30 +00:00
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//===----------------------------------------------------------------------===//
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// Selection DAG Node definitions.
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//
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class SDNode<string opcode, SDTypeProfile typeprof,
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list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
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string Opcode = opcode;
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string SDClass = sdclass;
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list<SDNodeProperty> Properties = props;
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SDTypeProfile TypeProfile = typeprof;
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}
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def set;
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2007-09-25 01:48:59 +00:00
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def implicit;
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2007-09-12 23:30:14 +00:00
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def parallel;
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2005-10-10 06:00:30 +00:00
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def node;
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2005-12-14 02:21:01 +00:00
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def srcvalue;
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2005-10-10 06:00:30 +00:00
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2005-12-11 07:45:04 +00:00
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def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
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2008-02-14 08:57:00 +00:00
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def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
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2005-12-04 08:13:17 +00:00
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def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
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def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
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def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
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2005-10-25 21:03:14 +00:00
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def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
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2005-12-24 23:36:59 +00:00
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def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
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2005-11-17 07:20:15 +00:00
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"GlobalAddressSDNode">;
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2005-12-24 23:36:59 +00:00
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def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
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"GlobalAddressSDNode">;
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2007-04-20 21:38:10 +00:00
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|
def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
|
|
|
|
|
"GlobalAddressSDNode">;
|
|
|
|
|
def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
|
|
|
|
|
"GlobalAddressSDNode">;
|
2005-12-24 23:36:59 +00:00
|
|
|
def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
|
|
|
|
|
"ConstantPoolSDNode">;
|
|
|
|
|
def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
|
|
|
|
|
"ConstantPoolSDNode">;
|
2006-04-22 18:53:45 +00:00
|
|
|
def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
|
|
|
|
|
"JumpTableSDNode">;
|
|
|
|
|
def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
|
|
|
|
|
"JumpTableSDNode">;
|
2005-12-24 23:36:59 +00:00
|
|
|
def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
|
|
|
|
|
"FrameIndexSDNode">;
|
|
|
|
|
def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
|
|
|
|
|
"FrameIndexSDNode">;
|
2008-09-16 21:48:12 +00:00
|
|
|
def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
|
|
|
|
|
"ExternalSymbolSDNode">;
|
|
|
|
|
def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
|
|
|
|
|
"ExternalSymbolSDNode">;
|
2005-12-24 23:36:59 +00:00
|
|
|
|
2005-10-10 06:00:30 +00:00
|
|
|
def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
|
|
|
|
|
[SDNPCommutative, SDNPAssociative]>;
|
|
|
|
|
def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
|
|
|
|
|
def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
|
|
|
|
|
[SDNPCommutative, SDNPAssociative]>;
|
|
|
|
|
def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
|
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|
|
|
def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
|
|
|
|
|
def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
|
|
|
|
|
def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
|
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|
|
|
def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
|
|
|
|
|
def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
|
2005-12-05 02:37:26 +00:00
|
|
|
def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
|
|
|
|
|
def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
|
|
|
|
|
def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
|
2006-01-11 21:21:00 +00:00
|
|
|
def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
|
|
|
|
|
def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
|
2005-10-10 06:00:30 +00:00
|
|
|
def and : SDNode<"ISD::AND" , SDTIntBinOp,
|
|
|
|
|
[SDNPCommutative, SDNPAssociative]>;
|
|
|
|
|
def or : SDNode<"ISD::OR" , SDTIntBinOp,
|
|
|
|
|
[SDNPCommutative, SDNPAssociative]>;
|
|
|
|
|
def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
|
|
|
|
|
[SDNPCommutative, SDNPAssociative]>;
|
2006-02-17 05:43:56 +00:00
|
|
|
def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
|
|
|
|
|
[SDNPCommutative, SDNPOutFlag]>;
|
|
|
|
|
def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
|
|
|
|
|
[SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
|
|
|
|
|
def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
|
|
|
|
|
[SDNPOutFlag]>;
|
|
|
|
|
def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
|
|
|
|
|
[SDNPOutFlag, SDNPInFlag]>;
|
2005-10-14 06:40:20 +00:00
|
|
|
|
|
|
|
|
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
|
2006-01-14 03:14:10 +00:00
|
|
|
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
|
2005-10-14 06:40:20 +00:00
|
|
|
def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
|
2005-10-20 19:38:11 +00:00
|
|
|
def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
|
|
|
|
|
def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
|
2005-10-14 06:40:20 +00:00
|
|
|
def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
|
|
|
|
|
def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
|
|
|
|
|
def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
|
|
|
|
|
def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
|
2006-03-16 01:29:53 +00:00
|
|
|
def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
|
2008-02-09 01:37:05 +00:00
|
|
|
def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
|
|
|
|
|
def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
|
|
|
|
|
|
2005-10-14 06:40:20 +00:00
|
|
|
|
2005-10-10 06:00:30 +00:00
|
|
|
def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
|
|
|
|
|
def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
|
|
|
|
|
def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
|
|
|
|
|
def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
|
|
|
|
|
def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
|
|
|
|
|
def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
|
|
|
|
|
def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
|
|
|
|
|
def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
|
2005-12-21 16:22:46 +00:00
|
|
|
def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
|
|
|
|
|
def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
|
2008-08-21 17:55:02 +00:00
|
|
|
def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
|
|
|
|
|
def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
|
|
|
|
|
def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
|
|
|
|
|
def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
|
|
|
|
|
def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
|
2005-10-10 06:00:30 +00:00
|
|
|
|
2005-10-14 04:55:10 +00:00
|
|
|
def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
|
|
|
|
|
def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
|
2006-03-09 17:47:22 +00:00
|
|
|
def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
|
2005-10-14 04:55:10 +00:00
|
|
|
|
2005-11-01 03:07:25 +00:00
|
|
|
def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
|
|
|
|
|
def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
|
|
|
|
|
def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
|
|
|
|
|
def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
|
|
|
|
|
|
2005-10-26 17:00:25 +00:00
|
|
|
def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
|
2005-11-02 02:37:18 +00:00
|
|
|
def select : SDNode<"ISD::SELECT" , SDTSelect>;
|
2005-12-11 08:35:54 +00:00
|
|
|
def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
|
2008-05-12 19:40:03 +00:00
|
|
|
def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
|
2005-10-26 17:00:25 +00:00
|
|
|
|
2006-01-01 22:16:43 +00:00
|
|
|
def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
|
2006-04-22 18:53:45 +00:00
|
|
|
def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
|
2005-12-04 08:13:17 +00:00
|
|
|
def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
|
2008-01-15 22:02:54 +00:00
|
|
|
def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
|
|
|
|
|
def trap : SDNode<"ISD::TRAP" , SDTNone,
|
|
|
|
|
[SDNPHasChain, SDNPSideEffect]>;
|
2008-03-08 00:58:38 +00:00
|
|
|
|
|
|
|
|
def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
|
|
|
|
|
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
|
|
|
|
|
|
|
|
|
|
def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
|
2008-02-16 01:24:58 +00:00
|
|
|
[SDNPHasChain, SDNPSideEffect]>;
|
2008-03-08 00:58:38 +00:00
|
|
|
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_cmp_swap_8 : SDNode<"ISD::ATOMIC_CMP_SWAP_8" , STDAtomic3,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_add_8 : SDNode<"ISD::ATOMIC_LOAD_ADD_8" , STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_swap_8 : SDNode<"ISD::ATOMIC_SWAP_8", STDAtomic2,
|
2008-08-19 23:09:18 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_sub_8 : SDNode<"ISD::ATOMIC_LOAD_SUB_8" , STDAtomic2,
|
2008-08-20 00:28:16 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_and_8 : SDNode<"ISD::ATOMIC_LOAD_AND_8" , STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_or_8 : SDNode<"ISD::ATOMIC_LOAD_OR_8" , STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_xor_8 : SDNode<"ISD::ATOMIC_LOAD_XOR_8" , STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_nand_8: SDNode<"ISD::ATOMIC_LOAD_NAND_8", STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_min_8 : SDNode<"ISD::ATOMIC_LOAD_MIN_8", STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_max_8 : SDNode<"ISD::ATOMIC_LOAD_MAX_8", STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_umin_8 : SDNode<"ISD::ATOMIC_LOAD_UMIN_8", STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2008-08-28 02:44:49 +00:00
|
|
|
def atomic_load_umax_8 : SDNode<"ISD::ATOMIC_LOAD_UMAX_8", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_cmp_swap_16 : SDNode<"ISD::ATOMIC_CMP_SWAP_16" , STDAtomic3,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_add_16 : SDNode<"ISD::ATOMIC_LOAD_ADD_16" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_swap_16 : SDNode<"ISD::ATOMIC_SWAP_16", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_sub_16 : SDNode<"ISD::ATOMIC_LOAD_SUB_16" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_and_16 : SDNode<"ISD::ATOMIC_LOAD_AND_16" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_or_16 : SDNode<"ISD::ATOMIC_LOAD_OR_16" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_xor_16 : SDNode<"ISD::ATOMIC_LOAD_XOR_16" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_nand_16: SDNode<"ISD::ATOMIC_LOAD_NAND_16", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_min_16 : SDNode<"ISD::ATOMIC_LOAD_MIN_16", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_max_16 : SDNode<"ISD::ATOMIC_LOAD_MAX_16", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_umin_16 : SDNode<"ISD::ATOMIC_LOAD_UMIN_16", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_umax_16 : SDNode<"ISD::ATOMIC_LOAD_UMAX_16", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_cmp_swap_32 : SDNode<"ISD::ATOMIC_CMP_SWAP_32" , STDAtomic3,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_add_32 : SDNode<"ISD::ATOMIC_LOAD_ADD_32" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_swap_32 : SDNode<"ISD::ATOMIC_SWAP_32", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_sub_32 : SDNode<"ISD::ATOMIC_LOAD_SUB_32" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_and_32 : SDNode<"ISD::ATOMIC_LOAD_AND_32" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_or_32 : SDNode<"ISD::ATOMIC_LOAD_OR_32" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_xor_32 : SDNode<"ISD::ATOMIC_LOAD_XOR_32" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_nand_32: SDNode<"ISD::ATOMIC_LOAD_NAND_32", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_min_32 : SDNode<"ISD::ATOMIC_LOAD_MIN_32", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_max_32 : SDNode<"ISD::ATOMIC_LOAD_MAX_32", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_umin_32 : SDNode<"ISD::ATOMIC_LOAD_UMIN_32", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_umax_32 : SDNode<"ISD::ATOMIC_LOAD_UMAX_32", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_cmp_swap_64 : SDNode<"ISD::ATOMIC_CMP_SWAP_64" , STDAtomic3,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_add_64 : SDNode<"ISD::ATOMIC_LOAD_ADD_64" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_swap_64 : SDNode<"ISD::ATOMIC_SWAP_64", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_sub_64 : SDNode<"ISD::ATOMIC_LOAD_SUB_64" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_and_64 : SDNode<"ISD::ATOMIC_LOAD_AND_64" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_or_64 : SDNode<"ISD::ATOMIC_LOAD_OR_64" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_xor_64 : SDNode<"ISD::ATOMIC_LOAD_XOR_64" , STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_nand_64: SDNode<"ISD::ATOMIC_LOAD_NAND_64", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_min_64 : SDNode<"ISD::ATOMIC_LOAD_MIN_64", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_max_64 : SDNode<"ISD::ATOMIC_LOAD_MAX_64", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_umin_64 : SDNode<"ISD::ATOMIC_LOAD_UMIN_64", STDAtomic2,
|
|
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
|
|
|
|
def atomic_load_umax_64 : SDNode<"ISD::ATOMIC_LOAD_UMAX_64", STDAtomic2,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
|
2005-12-04 08:13:17 +00:00
|
|
|
|
2006-10-13 21:14:26 +00:00
|
|
|
// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
|
|
|
|
|
// and truncst (see below).
|
2008-01-10 04:44:32 +00:00
|
|
|
def ld : SDNode<"ISD::LOAD" , SDTLoad,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
|
2008-01-06 06:44:58 +00:00
|
|
|
def st : SDNode<"ISD::STORE" , SDTStore,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
2008-01-06 06:44:58 +00:00
|
|
|
def ist : SDNode<"ISD::STORE" , SDTIStore,
|
2008-06-25 08:15:39 +00:00
|
|
|
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
2005-12-14 02:21:01 +00:00
|
|
|
|
2006-03-20 05:40:45 +00:00
|
|
|
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
|
2008-07-28 19:17:21 +00:00
|
|
|
def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
|
2006-03-21 00:33:35 +00:00
|
|
|
def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
|
|
|
|
|
[]>;
|
2006-03-31 19:21:16 +00:00
|
|
|
def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
|
2006-06-15 08:19:05 +00:00
|
|
|
SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
|
2006-03-31 19:21:16 +00:00
|
|
|
def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
|
2006-06-15 08:19:05 +00:00
|
|
|
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
|
2007-07-26 07:34:40 +00:00
|
|
|
|
|
|
|
|
def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
|
|
|
|
|
SDTypeProfile<1, 2, []>>;
|
|
|
|
|
def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
|
|
|
|
|
SDTypeProfile<1, 3, []>>;
|
2006-03-20 05:40:45 +00:00
|
|
|
|
2006-03-25 02:29:35 +00:00
|
|
|
// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
|
|
|
|
|
// these internally. Don't reference these directly.
|
2006-03-28 00:40:33 +00:00
|
|
|
def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
|
2006-03-25 02:29:35 +00:00
|
|
|
SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
|
|
|
|
|
[SDNPHasChain]>;
|
2006-03-28 00:40:33 +00:00
|
|
|
def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
|
2006-03-25 02:29:35 +00:00
|
|
|
SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
|
|
|
|
|
[SDNPHasChain]>;
|
2006-03-28 00:40:33 +00:00
|
|
|
def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
|
2006-03-25 02:29:35 +00:00
|
|
|
SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
|
|
|
|
|
|
|
|
|
|
|
2005-10-26 17:00:25 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Selection DAG Condition Codes
|
|
|
|
|
|
|
|
|
|
class CondCode; // ISD::CondCode enums
|
|
|
|
|
def SETOEQ : CondCode; def SETOGT : CondCode;
|
|
|
|
|
def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
|
|
|
|
|
def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
|
|
|
|
|
def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
|
|
|
|
|
def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
|
|
|
|
|
|
|
|
|
|
def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
|
|
|
|
|
def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
|
|
|
|
|
|
|
|
|
|
|
2005-10-10 06:00:30 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Selection DAG Node Transformation Functions.
|
|
|
|
|
//
|
|
|
|
|
// This mechanism allows targets to manipulate nodes in the output DAG once a
|
|
|
|
|
// match has been formed. This is typically used to manipulate immediate
|
|
|
|
|
// values.
|
|
|
|
|
//
|
|
|
|
|
class SDNodeXForm<SDNode opc, code xformFunction> {
|
|
|
|
|
SDNode Opcode = opc;
|
|
|
|
|
code XFormFunction = xformFunction;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Selection DAG Pattern Fragments.
|
|
|
|
|
//
|
|
|
|
|
// Pattern fragments are reusable chunks of dags that match specific things.
|
|
|
|
|
// They can take arguments and have C++ predicates that control whether they
|
|
|
|
|
// match. They are intended to make the patterns for common instructions more
|
|
|
|
|
// compact and readable.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
/// PatFrag - Represents a pattern fragment. This can match something on the
|
|
|
|
|
/// DAG, frame a single node to multiply nested other fragments.
|
|
|
|
|
///
|
|
|
|
|
class PatFrag<dag ops, dag frag, code pred = [{}],
|
|
|
|
|
SDNodeXForm xform = NOOP_SDNodeXForm> {
|
|
|
|
|
dag Operands = ops;
|
|
|
|
|
dag Fragment = frag;
|
|
|
|
|
code Predicate = pred;
|
|
|
|
|
SDNodeXForm OperandTransform = xform;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// PatLeaf's are pattern fragments that have no operands. This is just a helper
|
|
|
|
|
// to define immediates and other common things concisely.
|
|
|
|
|
class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
|
|
|
|
|
: PatFrag<(ops), frag, pred, xform>;
|
|
|
|
|
|
|
|
|
|
// Leaf fragments.
|
|
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
|
|
|
|
|
def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
|
2005-10-10 06:00:30 +00:00
|
|
|
|
2006-03-25 23:00:08 +00:00
|
|
|
def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
|
|
|
|
|
def immAllOnesV: PatLeaf<(build_vector), [{
|
2006-03-27 06:59:32 +00:00
|
|
|
return ISD::isBuildVectorAllOnes(N);
|
2006-03-26 09:51:39 +00:00
|
|
|
}]>;
|
2007-11-24 19:02:07 +00:00
|
|
|
def immAllOnesV_bc: PatLeaf<(bitconvert), [{
|
|
|
|
|
return ISD::isBuildVectorAllOnes(N);
|
|
|
|
|
}]>;
|
2006-03-26 09:51:39 +00:00
|
|
|
def immAllZerosV: PatLeaf<(build_vector), [{
|
|
|
|
|
return ISD::isBuildVectorAllZeros(N);
|
2006-03-25 23:00:08 +00:00
|
|
|
}]>;
|
2007-11-24 19:02:07 +00:00
|
|
|
def immAllZerosV_bc: PatLeaf<(bitconvert), [{
|
|
|
|
|
return ISD::isBuildVectorAllZeros(N);
|
2006-04-15 23:39:14 +00:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
|
2007-11-24 19:02:07 +00:00
|
|
|
|
2006-03-25 23:00:08 +00:00
|
|
|
// Other helper fragments.
|
2005-10-10 06:00:30 +00:00
|
|
|
def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
|
2006-03-25 23:00:08 +00:00
|
|
|
def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
|
2006-04-15 23:39:14 +00:00
|
|
|
def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
|
2005-10-20 23:30:37 +00:00
|
|
|
def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
|
2005-10-10 06:00:30 +00:00
|
|
|
|
2006-10-26 21:55:50 +00:00
|
|
|
// load fragments.
|
2006-10-09 20:57:25 +00:00
|
|
|
def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::NON_EXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
|
2006-10-13 21:14:26 +00:00
|
|
|
// extending load fragments.
|
2006-10-09 20:57:25 +00:00
|
|
|
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i1;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i8;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i16;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i32;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::f32;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
2007-08-05 18:49:15 +00:00
|
|
|
def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::EXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::f64;
|
2007-08-05 18:49:15 +00:00
|
|
|
}]>;
|
2006-10-09 20:57:25 +00:00
|
|
|
|
2006-10-26 21:55:50 +00:00
|
|
|
def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i1;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
2006-10-26 21:55:50 +00:00
|
|
|
def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i8;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i16;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::SEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i32;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
|
2006-10-26 21:55:50 +00:00
|
|
|
def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i1;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
2006-10-26 21:55:50 +00:00
|
|
|
def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i8;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i16;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
|
|
|
return LD->getExtensionType() == ISD::ZEXTLOAD &&
|
|
|
|
|
LD->getAddressingMode() == ISD::UNINDEXED &&
|
|
|
|
|
LD->getMemoryVT() == MVT::i32;
|
2006-10-09 20:57:25 +00:00
|
|
|
}]>;
|
|
|
|
|
|
2006-10-26 21:55:50 +00:00
|
|
|
// store fragments.
|
2006-10-13 21:14:26 +00:00
|
|
|
def store : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(st node:$val, node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
return !ST->isTruncatingStore() &&
|
|
|
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
2006-10-13 21:14:26 +00:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
// truncstore fragments.
|
|
|
|
|
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(st node:$val, node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8 &&
|
|
|
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
2006-10-13 21:14:26 +00:00
|
|
|
}]>;
|
|
|
|
|
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(st node:$val, node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16 &&
|
|
|
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
2006-10-13 21:14:26 +00:00
|
|
|
}]>;
|
|
|
|
|
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(st node:$val, node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
2008-08-20 15:54:46 +00:00
|
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32 &&
|
|
|
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
2006-10-13 21:14:26 +00:00
|
|
|
}]>;
|
|
|
|
|
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(st node:$val, node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32 &&
|
|
|
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
2007-08-05 18:49:15 +00:00
|
|
|
def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
|
|
|
|
|
(st node:$val, node:$ptr), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
return ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f64 &&
|
|
|
|
|
ST->getAddressingMode() == ISD::UNINDEXED;
|
2007-08-05 18:49:15 +00:00
|
|
|
}]>;
|
2006-11-08 23:02:11 +00:00
|
|
|
|
|
|
|
|
// indexed store fragments.
|
|
|
|
|
def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
|
|
|
!ST->isTruncatingStore();
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::PRE_INC || AM == ISD::PRE_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
|
|
|
|
|
(ist node:$val, node:$ptr, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return !ST->isTruncatingStore() &&
|
|
|
|
|
(AM == ISD::POST_INC || AM == ISD::POST_DEC);
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
|
|
|
|
|
def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i1;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i8;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i16;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::i32;
|
2006-11-08 23:02:11 +00:00
|
|
|
}]>;
|
|
|
|
|
def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
|
|
|
|
|
(ist node:$val, node:$base, node:$offset), [{
|
2008-08-20 15:24:22 +00:00
|
|
|
StoreSDNode *ST = cast<StoreSDNode>(N);
|
|
|
|
|
ISD::MemIndexedMode AM = ST->getAddressingMode();
|
|
|
|
|
return (AM == ISD::POST_INC || AM == ISD::POST_DEC) &&
|
|
|
|
|
ST->isTruncatingStore() && ST->getMemoryVT() == MVT::f32;
|
2006-10-13 21:14:26 +00:00
|
|
|
}]>;
|
2005-10-26 17:00:25 +00:00
|
|
|
|
|
|
|
|
// setcc convenience fragments.
|
|
|
|
|
def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETOEQ)>;
|
|
|
|
|
def setogt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETOGT)>;
|
|
|
|
|
def setoge : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETOGE)>;
|
|
|
|
|
def setolt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETOLT)>;
|
|
|
|
|
def setole : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETOLE)>;
|
|
|
|
|
def setone : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETONE)>;
|
|
|
|
|
def seto : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETO)>;
|
|
|
|
|
def setuo : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETUO)>;
|
|
|
|
|
def setueq : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETUEQ)>;
|
|
|
|
|
def setugt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETUGT)>;
|
|
|
|
|
def setuge : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETUGE)>;
|
|
|
|
|
def setult : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETULT)>;
|
|
|
|
|
def setule : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETULE)>;
|
|
|
|
|
def setune : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETUNE)>;
|
|
|
|
|
def seteq : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETEQ)>;
|
|
|
|
|
def setgt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETGT)>;
|
|
|
|
|
def setge : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETGE)>;
|
|
|
|
|
def setlt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETLT)>;
|
|
|
|
|
def setle : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETLE)>;
|
|
|
|
|
def setne : PatFrag<(ops node:$lhs, node:$rhs),
|
|
|
|
|
(setcc node:$lhs, node:$rhs, SETNE)>;
|
|
|
|
|
|
2005-10-10 06:00:30 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Selection DAG Pattern Support.
|
|
|
|
|
//
|
|
|
|
|
// Patterns are what are actually matched against the target-flavored
|
|
|
|
|
// instruction selection DAG. Instructions defined by the target implicitly
|
|
|
|
|
// define patterns in most cases, but patterns can also be explicitly added when
|
|
|
|
|
// an operation is defined by a sequence of instructions (e.g. loading a large
|
|
|
|
|
// immediate value on RISC targets that do not support immediates as large as
|
|
|
|
|
// their GPRs).
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
class Pattern<dag patternToMatch, list<dag> resultInstrs> {
|
2006-04-19 20:38:28 +00:00
|
|
|
dag PatternToMatch = patternToMatch;
|
|
|
|
|
list<dag> ResultInstrs = resultInstrs;
|
|
|
|
|
list<Predicate> Predicates = []; // See class Instruction in Target.td.
|
|
|
|
|
int AddedComplexity = 0; // See class Instruction in Target.td.
|
2005-10-10 06:00:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Pat - A simple (but common) form of a pattern, which produces a simple result
|
|
|
|
|
// not needing a full list.
|
|
|
|
|
class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
|
|
|
|
|
|
2005-12-08 04:28:48 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Complex pattern definitions.
|
|
|
|
|
//
|
2008-01-31 07:27:46 +00:00
|
|
|
|
|
|
|
|
class CPAttribute;
|
|
|
|
|
// Pass the parent Operand as root to CP function rather
|
|
|
|
|
// than the root of the sub-DAG
|
|
|
|
|
def CPAttrParentAsRoot : CPAttribute;
|
|
|
|
|
|
2005-12-08 04:28:48 +00:00
|
|
|
// Complex patterns, e.g. X86 addressing mode, requires pattern matching code
|
|
|
|
|
// in C++. NumOperands is the number of operands returned by the select function;
|
|
|
|
|
// SelectFunc is the name of the function used to pattern match the max. pattern;
|
|
|
|
|
// RootNodes are the list of possible root nodes of the sub-dags to match.
|
|
|
|
|
// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
|
|
|
|
|
//
|
2006-10-11 21:03:53 +00:00
|
|
|
class ComplexPattern<ValueType ty, int numops, string fn,
|
2008-01-31 07:27:46 +00:00
|
|
|
list<SDNode> roots = [], list<SDNodeProperty> props = [],
|
|
|
|
|
list<CPAttribute> attrs = []> {
|
2005-12-08 04:28:48 +00:00
|
|
|
ValueType Ty = ty;
|
|
|
|
|
int NumOperands = numops;
|
|
|
|
|
string SelectFunc = fn;
|
|
|
|
|
list<SDNode> RootNodes = roots;
|
2006-10-11 21:03:53 +00:00
|
|
|
list<SDNodeProperty> Properties = props;
|
2008-01-31 07:27:46 +00:00
|
|
|
list<CPAttribute> Attributes = attrs;
|
2005-12-08 04:28:48 +00:00
|
|
|
}
|
2005-12-16 22:45:29 +00:00
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Dwarf support.
|
|
|
|
|
//
|
2006-01-05 01:25:28 +00:00
|
|
|
def SDT_dwarf_loc : SDTypeProfile<0, 3,
|
|
|
|
|
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
|
|
|
|
|
def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
|
