2011-04-15 21:51:11 +00:00
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//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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#include "MipsInstrInfo.h"
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2008-07-14 14:42:54 +00:00
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#include "MipsTargetMachine.h"
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2009-06-03 20:30:14 +00:00
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#include "MipsMachineFunction.h"
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2011-07-07 23:56:50 +00:00
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#include "InstPrinter/MipsInstPrinter.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2009-06-03 20:30:14 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2009-07-11 20:10:48 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2011-08-24 18:08:43 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2011-07-11 03:57:24 +00:00
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#include "llvm/ADT/STLExtras.h"
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2011-06-28 20:07:07 +00:00
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2011-07-01 17:57:27 +00:00
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#define GET_INSTRINFO_CTOR
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2007-06-06 07:42:06 +00:00
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
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2011-07-01 17:57:27 +00:00
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: MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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2011-10-11 00:37:28 +00:00
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TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
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2011-12-12 22:39:35 +00:00
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RI(*TM.getSubtargetImpl(), *this),
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UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {}
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2011-07-07 23:56:50 +00:00
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const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
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return RI;
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}
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2007-06-06 07:42:06 +00:00
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static bool isZeroImm(const MachineOperand &op) {
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2008-10-03 15:45:36 +00:00
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return op.isImm() && op.getImm() == 0;
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2007-06-06 07:42:06 +00:00
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsInstrInfo::
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2011-03-04 17:51:39 +00:00
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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2007-06-06 07:42:06 +00:00
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{
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2011-10-11 01:12:52 +00:00
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
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(Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
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(Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
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(Opc == Mips::LDC164_P8)) {
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2011-07-07 18:57:00 +00:00
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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2007-06-06 07:42:06 +00:00
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsInstrInfo::
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2011-03-04 17:51:39 +00:00
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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2007-06-06 07:42:06 +00:00
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{
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2011-10-11 01:12:52 +00:00
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
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(Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
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(Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
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(Opc == Mips::SDC164_P8)) {
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2011-07-07 18:57:00 +00:00
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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2008-08-02 19:42:36 +00:00
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return MI->getOperand(0).getReg();
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2007-06-06 07:42:06 +00:00
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}
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}
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return 0;
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}
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2007-08-18 01:56:48 +00:00
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MipsInstrInfo::
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2011-03-04 17:51:39 +00:00
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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2007-08-18 01:56:48 +00:00
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{
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2010-04-02 20:16:16 +00:00
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DebugLoc DL;
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2009-02-12 00:02:55 +00:00
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BuildMI(MBB, MI, DL, get(Mips::NOP));
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2007-08-18 01:56:48 +00:00
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}
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2010-07-11 01:08:31 +00:00
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void MipsInstrInfo::
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copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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2011-10-03 20:38:08 +00:00
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unsigned Opc = 0, ZeroReg = 0;
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2008-08-02 19:42:36 +00:00
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2011-10-03 20:38:08 +00:00
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if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
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if (Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
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else if (Mips::CCRRegClass.contains(SrcReg))
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Opc = Mips::CFC1;
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2010-07-11 01:08:31 +00:00
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else if (Mips::FGR32RegClass.contains(SrcReg))
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2011-10-03 20:38:08 +00:00
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Opc = Mips::MFC1;
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2010-07-11 01:08:31 +00:00
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else if (SrcReg == Mips::HI)
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2011-10-03 20:38:08 +00:00
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Opc = Mips::MFHI, SrcReg = 0;
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2010-07-11 01:08:31 +00:00
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else if (SrcReg == Mips::LO)
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2011-10-03 20:38:08 +00:00
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Opc = Mips::MFLO, SrcReg = 0;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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}
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2011-10-03 20:38:08 +00:00
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else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
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2010-07-11 01:08:31 +00:00
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if (Mips::CCRRegClass.contains(DestReg))
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2011-10-03 20:38:08 +00:00
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Opc = Mips::CTC1;
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2010-07-11 01:08:31 +00:00
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else if (Mips::FGR32RegClass.contains(DestReg))
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2011-10-03 20:38:08 +00:00
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Opc = Mips::MTC1;
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2010-07-11 01:08:31 +00:00
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else if (DestReg == Mips::HI)
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2011-10-03 20:38:08 +00:00
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Opc = Mips::MTHI, DestReg = 0;
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2010-07-11 01:08:31 +00:00
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else if (DestReg == Mips::LO)
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2011-10-03 20:38:08 +00:00
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Opc = Mips::MTLO, DestReg = 0;
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2010-07-11 01:08:31 +00:00
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}
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2011-10-03 20:38:08 +00:00
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else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
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2011-10-08 03:50:18 +00:00
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Opc = Mips::FMOV_S;
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2011-10-03 20:38:08 +00:00
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else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D32;
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2011-11-07 21:35:45 +00:00
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else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D64;
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2011-10-03 20:38:08 +00:00
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else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
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Opc = Mips::MOVCCRToCCR;
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else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
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if (Mips::CPU64RegsRegClass.contains(SrcReg))
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Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
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else if (SrcReg == Mips::HI64)
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Opc = Mips::MFHI64, SrcReg = 0;
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else if (SrcReg == Mips::LO64)
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Opc = Mips::MFLO64, SrcReg = 0;
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2011-11-07 21:35:45 +00:00
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else if (Mips::FGR64RegClass.contains(SrcReg))
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Opc = Mips::DMFC1;
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2010-07-11 01:08:31 +00:00
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}
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2011-10-03 20:38:08 +00:00
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else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
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if (DestReg == Mips::HI64)
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Opc = Mips::MTHI64, DestReg = 0;
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else if (DestReg == Mips::LO64)
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Opc = Mips::MTLO64, DestReg = 0;
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2011-11-07 21:35:45 +00:00
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else if (Mips::FGR64RegClass.contains(DestReg))
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Opc = Mips::DMTC1;
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2010-07-11 01:08:31 +00:00
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}
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2011-10-03 20:38:08 +00:00
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (ZeroReg)
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MIB.addReg(ZeroReg);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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}
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2011-12-24 03:11:18 +00:00
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static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
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unsigned Flag) {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
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MFI.getObjectSize(FI), Align);
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}
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|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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void MipsInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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2011-03-04 17:51:39 +00:00
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unsigned SrcReg, bool isKill, int FI,
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2010-05-06 19:06:44 +00:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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2010-04-02 20:16:16 +00:00
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DebugLoc DL;
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2009-02-12 00:02:55 +00:00
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if (I != MBB.end()) DL = I->getDebugLoc();
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2011-12-24 03:11:18 +00:00
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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2011-10-11 00:37:28 +00:00
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unsigned Opc = 0;
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2009-02-12 00:02:55 +00:00
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2011-03-04 17:51:39 +00:00
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if (RC == Mips::CPURegsRegisterClass)
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2011-10-11 00:37:28 +00:00
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Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
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else if (RC == Mips::CPU64RegsRegisterClass)
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Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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else if (RC == Mips::FGR32RegisterClass)
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2011-10-11 01:12:52 +00:00
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Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
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2011-10-11 00:37:28 +00:00
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else if (RC == Mips::AFGR64RegisterClass)
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Opc = Mips::SDC1;
|
2011-10-11 01:12:52 +00:00
|
|
|
else if (RC == Mips::FGR64RegisterClass)
|
|
|
|
Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
|
2011-10-11 00:37:28 +00:00
|
|
|
|
|
|
|
assert(Opc && "Register class not handled!");
|
|
|
|
BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
|
2011-12-24 03:11:18 +00:00
|
|
|
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void MipsInstrInfo::
|
|
|
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
|
|
unsigned DestReg, int FI,
|
2010-05-06 19:06:44 +00:00
|
|
|
const TargetRegisterClass *RC,
|
2011-03-04 17:51:39 +00:00
|
|
|
const TargetRegisterInfo *TRI) const
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
{
|
2010-04-02 20:16:16 +00:00
|
|
|
DebugLoc DL;
|
2009-02-12 00:02:55 +00:00
|
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
2011-12-24 03:11:18 +00:00
|
|
|
MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
|
2011-10-11 00:37:28 +00:00
|
|
|
unsigned Opc = 0;
|
2009-11-25 00:36:00 +00:00
|
|
|
|
2011-03-04 17:51:39 +00:00
|
|
|
if (RC == Mips::CPURegsRegisterClass)
|
2011-10-11 00:37:28 +00:00
|
|
|
Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
|
|
|
|
else if (RC == Mips::CPU64RegsRegisterClass)
|
|
|
|
Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
|
2009-11-25 00:36:00 +00:00
|
|
|
else if (RC == Mips::FGR32RegisterClass)
|
2011-10-11 01:12:52 +00:00
|
|
|
Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
|
2011-10-11 00:37:28 +00:00
|
|
|
else if (RC == Mips::AFGR64RegisterClass)
|
|
|
|
Opc = Mips::LDC1;
|
2011-10-11 01:12:52 +00:00
|
|
|
else if (RC == Mips::FGR64RegisterClass)
|
|
|
|
Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
|
2011-10-11 00:37:28 +00:00
|
|
|
|
|
|
|
assert(Opc && "Register class not handled!");
|
2011-12-24 03:11:18 +00:00
|
|
|
BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
|
|
|
|
.addMemOperand(MMO);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2011-07-01 01:04:43 +00:00
|
|
|
MachineInstr*
|
|
|
|
MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
|
|
|
|
uint64_t Offset, const MDNode *MDPtr,
|
|
|
|
DebugLoc DL) const {
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
|
|
|
|
.addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
|
|
|
|
return &*MIB;
|
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-18 01:56:48 +00:00
|
|
|
// Branch Analysis
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
static unsigned GetAnalyzableBrOpc(unsigned Opc) {
|
2011-10-11 18:49:17 +00:00
|
|
|
return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
|
|
|
|
Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
|
|
|
|
Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
|
|
|
|
Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
|
2011-12-12 22:39:35 +00:00
|
|
|
Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
|
|
|
|
Opc == Mips::J) ?
|
2011-10-11 18:49:17 +00:00
|
|
|
Opc : 0;
|
2007-08-18 01:56:48 +00:00
|
|
|
}
|
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
/// GetOppositeBranchOpc - Return the inverse of the specified
|
|
|
|
/// opcode, e.g. turning BEQ to BNE.
|
|
|
|
unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
|
2007-08-18 01:56:48 +00:00
|
|
|
{
|
2011-04-01 17:39:08 +00:00
|
|
|
switch (Opc) {
|
2011-12-19 19:52:25 +00:00
|
|
|
default: llvm_unreachable("Illegal opcode!");
|
|
|
|
case Mips::BEQ: return Mips::BNE;
|
|
|
|
case Mips::BNE: return Mips::BEQ;
|
|
|
|
case Mips::BGTZ: return Mips::BLEZ;
|
|
|
|
case Mips::BGEZ: return Mips::BLTZ;
|
|
|
|
case Mips::BLTZ: return Mips::BGEZ;
|
|
|
|
case Mips::BLEZ: return Mips::BGTZ;
|
|
|
|
case Mips::BEQ64: return Mips::BNE64;
|
|
|
|
case Mips::BNE64: return Mips::BEQ64;
|
|
|
|
case Mips::BGTZ64: return Mips::BLEZ64;
|
|
|
|
case Mips::BGEZ64: return Mips::BLTZ64;
|
|
|
|
case Mips::BLTZ64: return Mips::BGEZ64;
|
|
|
|
case Mips::BLEZ64: return Mips::BGTZ64;
|
|
|
|
case Mips::BC1T: return Mips::BC1F;
|
|
|
|
case Mips::BC1F: return Mips::BC1T;
|
2007-08-18 01:56:48 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
|
|
|
|
MachineBasicBlock *&BB,
|
|
|
|
SmallVectorImpl<MachineOperand>& Cond) {
|
|
|
|
assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
|
|
|
|
int NumOp = Inst->getNumExplicitOperands();
|
|
|
|
|
|
|
|
// for both int and fp branches, the last explicit operand is the
|
|
|
|
// MBB.
|
|
|
|
BB = Inst->getOperand(NumOp-1).getMBB();
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(Opc));
|
|
|
|
|
|
|
|
for (int i=0; i<NumOp-1; i++)
|
|
|
|
Cond.push_back(Inst->getOperand(i));
|
2007-08-18 01:56:48 +00:00
|
|
|
}
|
|
|
|
|
2011-03-04 17:51:39 +00:00
|
|
|
bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
2007-08-18 01:56:48 +00:00
|
|
|
MachineBasicBlock *&TBB,
|
|
|
|
MachineBasicBlock *&FBB,
|
2009-02-09 07:14:22 +00:00
|
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
2011-03-04 17:51:39 +00:00
|
|
|
bool AllowModify) const
|
2007-08-18 01:56:48 +00:00
|
|
|
{
|
2011-04-01 17:39:08 +00:00
|
|
|
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
|
|
|
|
|
|
|
|
// Skip all the debug instructions.
|
|
|
|
while (I != REnd && I->isDebugValue())
|
|
|
|
++I;
|
|
|
|
|
|
|
|
if (I == REnd || !isUnpredicatedTerminator(&*I)) {
|
|
|
|
// If this block ends with no branches (it just falls through to its succ)
|
|
|
|
// just return false, leaving TBB/FBB null.
|
|
|
|
TBB = FBB = NULL;
|
2010-04-02 01:38:09 +00:00
|
|
|
return false;
|
|
|
|
}
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
MachineInstr *LastInst = &*I;
|
2007-08-18 01:56:48 +00:00
|
|
|
unsigned LastOpc = LastInst->getOpcode();
|
2011-04-01 17:39:08 +00:00
|
|
|
|
|
|
|
// Not an analyzable branch (must be an indirect jump).
|
|
|
|
if (!GetAnalyzableBrOpc(LastOpc))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Get the second to last instruction in the block.
|
|
|
|
unsigned SecondLastOpc = 0;
|
|
|
|
MachineInstr *SecondLastInst = NULL;
|
|
|
|
|
|
|
|
if (++I != REnd) {
|
|
|
|
SecondLastInst = &*I;
|
|
|
|
SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
|
|
|
|
|
|
|
|
// Not an analyzable branch (must be an indirect jump).
|
|
|
|
if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
|
2007-08-18 01:56:48 +00:00
|
|
|
return true;
|
2011-04-01 17:39:08 +00:00
|
|
|
}
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
// If there is only one terminator instruction, process it.
|
|
|
|
if (!SecondLastOpc) {
|
2007-08-18 01:56:48 +00:00
|
|
|
// Unconditional branch
|
2011-12-12 22:39:35 +00:00
|
|
|
if (LastOpc == UncondBrOpc) {
|
2007-12-30 23:10:15 +00:00
|
|
|
TBB = LastInst->getOperand(0).getMBB();
|
2007-08-18 01:56:48 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Conditional branch
|
2011-04-01 17:39:08 +00:00
|
|
|
AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
|
|
|
|
return false;
|
2007-08-18 01:56:48 +00:00
|
|
|
}
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
// If we reached here, there are two branches.
|
2007-08-18 01:56:48 +00:00
|
|
|
// If there are three terminators, we don't know what sort of block this is.
|
2011-04-01 17:39:08 +00:00
|
|
|
if (++I != REnd && isUnpredicatedTerminator(&*I))
|
2007-08-18 01:56:48 +00:00
|
|
|
return true;
|
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
// If second to last instruction is an unconditional branch,
|
|
|
|
// analyze it and remove the last instruction.
|
2011-12-12 22:39:35 +00:00
|
|
|
if (SecondLastOpc == UncondBrOpc) {
|
2011-04-01 17:39:08 +00:00
|
|
|
// Return if the last instruction cannot be removed.
|
|
|
|
if (!AllowModify)
|
|
|
|
return true;
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
TBB = SecondLastInst->getOperand(0).getMBB();
|
|
|
|
LastInst->eraseFromParent();
|
|
|
|
return false;
|
|
|
|
}
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
// Conditional branch followed by an unconditional branch.
|
|
|
|
// The last one must be unconditional.
|
2011-12-12 22:39:35 +00:00
|
|
|
if (LastOpc != UncondBrOpc)
|
2011-04-01 17:39:08 +00:00
|
|
|
return true;
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
|
|
|
|
FBB = LastInst->getOperand(0).getMBB();
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock *TBB, DebugLoc DL,
|
|
|
|
const SmallVectorImpl<MachineOperand>& Cond)
|
|
|
|
const {
|
|
|
|
unsigned Opc = Cond[0].getImm();
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &MCID = get(Opc);
|
|
|
|
MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
for (unsigned i = 1; i < Cond.size(); ++i)
|
|
|
|
MIB.addReg(Cond[i].getReg());
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
MIB.addMBB(TBB);
|
2007-08-18 01:56:48 +00:00
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
unsigned MipsInstrInfo::
|
2011-03-04 17:51:39 +00:00
|
|
|
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
2008-08-14 22:49:33 +00:00
|
|
|
MachineBasicBlock *FBB,
|
2010-06-17 22:43:56 +00:00
|
|
|
const SmallVectorImpl<MachineOperand> &Cond,
|
|
|
|
DebugLoc DL) const {
|
2007-08-18 01:56:48 +00:00
|
|
|
// Shouldn't be a fall through.
|
|
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
// # of condition operands:
|
|
|
|
// Unconditional branches: 0
|
|
|
|
// Floating point branches: 1 (opc)
|
|
|
|
// Int BranchZero: 2 (opc, reg)
|
|
|
|
// Int Branch: 3 (opc, reg0, reg1)
|
|
|
|
assert((Cond.size() <= 3) &&
|
|
|
|
"# of Mips branch conditions must be <= 3!");
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2007-08-18 01:56:48 +00:00
|
|
|
// Two-way Conditional branch.
|
2011-04-01 17:39:08 +00:00
|
|
|
if (FBB) {
|
|
|
|
BuildCondBr(MBB, TBB, DL, Cond);
|
2011-12-12 22:39:35 +00:00
|
|
|
BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
|
2011-04-01 17:39:08 +00:00
|
|
|
return 2;
|
|
|
|
}
|
2007-08-18 01:56:48 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
// One way branch.
|
|
|
|
// Unconditional branch.
|
|
|
|
if (Cond.empty())
|
2011-12-12 22:39:35 +00:00
|
|
|
BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
|
2011-04-01 17:39:08 +00:00
|
|
|
else // Conditional branch.
|
|
|
|
BuildCondBr(MBB, TBB, DL, Cond);
|
|
|
|
return 1;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2007-08-18 01:56:48 +00:00
|
|
|
|
|
|
|
unsigned MipsInstrInfo::
|
2011-03-04 17:51:39 +00:00
|
|
|
RemoveBranch(MachineBasicBlock &MBB) const
|
2007-08-18 01:56:48 +00:00
|
|
|
{
|
2011-04-01 17:39:08 +00:00
|
|
|
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
|
|
|
|
MachineBasicBlock::reverse_iterator FirstBr;
|
|
|
|
unsigned removed;
|
|
|
|
|
|
|
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// Skip all the debug instructions.
|
|
|
|
while (I != REnd && I->isDebugValue())
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|
|
|
++I;
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2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
FirstBr = I;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
// Up to 2 branches are removed.
|
|
|
|
// Note that indirect branches are not removed.
|
|
|
|
for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
|
|
|
|
if (!GetAnalyzableBrOpc(I->getOpcode()))
|
|
|
|
break;
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
MBB.erase(I.base(), FirstBr.base());
|
2011-03-04 17:51:39 +00:00
|
|
|
|
2011-04-01 17:39:08 +00:00
|
|
|
return removed;
|
2007-08-18 01:56:48 +00:00
|
|
|
}
|
|
|
|
|
2011-03-04 17:51:39 +00:00
|
|
|
/// ReverseBranchCondition - Return the inverse opcode of the
|
2007-08-18 01:56:48 +00:00
|
|
|
/// specified Branch instruction.
|
|
|
|
bool MipsInstrInfo::
|
2011-03-04 17:51:39 +00:00
|
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
|
2007-08-18 01:56:48 +00:00
|
|
|
{
|
2011-04-01 17:39:08 +00:00
|
|
|
assert( (Cond.size() && Cond.size() <= 3) &&
|
2007-08-18 01:56:48 +00:00
|
|
|
"Invalid Mips branch condition!");
|
2011-04-01 17:39:08 +00:00
|
|
|
Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
|
2007-08-18 01:56:48 +00:00
|
|
|
return false;
|
|
|
|
}
|
2009-06-03 20:30:14 +00:00
|
|
|
|
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
|
|
/// the global base register value. Output instructions required to
|
|
|
|
/// initialize the register in the function entry block, if necessary.
|
|
|
|
///
|
|
|
|
unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
|
|
|
|
MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
|
|
|
|
unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
|
|
|
|
if (GlobalBaseReg != 0)
|
|
|
|
return GlobalBaseReg;
|
|
|
|
|
|
|
|
// Insert the set of GlobalBaseReg into the first MBB of the function
|
|
|
|
MachineBasicBlock &FirstMBB = MF->front();
|
|
|
|
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
|
|
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
2012-02-03 04:33:00 +00:00
|
|
|
unsigned GP = IsN64 ? Mips::GP_64 : Mips::GP;
|
|
|
|
const TargetRegisterClass *RC
|
|
|
|
= IsN64 ? Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
|
2009-06-03 20:30:14 +00:00
|
|
|
|
2012-02-03 04:33:00 +00:00
|
|
|
GlobalBaseReg = RegInfo.createVirtualRegister(RC);
|
2010-07-10 22:43:03 +00:00
|
|
|
BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
|
2012-02-03 04:33:00 +00:00
|
|
|
GlobalBaseReg).addReg(GP);
|
|
|
|
RegInfo.addLiveIn(GP);
|
2009-06-03 20:30:14 +00:00
|
|
|
|
|
|
|
MipsFI->setGlobalBaseReg(GlobalBaseReg);
|
|
|
|
return GlobalBaseReg;
|
|
|
|
}
|