2013-03-14 19:09:52 +00:00
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//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
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2013-03-13 00:54:29 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEISelLowering.h"
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#include "MipsRegisterInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2013-04-13 02:13:30 +00:00
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#include "llvm/IR/Intrinsics.h"
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2013-03-13 00:54:29 +00:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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static cl::opt<bool>
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EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
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cl::desc("MIPS: Enable tail calls."), cl::init(false));
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2013-09-07 00:52:30 +00:00
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static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
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cl::desc("Expand double precision loads and "
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"stores to their single precision "
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"counterparts"));
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2013-03-13 00:54:29 +00:00
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MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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: MipsTargetLowering(TM) {
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// Set up the register classes
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2013-04-09 19:46:01 +00:00
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clearRegisterClasses();
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2013-08-06 23:08:38 +00:00
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addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
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2013-03-13 00:54:29 +00:00
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if (HasMips64)
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2013-08-06 23:08:38 +00:00
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addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
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2013-03-13 00:54:29 +00:00
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if (Subtarget->hasDSP()) {
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MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
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for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
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2013-08-14 00:53:38 +00:00
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addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
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2013-03-13 00:54:29 +00:00
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// Expand all builtin opcodes.
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for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
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setOperationAction(Opc, VecTys[i], Expand);
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2013-04-13 00:55:41 +00:00
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setOperationAction(ISD::ADD, VecTys[i], Legal);
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setOperationAction(ISD::SUB, VecTys[i], Legal);
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2013-03-13 00:54:29 +00:00
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setOperationAction(ISD::LOAD, VecTys[i], Legal);
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setOperationAction(ISD::STORE, VecTys[i], Legal);
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setOperationAction(ISD::BITCAST, VecTys[i], Legal);
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}
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2013-04-19 23:21:32 +00:00
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2013-08-02 19:23:33 +00:00
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// Expand all truncating stores and extending loads.
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unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
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for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
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for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
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setTruncStoreAction((MVT::SimpleValueType)VT0,
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(MVT::SimpleValueType)VT1, Expand);
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setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
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setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
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}
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2013-04-19 23:21:32 +00:00
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRL);
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2013-04-30 22:37:26 +00:00
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setTargetDAGCombine(ISD::SETCC);
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setTargetDAGCombine(ISD::VSELECT);
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2013-03-13 00:54:29 +00:00
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}
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2013-04-13 00:55:41 +00:00
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if (Subtarget->hasDSPR2())
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setOperationAction(ISD::MUL, MVT::v2i16, Legal);
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2013-08-13 20:54:07 +00:00
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if (Subtarget->hasMSA()) {
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2013-09-11 10:15:48 +00:00
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addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
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addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
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addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
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addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
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addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
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addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
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addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
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2013-09-23 13:22:24 +00:00
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2013-09-23 14:03:12 +00:00
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::SRA);
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2013-09-24 12:04:44 +00:00
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setTargetDAGCombine(ISD::VSELECT);
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2013-09-23 13:22:24 +00:00
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setTargetDAGCombine(ISD::XOR);
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2013-08-13 20:54:07 +00:00
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}
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2013-08-30 19:40:56 +00:00
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if (!Subtarget->mipsSEUsesSoftFloat()) {
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2013-03-13 00:54:29 +00:00
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addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
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// When dealing with single precision only, use libcalls
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if (!Subtarget->isSingleFloat()) {
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2013-08-20 23:38:40 +00:00
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if (Subtarget->isFP64bit())
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2013-03-13 00:54:29 +00:00
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addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
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else
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addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
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}
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}
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2013-03-30 01:36:35 +00:00
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::MULHS, MVT::i32, Custom);
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setOperationAction(ISD::MULHU, MVT::i32, Custom);
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2013-04-11 19:29:26 +00:00
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if (HasMips64) {
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setOperationAction(ISD::MULHS, MVT::i64, Custom);
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setOperationAction(ISD::MULHU, MVT::i64, Custom);
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2013-03-30 01:36:35 +00:00
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setOperationAction(ISD::MUL, MVT::i64, Custom);
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2013-04-11 19:29:26 +00:00
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}
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2013-03-30 01:36:35 +00:00
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2013-04-13 02:13:30 +00:00
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
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2013-03-30 01:36:35 +00:00
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setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
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2013-03-13 00:54:29 +00:00
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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2013-03-30 01:42:24 +00:00
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setTargetDAGCombine(ISD::ADDE);
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setTargetDAGCombine(ISD::SUBE);
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2013-06-26 18:48:17 +00:00
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setTargetDAGCombine(ISD::MUL);
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2013-03-30 01:42:24 +00:00
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2013-08-28 12:14:50 +00:00
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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2013-08-28 12:04:29 +00:00
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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2013-09-07 00:52:30 +00:00
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if (NoDPLoadStore) {
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setOperationAction(ISD::LOAD, MVT::f64, Custom);
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setOperationAction(ISD::STORE, MVT::f64, Custom);
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}
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2013-03-13 00:54:29 +00:00
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computeRegisterProperties();
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}
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const MipsTargetLowering *
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llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
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return new MipsSETargetLowering(TM);
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}
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2013-09-23 12:02:46 +00:00
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// Enable MSA support for the given integer type and Register class.
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2013-08-23 10:10:13 +00:00
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void MipsSETargetLowering::
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2013-09-11 10:15:48 +00:00
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addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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addRegisterClass(Ty, RC);
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// Expand all builtin opcodes.
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for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
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setOperationAction(Opc, Ty, Expand);
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setOperationAction(ISD::BITCAST, Ty, Legal);
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setOperationAction(ISD::LOAD, Ty, Legal);
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setOperationAction(ISD::STORE, Ty, Legal);
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2013-09-23 14:03:12 +00:00
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
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2013-09-23 12:02:46 +00:00
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setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
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2013-09-11 10:15:48 +00:00
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2013-09-11 10:28:16 +00:00
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setOperationAction(ISD::ADD, Ty, Legal);
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2013-09-23 12:57:42 +00:00
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setOperationAction(ISD::AND, Ty, Legal);
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2013-09-11 11:58:30 +00:00
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setOperationAction(ISD::CTLZ, Ty, Legal);
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2013-09-23 13:40:21 +00:00
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setOperationAction(ISD::CTPOP, Ty, Legal);
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2013-09-11 11:58:30 +00:00
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setOperationAction(ISD::MUL, Ty, Legal);
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2013-09-23 12:57:42 +00:00
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setOperationAction(ISD::OR, Ty, Legal);
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2013-09-11 10:38:58 +00:00
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setOperationAction(ISD::SDIV, Ty, Legal);
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2013-09-11 11:58:30 +00:00
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setOperationAction(ISD::SHL, Ty, Legal);
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setOperationAction(ISD::SRA, Ty, Legal);
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setOperationAction(ISD::SRL, Ty, Legal);
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setOperationAction(ISD::SUB, Ty, Legal);
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2013-09-11 10:38:58 +00:00
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setOperationAction(ISD::UDIV, Ty, Legal);
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2013-09-24 12:04:44 +00:00
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setOperationAction(ISD::VSELECT, Ty, Legal);
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2013-09-23 12:57:42 +00:00
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setOperationAction(ISD::XOR, Ty, Legal);
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2013-09-24 10:46:19 +00:00
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setOperationAction(ISD::SETCC, Ty, Legal);
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setCondCodeAction(ISD::SETNE, Ty, Expand);
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setCondCodeAction(ISD::SETGE, Ty, Expand);
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setCondCodeAction(ISD::SETGT, Ty, Expand);
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setCondCodeAction(ISD::SETUGE, Ty, Expand);
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setCondCodeAction(ISD::SETUGT, Ty, Expand);
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2013-09-11 10:15:48 +00:00
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}
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2013-09-23 12:02:46 +00:00
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// Enable MSA support for the given floating-point type and Register class.
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2013-09-11 10:15:48 +00:00
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void MipsSETargetLowering::
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addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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2013-08-23 10:10:13 +00:00
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addRegisterClass(Ty, RC);
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 12:24:57 +00:00
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// Expand all builtin opcodes.
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for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
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setOperationAction(Opc, Ty, Expand);
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setOperationAction(ISD::LOAD, Ty, Legal);
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setOperationAction(ISD::STORE, Ty, Legal);
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setOperationAction(ISD::BITCAST, Ty, Legal);
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2013-09-23 14:03:12 +00:00
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
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2013-09-11 10:51:30 +00:00
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if (Ty != MVT::v8f16) {
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2013-09-24 13:02:08 +00:00
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setOperationAction(ISD::FABS, Ty, Legal);
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2013-09-11 10:51:30 +00:00
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setOperationAction(ISD::FADD, Ty, Legal);
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setOperationAction(ISD::FDIV, Ty, Legal);
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setOperationAction(ISD::FLOG2, Ty, Legal);
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setOperationAction(ISD::FMUL, Ty, Legal);
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setOperationAction(ISD::FRINT, Ty, Legal);
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setOperationAction(ISD::FSQRT, Ty, Legal);
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setOperationAction(ISD::FSUB, Ty, Legal);
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2013-09-24 12:04:44 +00:00
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setOperationAction(ISD::VSELECT, Ty, Legal);
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2013-09-24 10:46:19 +00:00
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setOperationAction(ISD::SETCC, Ty, Legal);
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setCondCodeAction(ISD::SETOGE, Ty, Expand);
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setCondCodeAction(ISD::SETOGT, Ty, Expand);
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setCondCodeAction(ISD::SETUGE, Ty, Expand);
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setCondCodeAction(ISD::SETUGT, Ty, Expand);
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setCondCodeAction(ISD::SETGE, Ty, Expand);
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setCondCodeAction(ISD::SETGT, Ty, Expand);
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2013-09-11 10:51:30 +00:00
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}
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 12:24:57 +00:00
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}
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2013-03-13 00:54:29 +00:00
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bool
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MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
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MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
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switch (SVT) {
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case MVT::i64:
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case MVT::i32:
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if (Fast)
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*Fast = true;
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return true;
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default:
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return false;
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}
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}
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2013-03-30 01:36:35 +00:00
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SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch(Op.getOpcode()) {
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2013-09-07 00:52:30 +00:00
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case ISD::LOAD: return lowerLOAD(Op, DAG);
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case ISD::STORE: return lowerSTORE(Op, DAG);
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2013-03-30 01:36:35 +00:00
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case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
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case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
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case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
|
|
|
|
case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
|
|
|
|
case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
|
|
|
|
case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
|
2013-04-22 20:13:37 +00:00
|
|
|
case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
|
|
|
|
DAG);
|
2013-04-13 02:13:30 +00:00
|
|
|
case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
|
|
|
|
case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
|
2013-08-28 12:04:29 +00:00
|
|
|
case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
|
2013-09-23 14:03:12 +00:00
|
|
|
case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
|
2013-09-23 12:02:46 +00:00
|
|
|
case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
|
2013-03-30 01:36:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return MipsTargetLowering::LowerOperation(Op, DAG);
|
|
|
|
}
|
|
|
|
|
2013-03-30 01:42:24 +00:00
|
|
|
// selectMADD -
|
|
|
|
// Transforms a subgraph in CurDAG if the following pattern is found:
|
|
|
|
// (addc multLo, Lo0), (adde multHi, Hi0),
|
|
|
|
// where,
|
|
|
|
// multHi/Lo: product of multiplication
|
|
|
|
// Lo0: initial value of Lo register
|
|
|
|
// Hi0: initial value of Hi register
|
|
|
|
// Return true if pattern matching was successful.
|
|
|
|
static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
|
|
|
|
// ADDENode's second operand must be a flag output of an ADDC node in order
|
|
|
|
// for the matching to be successful.
|
|
|
|
SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
|
|
|
|
|
|
|
|
if (ADDCNode->getOpcode() != ISD::ADDC)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue MultHi = ADDENode->getOperand(0);
|
|
|
|
SDValue MultLo = ADDCNode->getOperand(0);
|
|
|
|
SDNode *MultNode = MultHi.getNode();
|
|
|
|
unsigned MultOpc = MultHi.getOpcode();
|
|
|
|
|
|
|
|
// MultHi and MultLo must be generated by the same node,
|
|
|
|
if (MultLo.getNode() != MultNode)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// and it must be a multiplication.
|
|
|
|
if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// MultLo amd MultHi must be the first and second output of MultNode
|
|
|
|
// respectively.
|
|
|
|
if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Transform this to a MADD only if ADDENode and ADDCNode are the only users
|
|
|
|
// of the values of MultNode, in which case MultNode will be removed in later
|
|
|
|
// phases.
|
|
|
|
// If there exist users other than ADDENode or ADDCNode, this function returns
|
|
|
|
// here, which will result in MultNode being mapped to a single MULT
|
|
|
|
// instruction node rather than a pair of MULT and MADD instructions being
|
|
|
|
// produced.
|
|
|
|
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(ADDENode);
|
2013-03-30 01:42:24 +00:00
|
|
|
|
|
|
|
// Initialize accumulator.
|
|
|
|
SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
|
|
|
|
ADDCNode->getOperand(1),
|
|
|
|
ADDENode->getOperand(1));
|
|
|
|
|
|
|
|
// create MipsMAdd(u) node
|
|
|
|
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
|
|
|
|
|
|
|
|
SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
|
|
|
|
MultNode->getOperand(0),// Factor 0
|
|
|
|
MultNode->getOperand(1),// Factor 1
|
|
|
|
ACCIn);
|
|
|
|
|
|
|
|
// replace uses of adde and addc here
|
|
|
|
if (!SDValue(ADDCNode, 0).use_empty()) {
|
|
|
|
SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
|
|
|
|
SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
|
|
|
|
LoIdx);
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
|
|
|
|
}
|
|
|
|
if (!SDValue(ADDENode, 0).use_empty()) {
|
|
|
|
SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
|
|
|
|
SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
|
|
|
|
HiIdx);
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// selectMSUB -
|
|
|
|
// Transforms a subgraph in CurDAG if the following pattern is found:
|
|
|
|
// (addc Lo0, multLo), (sube Hi0, multHi),
|
|
|
|
// where,
|
|
|
|
// multHi/Lo: product of multiplication
|
|
|
|
// Lo0: initial value of Lo register
|
|
|
|
// Hi0: initial value of Hi register
|
|
|
|
// Return true if pattern matching was successful.
|
|
|
|
static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
|
|
|
|
// SUBENode's second operand must be a flag output of an SUBC node in order
|
|
|
|
// for the matching to be successful.
|
|
|
|
SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
|
|
|
|
|
|
|
|
if (SUBCNode->getOpcode() != ISD::SUBC)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue MultHi = SUBENode->getOperand(1);
|
|
|
|
SDValue MultLo = SUBCNode->getOperand(1);
|
|
|
|
SDNode *MultNode = MultHi.getNode();
|
|
|
|
unsigned MultOpc = MultHi.getOpcode();
|
|
|
|
|
|
|
|
// MultHi and MultLo must be generated by the same node,
|
|
|
|
if (MultLo.getNode() != MultNode)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// and it must be a multiplication.
|
|
|
|
if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// MultLo amd MultHi must be the first and second output of MultNode
|
|
|
|
// respectively.
|
|
|
|
if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Transform this to a MSUB only if SUBENode and SUBCNode are the only users
|
|
|
|
// of the values of MultNode, in which case MultNode will be removed in later
|
|
|
|
// phases.
|
|
|
|
// If there exist users other than SUBENode or SUBCNode, this function returns
|
|
|
|
// here, which will result in MultNode being mapped to a single MULT
|
|
|
|
// instruction node rather than a pair of MULT and MSUB instructions being
|
|
|
|
// produced.
|
|
|
|
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(SUBENode);
|
2013-03-30 01:42:24 +00:00
|
|
|
|
|
|
|
// Initialize accumulator.
|
|
|
|
SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
|
|
|
|
SUBCNode->getOperand(0),
|
|
|
|
SUBENode->getOperand(0));
|
|
|
|
|
|
|
|
// create MipsSub(u) node
|
|
|
|
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
|
|
|
|
|
|
|
|
SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
|
|
|
|
MultNode->getOperand(0),// Factor 0
|
|
|
|
MultNode->getOperand(1),// Factor 1
|
|
|
|
ACCIn);
|
|
|
|
|
|
|
|
// replace uses of sube and subc here
|
|
|
|
if (!SDValue(SUBCNode, 0).use_empty()) {
|
|
|
|
SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
|
|
|
|
SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
|
|
|
|
LoIdx);
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
|
|
|
|
}
|
|
|
|
if (!SDValue(SUBENode, 0).use_empty()) {
|
|
|
|
SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
|
|
|
|
SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
|
|
|
|
HiIdx);
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalize())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
|
|
|
|
selectMADD(N, &DAG))
|
|
|
|
return SDValue(N, 0);
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2013-09-23 14:03:12 +00:00
|
|
|
// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
|
|
|
|
//
|
|
|
|
// Performs the following transformations:
|
|
|
|
// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
|
|
|
|
// sign/zero-extension is completely overwritten by the new one performed by
|
|
|
|
// the ISD::AND.
|
|
|
|
// - Removes redundant zero extensions performed by an ISD::AND.
|
|
|
|
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
if (!Subtarget->hasMSA())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue Op0 = N->getOperand(0);
|
|
|
|
SDValue Op1 = N->getOperand(1);
|
|
|
|
unsigned Op0Opcode = Op0->getOpcode();
|
|
|
|
|
|
|
|
// (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
|
|
|
|
// where $d + 1 == 2^n and n == 32
|
|
|
|
// or $d + 1 == 2^n and n <= 32 and ZExt
|
|
|
|
// -> (MipsVExtractZExt $a, $b, $c)
|
|
|
|
if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
|
|
|
|
Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
|
|
|
|
ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
|
|
|
|
|
|
|
|
if (!Mask)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
|
|
|
|
|
|
|
|
if (Log2IfPositive <= 0)
|
|
|
|
return SDValue(); // Mask+1 is not a power of 2
|
|
|
|
|
|
|
|
SDValue Op0Op2 = Op0->getOperand(2);
|
|
|
|
EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
|
|
|
|
unsigned ExtendTySize = ExtendTy.getSizeInBits();
|
|
|
|
unsigned Log2 = Log2IfPositive;
|
|
|
|
|
|
|
|
if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
|
|
|
|
Log2 == ExtendTySize) {
|
|
|
|
SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
|
|
|
|
DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
|
|
|
|
Op0->getVTList(), Ops, Op0->getNumOperands());
|
|
|
|
return Op0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2013-03-30 01:42:24 +00:00
|
|
|
static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalize())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
|
|
|
|
selectMSUB(N, &DAG))
|
|
|
|
return SDValue(N, 0);
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2013-06-26 18:48:17 +00:00
|
|
|
static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
|
|
|
|
EVT ShiftTy, SelectionDAG &DAG) {
|
|
|
|
// Clear the upper (64 - VT.sizeInBits) bits.
|
|
|
|
C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
|
|
|
|
|
|
|
|
// Return 0.
|
|
|
|
if (C == 0)
|
|
|
|
return DAG.getConstant(0, VT);
|
|
|
|
|
|
|
|
// Return x.
|
|
|
|
if (C == 1)
|
|
|
|
return X;
|
|
|
|
|
|
|
|
// If c is power of 2, return (shl x, log2(c)).
|
|
|
|
if (isPowerOf2_64(C))
|
|
|
|
return DAG.getNode(ISD::SHL, DL, VT, X,
|
|
|
|
DAG.getConstant(Log2_64(C), ShiftTy));
|
|
|
|
|
|
|
|
unsigned Log2Ceil = Log2_64_Ceil(C);
|
|
|
|
uint64_t Floor = 1LL << Log2_64(C);
|
|
|
|
uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
|
|
|
|
|
|
|
|
// If |c - floor_c| <= |c - ceil_c|,
|
|
|
|
// where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
|
|
|
|
// return (add constMult(x, floor_c), constMult(x, c - floor_c)).
|
|
|
|
if (C - Floor <= Ceil - C) {
|
|
|
|
SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
|
|
|
|
SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
|
|
|
|
return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
|
|
|
|
}
|
|
|
|
|
|
|
|
// If |c - floor_c| > |c - ceil_c|,
|
|
|
|
// return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
|
|
|
|
SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
|
|
|
|
SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
|
|
|
|
return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
const TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSETargetLowering *TL) {
|
|
|
|
EVT VT = N->getValueType(0);
|
|
|
|
|
|
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
|
|
|
|
if (!VT.isVector())
|
|
|
|
return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
|
|
|
|
VT, TL->getScalarShiftAmountTy(VT), DAG);
|
|
|
|
|
|
|
|
return SDValue(N, 0);
|
|
|
|
}
|
|
|
|
|
2013-04-19 23:21:32 +00:00
|
|
|
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
|
|
|
|
SelectionDAG &DAG,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
// See if this is a vector splat immediate node.
|
|
|
|
APInt SplatValue, SplatUndef;
|
|
|
|
unsigned SplatBitSize;
|
|
|
|
bool HasAnyUndefs;
|
|
|
|
unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
|
|
|
|
BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
|
|
|
|
|
2013-04-22 19:58:23 +00:00
|
|
|
if (!BV ||
|
2013-04-22 20:13:37 +00:00
|
|
|
!BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
|
2013-04-23 18:09:42 +00:00
|
|
|
EltSize, !Subtarget->isLittle()) ||
|
2013-04-22 19:58:23 +00:00
|
|
|
(SplatBitSize != EltSize) ||
|
2013-04-23 18:09:42 +00:00
|
|
|
(SplatValue.getZExtValue() >= EltSize))
|
2013-04-19 23:21:32 +00:00
|
|
|
return SDValue();
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
|
2013-04-19 23:21:32 +00:00
|
|
|
DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
EVT Ty = N->getValueType(0);
|
|
|
|
|
|
|
|
if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
|
|
|
|
}
|
|
|
|
|
2013-09-23 14:03:12 +00:00
|
|
|
// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
|
|
|
|
// constant splats into MipsISD::SHRA_DSP for DSPr2.
|
|
|
|
//
|
|
|
|
// Performs the following transformations:
|
|
|
|
// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
|
|
|
|
// sign/zero-extension is completely overwritten by the new one performed by
|
|
|
|
// the ISD::SRA and ISD::SHL nodes.
|
|
|
|
// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
|
|
|
|
// sequence.
|
|
|
|
//
|
|
|
|
// See performDSPShiftCombine for more information about the transformation
|
|
|
|
// used for DSPr2.
|
2013-04-19 23:21:32 +00:00
|
|
|
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
EVT Ty = N->getValueType(0);
|
|
|
|
|
2013-09-23 14:03:12 +00:00
|
|
|
if (Subtarget->hasMSA()) {
|
|
|
|
SDValue Op0 = N->getOperand(0);
|
|
|
|
SDValue Op1 = N->getOperand(1);
|
|
|
|
|
|
|
|
// (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
|
|
|
|
// where $d + sizeof($c) == 32
|
|
|
|
// or $d + sizeof($c) <= 32 and SExt
|
|
|
|
// -> (MipsVExtractSExt $a, $b, $c)
|
|
|
|
if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
|
|
|
|
SDValue Op0Op0 = Op0->getOperand(0);
|
|
|
|
ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
|
|
|
|
|
|
|
|
if (!ShAmount)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
|
|
|
|
unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
|
|
|
|
|
|
|
|
if (TotalBits == 32 ||
|
|
|
|
(Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
|
|
|
|
TotalBits <= 32)) {
|
|
|
|
SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
|
|
|
|
Op0Op0->getOperand(2) };
|
|
|
|
DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
|
|
|
|
Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
|
|
|
|
return Op0Op0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-19 23:21:32 +00:00
|
|
|
if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
EVT Ty = N->getValueType(0);
|
|
|
|
|
|
|
|
if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
|
|
|
|
}
|
|
|
|
|
2013-04-30 22:37:26 +00:00
|
|
|
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
|
|
|
|
bool IsV216 = (Ty == MVT::v2i16);
|
|
|
|
|
|
|
|
switch (CC) {
|
|
|
|
case ISD::SETEQ:
|
|
|
|
case ISD::SETNE: return true;
|
|
|
|
case ISD::SETLT:
|
|
|
|
case ISD::SETLE:
|
|
|
|
case ISD::SETGT:
|
|
|
|
case ISD::SETGE: return IsV216;
|
|
|
|
case ISD::SETULT:
|
|
|
|
case ISD::SETULE:
|
|
|
|
case ISD::SETUGT:
|
|
|
|
case ISD::SETUGE: return !IsV216;
|
|
|
|
default: return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
|
|
|
|
EVT Ty = N->getValueType(0);
|
|
|
|
|
|
|
|
if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
|
|
|
|
return SDValue();
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
|
2013-04-30 22:37:26 +00:00
|
|
|
N->getOperand(1), N->getOperand(2));
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
|
|
|
|
EVT Ty = N->getValueType(0);
|
|
|
|
|
2013-09-24 12:18:31 +00:00
|
|
|
if (Ty.is128BitVector() && Ty.isInteger()) {
|
|
|
|
// Try the following combines:
|
|
|
|
// (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
|
|
|
|
// (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
|
|
|
|
// (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
|
|
|
|
// (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
|
|
|
|
// (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
|
|
|
|
// (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
|
|
|
|
// (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
|
|
|
|
// (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
|
|
|
|
// SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
|
|
|
|
// will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
|
|
|
|
// legalizer.
|
|
|
|
SDValue Op0 = N->getOperand(0);
|
|
|
|
|
|
|
|
if (Op0->getOpcode() != ISD::SETCC)
|
|
|
|
return SDValue();
|
2013-04-30 22:37:26 +00:00
|
|
|
|
2013-09-24 12:18:31 +00:00
|
|
|
ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
|
|
|
|
bool Signed;
|
2013-04-30 22:37:26 +00:00
|
|
|
|
2013-09-24 12:18:31 +00:00
|
|
|
if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
|
|
|
|
Signed = true;
|
|
|
|
else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
|
|
|
|
Signed = false;
|
|
|
|
else
|
|
|
|
return SDValue();
|
2013-04-30 22:37:26 +00:00
|
|
|
|
2013-09-24 12:18:31 +00:00
|
|
|
SDValue Op1 = N->getOperand(1);
|
|
|
|
SDValue Op2 = N->getOperand(2);
|
|
|
|
SDValue Op0Op0 = Op0->getOperand(0);
|
|
|
|
SDValue Op0Op1 = Op0->getOperand(1);
|
|
|
|
|
|
|
|
if (Op1 == Op0Op0 && Op2 == Op0Op1)
|
|
|
|
return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
|
|
|
|
Ty, Op1, Op2);
|
|
|
|
else if (Op1 == Op0Op1 && Op2 == Op0Op0)
|
|
|
|
return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
|
|
|
|
Ty, Op1, Op2);
|
|
|
|
} else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
|
|
|
|
SDValue SetCC = N->getOperand(0);
|
|
|
|
|
|
|
|
if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
|
|
|
|
SetCC.getOperand(0), SetCC.getOperand(1),
|
|
|
|
N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
2013-04-30 22:37:26 +00:00
|
|
|
}
|
|
|
|
|
2013-09-23 13:22:24 +00:00
|
|
|
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
|
|
|
|
const MipsSubtarget *Subtarget) {
|
|
|
|
EVT Ty = N->getValueType(0);
|
|
|
|
|
|
|
|
if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
|
|
|
|
// Try the following combines:
|
|
|
|
// (xor (or $a, $b), (build_vector allones))
|
|
|
|
// (xor (or $a, $b), (bitcast (build_vector allones)))
|
|
|
|
SDValue Op0 = N->getOperand(0);
|
|
|
|
SDValue Op1 = N->getOperand(1);
|
|
|
|
SDValue NotOp;
|
|
|
|
ConstantSDNode *Const;
|
|
|
|
|
|
|
|
if (ISD::isBuildVectorAllOnes(Op0.getNode()))
|
|
|
|
NotOp = Op1;
|
|
|
|
else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
|
|
|
|
NotOp = Op0;
|
|
|
|
else if ((Op0->getOpcode() == MipsISD::VSPLAT ||
|
|
|
|
Op0->getOpcode() == MipsISD::VSPLATD) &&
|
|
|
|
(Const = dyn_cast<ConstantSDNode>(Op0->getOperand(0))) &&
|
|
|
|
Const->isAllOnesValue())
|
|
|
|
NotOp = Op1;
|
|
|
|
else if ((Op1->getOpcode() == MipsISD::VSPLAT ||
|
|
|
|
Op1->getOpcode() == MipsISD::VSPLATD) &&
|
|
|
|
(Const = dyn_cast<ConstantSDNode>(Op1->getOperand(0))) &&
|
|
|
|
Const->isAllOnesValue())
|
|
|
|
NotOp = Op0;
|
|
|
|
else
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (NotOp->getOpcode() == ISD::OR)
|
|
|
|
return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
|
|
|
|
NotOp->getOperand(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2013-03-30 01:42:24 +00:00
|
|
|
SDValue
|
|
|
|
MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
|
|
|
|
SelectionDAG &DAG = DCI.DAG;
|
2013-04-30 22:37:26 +00:00
|
|
|
SDValue Val;
|
2013-03-30 01:42:24 +00:00
|
|
|
|
|
|
|
switch (N->getOpcode()) {
|
|
|
|
case ISD::ADDE:
|
|
|
|
return performADDECombine(N, DAG, DCI, Subtarget);
|
2013-09-23 14:03:12 +00:00
|
|
|
case ISD::AND:
|
|
|
|
Val = performANDCombine(N, DAG, DCI, Subtarget);
|
|
|
|
break;
|
2013-03-30 01:42:24 +00:00
|
|
|
case ISD::SUBE:
|
|
|
|
return performSUBECombine(N, DAG, DCI, Subtarget);
|
2013-06-26 18:48:17 +00:00
|
|
|
case ISD::MUL:
|
|
|
|
return performMULCombine(N, DAG, DCI, this);
|
2013-04-19 23:21:32 +00:00
|
|
|
case ISD::SHL:
|
|
|
|
return performSHLCombine(N, DAG, DCI, Subtarget);
|
|
|
|
case ISD::SRA:
|
|
|
|
return performSRACombine(N, DAG, DCI, Subtarget);
|
|
|
|
case ISD::SRL:
|
|
|
|
return performSRLCombine(N, DAG, DCI, Subtarget);
|
2013-04-30 22:37:26 +00:00
|
|
|
case ISD::VSELECT:
|
|
|
|
return performVSELECTCombine(N, DAG);
|
2013-09-23 13:22:24 +00:00
|
|
|
case ISD::XOR:
|
|
|
|
Val = performXORCombine(N, DAG, Subtarget);
|
|
|
|
break;
|
|
|
|
case ISD::SETCC:
|
2013-04-30 22:37:26 +00:00
|
|
|
Val = performSETCCCombine(N, DAG);
|
|
|
|
break;
|
2013-03-30 01:42:24 +00:00
|
|
|
}
|
2013-04-30 22:37:26 +00:00
|
|
|
|
|
|
|
if (Val.getNode())
|
|
|
|
return Val;
|
|
|
|
|
|
|
|
return MipsTargetLowering::PerformDAGCombine(N, DCI);
|
2013-03-30 01:42:24 +00:00
|
|
|
}
|
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
MachineBasicBlock *
|
|
|
|
MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB) const {
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default:
|
|
|
|
return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
|
|
|
|
case Mips::BPOSGE32_PSEUDO:
|
|
|
|
return emitBPOSGE32(MI, BB);
|
2013-08-28 12:14:50 +00:00
|
|
|
case Mips::SNZ_B_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
|
|
|
|
case Mips::SNZ_H_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
|
|
|
|
case Mips::SNZ_W_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
|
|
|
|
case Mips::SNZ_D_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
|
|
|
|
case Mips::SNZ_V_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
|
|
|
|
case Mips::SZ_B_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
|
|
|
|
case Mips::SZ_H_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
|
|
|
|
case Mips::SZ_W_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
|
|
|
|
case Mips::SZ_D_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
|
|
|
|
case Mips::SZ_V_PSEUDO:
|
|
|
|
return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
|
2013-03-13 00:54:29 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool MipsSETargetLowering::
|
|
|
|
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
|
|
|
|
unsigned NextStackOffset,
|
|
|
|
const MipsFunctionInfo& FI) const {
|
|
|
|
if (!EnableMipsTailCalls)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Return false if either the callee or caller has a byval argument.
|
|
|
|
if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Return true if the callee's argument area is no larger than the
|
|
|
|
// caller's.
|
|
|
|
return NextStackOffset <= FI.getIncomingArgSize();
|
|
|
|
}
|
|
|
|
|
|
|
|
void MipsSETargetLowering::
|
|
|
|
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
|
|
|
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
|
|
|
|
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
|
|
|
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
|
|
|
|
// T9 should contain the address of the callee function if
|
|
|
|
// -reloction-model=pic or it is an indirect call.
|
|
|
|
if (IsPICCall || !GlobalOrExternal) {
|
|
|
|
unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
|
|
|
|
RegsToPass.push_front(std::make_pair(T9Reg, Callee));
|
|
|
|
} else
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
|
|
|
|
MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
|
|
|
|
InternalLinkage, CLI, Callee, Chain);
|
|
|
|
}
|
|
|
|
|
2013-09-07 00:52:30 +00:00
|
|
|
SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
|
|
|
|
LoadSDNode &Nd = *cast<LoadSDNode>(Op);
|
|
|
|
|
|
|
|
if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
|
|
|
|
return MipsTargetLowering::lowerLOAD(Op, DAG);
|
|
|
|
|
|
|
|
// Replace a double precision load with two i32 loads and a buildpair64.
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
|
|
|
|
EVT PtrVT = Ptr.getValueType();
|
|
|
|
|
|
|
|
// i32 load from lower address.
|
|
|
|
SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
|
|
|
|
MachinePointerInfo(), Nd.isVolatile(),
|
|
|
|
Nd.isNonTemporal(), Nd.isInvariant(),
|
|
|
|
Nd.getAlignment());
|
|
|
|
|
|
|
|
// i32 load from higher address.
|
|
|
|
Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
|
|
|
|
SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
|
|
|
|
MachinePointerInfo(), Nd.isVolatile(),
|
|
|
|
Nd.isNonTemporal(), Nd.isInvariant(),
|
2013-09-09 17:59:32 +00:00
|
|
|
std::min(Nd.getAlignment(), 4U));
|
2013-09-07 00:52:30 +00:00
|
|
|
|
|
|
|
if (!Subtarget->isLittle())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
|
|
|
|
SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
|
|
|
|
SDValue Ops[2] = {BP, Hi.getValue(1)};
|
|
|
|
return DAG.getMergeValues(Ops, 2, DL);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
|
|
|
|
StoreSDNode &Nd = *cast<StoreSDNode>(Op);
|
|
|
|
|
|
|
|
if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
|
|
|
|
return MipsTargetLowering::lowerSTORE(Op, DAG);
|
|
|
|
|
|
|
|
// Replace a double precision store with two extractelement64s and i32 stores.
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
|
|
|
|
EVT PtrVT = Ptr.getValueType();
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
|
|
|
|
Val, DAG.getConstant(0, MVT::i32));
|
|
|
|
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
|
|
|
|
Val, DAG.getConstant(1, MVT::i32));
|
|
|
|
|
|
|
|
if (!Subtarget->isLittle())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
|
|
|
|
// i32 store to lower address.
|
|
|
|
Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
|
|
|
|
Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
|
|
|
|
Nd.getTBAAInfo());
|
|
|
|
|
|
|
|
// i32 store to higher address.
|
|
|
|
Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
|
|
|
|
return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
|
2013-09-09 17:59:32 +00:00
|
|
|
Nd.isVolatile(), Nd.isNonTemporal(),
|
|
|
|
std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
|
2013-09-07 00:52:30 +00:00
|
|
|
}
|
|
|
|
|
2013-03-30 01:36:35 +00:00
|
|
|
SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
|
|
|
|
bool HasLo, bool HasHi,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
EVT Ty = Op.getOperand(0).getValueType();
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2013-03-30 01:36:35 +00:00
|
|
|
SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
|
|
|
|
Op.getOperand(0), Op.getOperand(1));
|
|
|
|
SDValue Lo, Hi;
|
|
|
|
|
|
|
|
if (HasLo)
|
|
|
|
Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
|
|
|
|
DAG.getConstant(Mips::sub_lo, MVT::i32));
|
|
|
|
if (HasHi)
|
|
|
|
Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
|
|
|
|
DAG.getConstant(Mips::sub_hi, MVT::i32));
|
|
|
|
|
|
|
|
if (!HasLo || !HasHi)
|
|
|
|
return HasLo ? Lo : Hi;
|
|
|
|
|
|
|
|
SDValue Vals[] = { Lo, Hi };
|
|
|
|
return DAG.getMergeValues(Vals, 2, DL);
|
|
|
|
}
|
|
|
|
|
2013-04-13 02:13:30 +00:00
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
|
2013-04-13 02:13:30 +00:00
|
|
|
SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
|
|
|
|
DAG.getConstant(0, MVT::i32));
|
|
|
|
SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
|
|
|
|
DAG.getConstant(1, MVT::i32));
|
|
|
|
return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
|
|
|
|
}
|
|
|
|
|
2013-05-25 02:42:55 +00:00
|
|
|
static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
|
2013-04-13 02:13:30 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
|
|
|
|
DAG.getConstant(Mips::sub_lo, MVT::i32));
|
|
|
|
SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
|
|
|
|
DAG.getConstant(Mips::sub_hi, MVT::i32));
|
|
|
|
return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
|
|
|
|
}
|
|
|
|
|
|
|
|
// This function expands mips intrinsic nodes which have 64-bit input operands
|
|
|
|
// or output values.
|
|
|
|
//
|
|
|
|
// out64 = intrinsic-node in64
|
|
|
|
// =>
|
|
|
|
// lo = copy (extract-element (in64, 0))
|
|
|
|
// hi = copy (extract-element (in64, 1))
|
|
|
|
// mips-specific-node
|
|
|
|
// v0 = copy lo
|
|
|
|
// v1 = copy hi
|
|
|
|
// out64 = merge-values (v0, v1)
|
|
|
|
//
|
|
|
|
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
2013-05-25 02:42:55 +00:00
|
|
|
SDLoc DL(Op);
|
2013-04-13 02:13:30 +00:00
|
|
|
bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
|
|
|
|
SmallVector<SDValue, 3> Ops;
|
|
|
|
unsigned OpNo = 0;
|
|
|
|
|
|
|
|
// See if Op has a chain input.
|
|
|
|
if (HasChainIn)
|
|
|
|
Ops.push_back(Op->getOperand(OpNo++));
|
|
|
|
|
|
|
|
// The next operand is the intrinsic opcode.
|
|
|
|
assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
|
|
|
|
|
|
|
|
// See if the next operand has type i64.
|
|
|
|
SDValue Opnd = Op->getOperand(++OpNo), In64;
|
|
|
|
|
|
|
|
if (Opnd.getValueType() == MVT::i64)
|
|
|
|
In64 = initAccumulator(Opnd, DL, DAG);
|
|
|
|
else
|
|
|
|
Ops.push_back(Opnd);
|
|
|
|
|
|
|
|
// Push the remaining operands.
|
|
|
|
for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
|
|
|
|
Ops.push_back(Op->getOperand(OpNo));
|
|
|
|
|
|
|
|
// Add In64 to the end of the list.
|
|
|
|
if (In64.getNode())
|
|
|
|
Ops.push_back(In64);
|
|
|
|
|
|
|
|
// Scan output.
|
|
|
|
SmallVector<EVT, 2> ResTys;
|
|
|
|
|
|
|
|
for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
|
|
|
|
I != E; ++I)
|
|
|
|
ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
|
|
|
|
|
|
|
|
// Create node.
|
|
|
|
SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
|
|
|
|
SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
|
|
|
|
|
|
|
|
if (!HasChainIn)
|
|
|
|
return Out;
|
|
|
|
|
|
|
|
assert(Val->getValueType(1) == MVT::Other);
|
|
|
|
SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
|
|
|
|
return DAG.getMergeValues(Vals, 2, DL);
|
|
|
|
}
|
|
|
|
|
2013-09-11 10:28:16 +00:00
|
|
|
static SDValue lowerMSABinaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue LHS = Op->getOperand(1);
|
|
|
|
SDValue RHS = Op->getOperand(2);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
|
|
|
|
SDValue Result = DAG.getNode(Opc, DL, ResTy, LHS, RHS);
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
2013-09-23 14:29:55 +00:00
|
|
|
static SDValue lowerMSABinaryImmIntr(SDValue Op, SelectionDAG &DAG,
|
|
|
|
unsigned Opc, SDValue RHS) {
|
|
|
|
SDValue LHS = Op->getOperand(1);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
|
|
|
|
return DAG.getNode(Opc, SDLoc(Op), ResTy, LHS, RHS);
|
|
|
|
}
|
|
|
|
|
2013-08-28 12:14:50 +00:00
|
|
|
static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Value = Op->getOperand(1);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
|
|
|
|
SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
2013-09-23 14:03:12 +00:00
|
|
|
// Lower an MSA copy intrinsic into the specified SelectionDAG node
|
|
|
|
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Vec = Op->getOperand(1);
|
|
|
|
SDValue Idx = Op->getOperand(2);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
EVT EltTy = Vec->getValueType(0).getVectorElementType();
|
|
|
|
|
|
|
|
SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
|
|
|
|
DAG.getValueType(EltTy));
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Lower an MSA insert intrinsic into the specified SelectionDAG node
|
|
|
|
static SDValue lowerMSAInsertIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Op0 = Op->getOperand(1);
|
|
|
|
SDValue Op1 = Op->getOperand(2);
|
|
|
|
SDValue Op2 = Op->getOperand(3);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
|
|
|
|
SDValue Result = DAG.getNode(Opc, DL, ResTy, Op0, Op2, Op1);
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
2013-09-23 14:29:55 +00:00
|
|
|
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
|
|
|
|
unsigned SplatOp = MipsISD::VSPLAT;
|
|
|
|
if (ResTy == MVT::v2i64)
|
|
|
|
SplatOp = MipsISD::VSPLATD;
|
|
|
|
|
|
|
|
return DAG.getNode(SplatOp, SDLoc(Op), ResTy, Op->getOperand(ImmOp));
|
|
|
|
}
|
|
|
|
|
2013-09-11 10:51:30 +00:00
|
|
|
static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue Value = Op->getOperand(1);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
|
|
|
|
SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
2013-04-13 02:13:30 +00:00
|
|
|
SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
|
|
|
|
default:
|
|
|
|
return SDValue();
|
|
|
|
case Intrinsic::mips_shilo:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
|
|
|
|
case Intrinsic::mips_dpau_h_qbl:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
|
|
|
|
case Intrinsic::mips_dpau_h_qbr:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
|
|
|
|
case Intrinsic::mips_dpsu_h_qbl:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
|
|
|
|
case Intrinsic::mips_dpsu_h_qbr:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
|
|
|
|
case Intrinsic::mips_dpa_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
|
|
|
|
case Intrinsic::mips_dps_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
|
|
|
|
case Intrinsic::mips_dpax_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
|
|
|
|
case Intrinsic::mips_dpsx_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
|
|
|
|
case Intrinsic::mips_mulsa_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
|
|
|
|
case Intrinsic::mips_mult:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::Mult);
|
|
|
|
case Intrinsic::mips_multu:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::Multu);
|
|
|
|
case Intrinsic::mips_madd:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
|
|
|
|
case Intrinsic::mips_maddu:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
|
|
|
|
case Intrinsic::mips_msub:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MSub);
|
|
|
|
case Intrinsic::mips_msubu:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
|
2013-09-11 10:28:16 +00:00
|
|
|
case Intrinsic::mips_addv_b:
|
|
|
|
case Intrinsic::mips_addv_h:
|
|
|
|
case Intrinsic::mips_addv_w:
|
|
|
|
case Intrinsic::mips_addv_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
|
2013-09-23 14:29:55 +00:00
|
|
|
case Intrinsic::mips_addvi_b:
|
|
|
|
case Intrinsic::mips_addvi_h:
|
|
|
|
case Intrinsic::mips_addvi_w:
|
|
|
|
case Intrinsic::mips_addvi_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::ADD,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-09-23 12:57:42 +00:00
|
|
|
case Intrinsic::mips_and_v:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::AND);
|
2013-09-24 12:32:47 +00:00
|
|
|
case Intrinsic::mips_andi_b:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::AND,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-08-28 12:14:50 +00:00
|
|
|
case Intrinsic::mips_bnz_b:
|
|
|
|
case Intrinsic::mips_bnz_h:
|
|
|
|
case Intrinsic::mips_bnz_w:
|
|
|
|
case Intrinsic::mips_bnz_d:
|
|
|
|
return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
|
|
|
|
case Intrinsic::mips_bnz_v:
|
|
|
|
return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
|
2013-09-24 12:04:44 +00:00
|
|
|
case Intrinsic::mips_bsel_v:
|
|
|
|
return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
|
|
|
|
Op->getOperand(1), Op->getOperand(2),
|
|
|
|
Op->getOperand(3));
|
|
|
|
case Intrinsic::mips_bseli_b:
|
|
|
|
return DAG.getNode(ISD::VSELECT, SDLoc(Op), Op->getValueType(0),
|
|
|
|
Op->getOperand(1), Op->getOperand(2),
|
|
|
|
lowerMSASplatImm(Op, 3, DAG));
|
2013-08-28 12:14:50 +00:00
|
|
|
case Intrinsic::mips_bz_b:
|
|
|
|
case Intrinsic::mips_bz_h:
|
|
|
|
case Intrinsic::mips_bz_w:
|
|
|
|
case Intrinsic::mips_bz_d:
|
|
|
|
return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
|
|
|
|
case Intrinsic::mips_bz_v:
|
|
|
|
return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
|
2013-09-24 10:46:19 +00:00
|
|
|
case Intrinsic::mips_ceq_b:
|
|
|
|
case Intrinsic::mips_ceq_h:
|
|
|
|
case Intrinsic::mips_ceq_w:
|
|
|
|
case Intrinsic::mips_ceq_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETEQ);
|
|
|
|
case Intrinsic::mips_ceqi_b:
|
|
|
|
case Intrinsic::mips_ceqi_h:
|
|
|
|
case Intrinsic::mips_ceqi_w:
|
|
|
|
case Intrinsic::mips_ceqi_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
|
|
|
|
case Intrinsic::mips_cle_s_b:
|
|
|
|
case Intrinsic::mips_cle_s_h:
|
|
|
|
case Intrinsic::mips_cle_s_w:
|
|
|
|
case Intrinsic::mips_cle_s_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETLE);
|
|
|
|
case Intrinsic::mips_clei_s_b:
|
|
|
|
case Intrinsic::mips_clei_s_h:
|
|
|
|
case Intrinsic::mips_clei_s_w:
|
|
|
|
case Intrinsic::mips_clei_s_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
|
|
|
|
case Intrinsic::mips_cle_u_b:
|
|
|
|
case Intrinsic::mips_cle_u_h:
|
|
|
|
case Intrinsic::mips_cle_u_w:
|
|
|
|
case Intrinsic::mips_cle_u_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETULE);
|
|
|
|
case Intrinsic::mips_clei_u_b:
|
|
|
|
case Intrinsic::mips_clei_u_h:
|
|
|
|
case Intrinsic::mips_clei_u_w:
|
|
|
|
case Intrinsic::mips_clei_u_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
|
|
|
|
case Intrinsic::mips_clt_s_b:
|
|
|
|
case Intrinsic::mips_clt_s_h:
|
|
|
|
case Intrinsic::mips_clt_s_w:
|
|
|
|
case Intrinsic::mips_clt_s_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETLT);
|
|
|
|
case Intrinsic::mips_clti_s_b:
|
|
|
|
case Intrinsic::mips_clti_s_h:
|
|
|
|
case Intrinsic::mips_clti_s_w:
|
|
|
|
case Intrinsic::mips_clti_s_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
|
|
|
|
case Intrinsic::mips_clt_u_b:
|
|
|
|
case Intrinsic::mips_clt_u_h:
|
|
|
|
case Intrinsic::mips_clt_u_w:
|
|
|
|
case Intrinsic::mips_clt_u_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETULT);
|
|
|
|
case Intrinsic::mips_clti_u_b:
|
|
|
|
case Intrinsic::mips_clti_u_h:
|
|
|
|
case Intrinsic::mips_clti_u_w:
|
|
|
|
case Intrinsic::mips_clti_u_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
|
2013-09-23 14:03:12 +00:00
|
|
|
case Intrinsic::mips_copy_s_b:
|
|
|
|
case Intrinsic::mips_copy_s_h:
|
|
|
|
case Intrinsic::mips_copy_s_w:
|
|
|
|
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
|
|
|
|
case Intrinsic::mips_copy_u_b:
|
|
|
|
case Intrinsic::mips_copy_u_h:
|
|
|
|
case Intrinsic::mips_copy_u_w:
|
|
|
|
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
|
2013-09-11 10:38:58 +00:00
|
|
|
case Intrinsic::mips_div_s_b:
|
|
|
|
case Intrinsic::mips_div_s_h:
|
|
|
|
case Intrinsic::mips_div_s_w:
|
|
|
|
case Intrinsic::mips_div_s_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
|
|
|
|
case Intrinsic::mips_div_u_b:
|
|
|
|
case Intrinsic::mips_div_u_h:
|
|
|
|
case Intrinsic::mips_div_u_w:
|
|
|
|
case Intrinsic::mips_div_u_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
|
2013-09-11 10:51:30 +00:00
|
|
|
case Intrinsic::mips_fadd_w:
|
|
|
|
case Intrinsic::mips_fadd_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::FADD);
|
2013-09-24 10:46:19 +00:00
|
|
|
// Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
|
|
|
|
case Intrinsic::mips_fceq_w:
|
|
|
|
case Intrinsic::mips_fceq_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETOEQ);
|
|
|
|
case Intrinsic::mips_fcle_w:
|
|
|
|
case Intrinsic::mips_fcle_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETOLE);
|
|
|
|
case Intrinsic::mips_fclt_w:
|
|
|
|
case Intrinsic::mips_fclt_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETOLT);
|
|
|
|
case Intrinsic::mips_fcne_w:
|
|
|
|
case Intrinsic::mips_fcne_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETONE);
|
|
|
|
case Intrinsic::mips_fcor_w:
|
|
|
|
case Intrinsic::mips_fcor_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETO);
|
|
|
|
case Intrinsic::mips_fcueq_w:
|
|
|
|
case Intrinsic::mips_fcueq_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETUEQ);
|
|
|
|
case Intrinsic::mips_fcule_w:
|
|
|
|
case Intrinsic::mips_fcule_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETULE);
|
|
|
|
case Intrinsic::mips_fcult_w:
|
|
|
|
case Intrinsic::mips_fcult_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETULT);
|
|
|
|
case Intrinsic::mips_fcun_w:
|
|
|
|
case Intrinsic::mips_fcun_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETUO);
|
|
|
|
case Intrinsic::mips_fcune_w:
|
|
|
|
case Intrinsic::mips_fcune_d:
|
|
|
|
return DAG.getSetCC(SDLoc(Op), Op->getValueType(0), Op->getOperand(1),
|
|
|
|
Op->getOperand(2), ISD::SETUNE);
|
2013-09-11 10:51:30 +00:00
|
|
|
case Intrinsic::mips_fdiv_w:
|
|
|
|
case Intrinsic::mips_fdiv_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::FDIV);
|
2013-09-23 12:02:46 +00:00
|
|
|
case Intrinsic::mips_fill_b:
|
|
|
|
case Intrinsic::mips_fill_h:
|
|
|
|
case Intrinsic::mips_fill_w:
|
|
|
|
return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
|
2013-09-11 10:51:30 +00:00
|
|
|
case Intrinsic::mips_flog2_w:
|
|
|
|
case Intrinsic::mips_flog2_d:
|
|
|
|
return lowerMSAUnaryIntr(Op, DAG, ISD::FLOG2);
|
|
|
|
case Intrinsic::mips_fmul_w:
|
|
|
|
case Intrinsic::mips_fmul_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::FMUL);
|
|
|
|
case Intrinsic::mips_frint_w:
|
|
|
|
case Intrinsic::mips_frint_d:
|
|
|
|
return lowerMSAUnaryIntr(Op, DAG, ISD::FRINT);
|
|
|
|
case Intrinsic::mips_fsqrt_w:
|
|
|
|
case Intrinsic::mips_fsqrt_d:
|
|
|
|
return lowerMSAUnaryIntr(Op, DAG, ISD::FSQRT);
|
|
|
|
case Intrinsic::mips_fsub_w:
|
|
|
|
case Intrinsic::mips_fsub_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::FSUB);
|
2013-09-23 14:03:12 +00:00
|
|
|
case Intrinsic::mips_insert_b:
|
|
|
|
case Intrinsic::mips_insert_h:
|
|
|
|
case Intrinsic::mips_insert_w:
|
|
|
|
return lowerMSAInsertIntr(Op, DAG, ISD::INSERT_VECTOR_ELT);
|
2013-09-23 12:02:46 +00:00
|
|
|
case Intrinsic::mips_ldi_b:
|
|
|
|
case Intrinsic::mips_ldi_h:
|
|
|
|
case Intrinsic::mips_ldi_w:
|
|
|
|
case Intrinsic::mips_ldi_d:
|
|
|
|
return lowerMSAUnaryIntr(Op, DAG, MipsISD::VSPLAT);
|
2013-09-24 12:18:31 +00:00
|
|
|
case Intrinsic::mips_max_s_b:
|
|
|
|
case Intrinsic::mips_max_s_h:
|
|
|
|
case Intrinsic::mips_max_s_w:
|
|
|
|
case Intrinsic::mips_max_s_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, MipsISD::VSMAX);
|
|
|
|
case Intrinsic::mips_max_u_b:
|
|
|
|
case Intrinsic::mips_max_u_h:
|
|
|
|
case Intrinsic::mips_max_u_w:
|
|
|
|
case Intrinsic::mips_max_u_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, MipsISD::VUMAX);
|
|
|
|
case Intrinsic::mips_maxi_s_b:
|
|
|
|
case Intrinsic::mips_maxi_s_h:
|
|
|
|
case Intrinsic::mips_maxi_s_w:
|
|
|
|
case Intrinsic::mips_maxi_s_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VSMAX,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
|
|
|
case Intrinsic::mips_maxi_u_b:
|
|
|
|
case Intrinsic::mips_maxi_u_h:
|
|
|
|
case Intrinsic::mips_maxi_u_w:
|
|
|
|
case Intrinsic::mips_maxi_u_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VUMAX,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
|
|
|
case Intrinsic::mips_min_s_b:
|
|
|
|
case Intrinsic::mips_min_s_h:
|
|
|
|
case Intrinsic::mips_min_s_w:
|
|
|
|
case Intrinsic::mips_min_s_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, MipsISD::VSMIN);
|
|
|
|
case Intrinsic::mips_min_u_b:
|
|
|
|
case Intrinsic::mips_min_u_h:
|
|
|
|
case Intrinsic::mips_min_u_w:
|
|
|
|
case Intrinsic::mips_min_u_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, MipsISD::VUMIN);
|
|
|
|
case Intrinsic::mips_mini_s_b:
|
|
|
|
case Intrinsic::mips_mini_s_h:
|
|
|
|
case Intrinsic::mips_mini_s_w:
|
|
|
|
case Intrinsic::mips_mini_s_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VSMIN,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
|
|
|
case Intrinsic::mips_mini_u_b:
|
|
|
|
case Intrinsic::mips_mini_u_h:
|
|
|
|
case Intrinsic::mips_mini_u_w:
|
|
|
|
case Intrinsic::mips_mini_u_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, MipsISD::VUMIN,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-09-11 11:58:30 +00:00
|
|
|
case Intrinsic::mips_mulv_b:
|
|
|
|
case Intrinsic::mips_mulv_h:
|
|
|
|
case Intrinsic::mips_mulv_w:
|
|
|
|
case Intrinsic::mips_mulv_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::MUL);
|
|
|
|
case Intrinsic::mips_nlzc_b:
|
|
|
|
case Intrinsic::mips_nlzc_h:
|
|
|
|
case Intrinsic::mips_nlzc_w:
|
|
|
|
case Intrinsic::mips_nlzc_d:
|
|
|
|
return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ);
|
2013-09-23 13:22:24 +00:00
|
|
|
case Intrinsic::mips_nor_v: {
|
|
|
|
SDValue Res = lowerMSABinaryIntr(Op, DAG, ISD::OR);
|
|
|
|
return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
|
|
|
|
}
|
2013-09-24 12:32:47 +00:00
|
|
|
case Intrinsic::mips_nori_b: {
|
|
|
|
SDValue Res = lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
|
|
|
return DAG.getNOT(SDLoc(Op), Res, Res->getValueType(0));
|
|
|
|
}
|
2013-09-23 12:57:42 +00:00
|
|
|
case Intrinsic::mips_or_v:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::OR);
|
2013-09-24 12:32:47 +00:00
|
|
|
case Intrinsic::mips_ori_b:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-09-23 13:40:21 +00:00
|
|
|
case Intrinsic::mips_pcnt_b:
|
|
|
|
case Intrinsic::mips_pcnt_h:
|
|
|
|
case Intrinsic::mips_pcnt_w:
|
|
|
|
case Intrinsic::mips_pcnt_d:
|
|
|
|
return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
|
2013-09-11 11:58:30 +00:00
|
|
|
case Intrinsic::mips_sll_b:
|
|
|
|
case Intrinsic::mips_sll_h:
|
|
|
|
case Intrinsic::mips_sll_w:
|
|
|
|
case Intrinsic::mips_sll_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::SHL);
|
2013-09-24 10:28:18 +00:00
|
|
|
case Intrinsic::mips_slli_b:
|
|
|
|
case Intrinsic::mips_slli_h:
|
|
|
|
case Intrinsic::mips_slli_w:
|
|
|
|
case Intrinsic::mips_slli_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::SHL,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-09-11 11:58:30 +00:00
|
|
|
case Intrinsic::mips_sra_b:
|
|
|
|
case Intrinsic::mips_sra_h:
|
|
|
|
case Intrinsic::mips_sra_w:
|
|
|
|
case Intrinsic::mips_sra_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::SRA);
|
2013-09-24 10:28:18 +00:00
|
|
|
case Intrinsic::mips_srai_b:
|
|
|
|
case Intrinsic::mips_srai_h:
|
|
|
|
case Intrinsic::mips_srai_w:
|
|
|
|
case Intrinsic::mips_srai_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::SRA,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-09-11 11:58:30 +00:00
|
|
|
case Intrinsic::mips_srl_b:
|
|
|
|
case Intrinsic::mips_srl_h:
|
|
|
|
case Intrinsic::mips_srl_w:
|
|
|
|
case Intrinsic::mips_srl_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::SRL);
|
2013-09-24 10:28:18 +00:00
|
|
|
case Intrinsic::mips_srli_b:
|
|
|
|
case Intrinsic::mips_srli_h:
|
|
|
|
case Intrinsic::mips_srli_w:
|
|
|
|
case Intrinsic::mips_srli_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::SRL,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-09-11 11:58:30 +00:00
|
|
|
case Intrinsic::mips_subv_b:
|
|
|
|
case Intrinsic::mips_subv_h:
|
|
|
|
case Intrinsic::mips_subv_w:
|
|
|
|
case Intrinsic::mips_subv_d:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
|
2013-09-23 14:29:55 +00:00
|
|
|
case Intrinsic::mips_subvi_b:
|
|
|
|
case Intrinsic::mips_subvi_h:
|
|
|
|
case Intrinsic::mips_subvi_w:
|
|
|
|
case Intrinsic::mips_subvi_d:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::SUB,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-09-23 12:57:42 +00:00
|
|
|
case Intrinsic::mips_xor_v:
|
|
|
|
return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
|
2013-09-24 12:32:47 +00:00
|
|
|
case Intrinsic::mips_xori_b:
|
|
|
|
return lowerMSABinaryImmIntr(Op, DAG, ISD::XOR,
|
|
|
|
lowerMSASplatImm(Op, 2, DAG));
|
2013-04-13 02:13:30 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-08-28 12:04:29 +00:00
|
|
|
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue ChainIn = Op->getOperand(0);
|
|
|
|
SDValue Address = Op->getOperand(2);
|
|
|
|
SDValue Offset = Op->getOperand(3);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
EVT PtrTy = Address->getValueType(0);
|
|
|
|
|
|
|
|
Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
|
|
|
|
|
|
|
|
return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
|
|
|
|
false, false, 16);
|
|
|
|
}
|
|
|
|
|
2013-04-13 02:13:30 +00:00
|
|
|
SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
2013-08-28 12:04:29 +00:00
|
|
|
unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
|
|
|
|
switch (Intr) {
|
2013-04-13 02:13:30 +00:00
|
|
|
default:
|
|
|
|
return SDValue();
|
|
|
|
case Intrinsic::mips_extp:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
|
|
|
|
case Intrinsic::mips_extpdp:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
|
|
|
|
case Intrinsic::mips_extr_w:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
|
|
|
|
case Intrinsic::mips_extr_r_w:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
|
|
|
|
case Intrinsic::mips_extr_rs_w:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
|
|
|
|
case Intrinsic::mips_extr_s_h:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
|
|
|
|
case Intrinsic::mips_mthlip:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
|
|
|
|
case Intrinsic::mips_mulsaq_s_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
|
|
|
|
case Intrinsic::mips_maq_s_w_phl:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
|
|
|
|
case Intrinsic::mips_maq_s_w_phr:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
|
|
|
|
case Intrinsic::mips_maq_sa_w_phl:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
|
|
|
|
case Intrinsic::mips_maq_sa_w_phr:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
|
|
|
|
case Intrinsic::mips_dpaq_s_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
|
|
|
|
case Intrinsic::mips_dpsq_s_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
|
|
|
|
case Intrinsic::mips_dpaq_sa_l_w:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
|
|
|
|
case Intrinsic::mips_dpsq_sa_l_w:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
|
|
|
|
case Intrinsic::mips_dpaqx_s_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
|
|
|
|
case Intrinsic::mips_dpaqx_sa_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
|
|
|
|
case Intrinsic::mips_dpsqx_s_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
|
|
|
|
case Intrinsic::mips_dpsqx_sa_w_ph:
|
|
|
|
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
|
2013-08-28 12:04:29 +00:00
|
|
|
case Intrinsic::mips_ld_b:
|
|
|
|
case Intrinsic::mips_ld_h:
|
|
|
|
case Intrinsic::mips_ld_w:
|
|
|
|
case Intrinsic::mips_ld_d:
|
|
|
|
case Intrinsic::mips_ldx_b:
|
|
|
|
case Intrinsic::mips_ldx_h:
|
|
|
|
case Intrinsic::mips_ldx_w:
|
|
|
|
case Intrinsic::mips_ldx_d:
|
|
|
|
return lowerMSALoadIntr(Op, DAG, Intr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
SDValue ChainIn = Op->getOperand(0);
|
|
|
|
SDValue Value = Op->getOperand(2);
|
|
|
|
SDValue Address = Op->getOperand(3);
|
|
|
|
SDValue Offset = Op->getOperand(4);
|
|
|
|
EVT PtrTy = Address->getValueType(0);
|
|
|
|
|
|
|
|
Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
|
|
|
|
|
|
|
|
return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
|
|
|
|
false, 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
|
|
|
|
switch (Intr) {
|
|
|
|
default:
|
|
|
|
return SDValue();
|
|
|
|
case Intrinsic::mips_st_b:
|
|
|
|
case Intrinsic::mips_st_h:
|
|
|
|
case Intrinsic::mips_st_w:
|
|
|
|
case Intrinsic::mips_st_d:
|
|
|
|
case Intrinsic::mips_stx_b:
|
|
|
|
case Intrinsic::mips_stx_h:
|
|
|
|
case Intrinsic::mips_stx_w:
|
|
|
|
case Intrinsic::mips_stx_d:
|
2013-08-28 12:14:50 +00:00
|
|
|
return lowerMSAStoreIntr(Op, DAG, Intr);
|
2013-04-13 02:13:30 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-09-23 12:02:46 +00:00
|
|
|
/// \brief Check if the given BuildVectorSDNode is a splat.
|
|
|
|
/// This method currently relies on DAG nodes being reused when equivalent,
|
|
|
|
/// so it's possible for this to return false even when isConstantSplat returns
|
|
|
|
/// true.
|
|
|
|
static bool isSplatVector(const BuildVectorSDNode *N) {
|
|
|
|
unsigned int nOps = N->getNumOperands();
|
|
|
|
assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
|
|
|
|
|
|
|
|
SDValue Operand0 = N->getOperand(0);
|
|
|
|
|
|
|
|
for (unsigned int i = 1; i < nOps; ++i) {
|
|
|
|
if (N->getOperand(i) != Operand0)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-09-23 14:03:12 +00:00
|
|
|
// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
|
|
|
|
//
|
|
|
|
// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
|
|
|
|
// choose to sign-extend but we could have equally chosen zero-extend. The
|
|
|
|
// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
|
|
|
|
// result into this node later (possibly changing it to a zero-extend in the
|
|
|
|
// process).
|
|
|
|
SDValue MipsSETargetLowering::
|
|
|
|
lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
|
|
|
|
SDLoc DL(Op);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
SDValue Op0 = Op->getOperand(0);
|
|
|
|
SDValue Op1 = Op->getOperand(1);
|
|
|
|
EVT EltTy = Op0->getValueType(0).getVectorElementType();
|
|
|
|
return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
|
|
|
|
DAG.getValueType(EltTy));
|
|
|
|
}
|
|
|
|
|
2013-09-23 12:02:46 +00:00
|
|
|
// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
|
|
|
|
// backend.
|
|
|
|
//
|
|
|
|
// Lowers according to the following rules:
|
|
|
|
// - Vectors of 128-bits may be legal subject to the other rules. Other sizes
|
|
|
|
// are not legal.
|
|
|
|
// - Non-constant splats are legal and are lowered to MipsISD::VSPLAT.
|
|
|
|
// - Constant splats with an element size of 32-bits or less are legal and are
|
|
|
|
// lowered to MipsISD::VSPLAT.
|
|
|
|
// - Constant splats with an element size of 64-bits but whose value would fit
|
|
|
|
// within a 10 bit immediate are legal and are lowered to MipsISD::VSPLATD.
|
|
|
|
// - All other ISD::BUILD_VECTORS are not legal
|
|
|
|
SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
|
|
|
BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
|
|
|
|
EVT ResTy = Op->getValueType(0);
|
|
|
|
SDLoc DL(Op);
|
|
|
|
APInt SplatValue, SplatUndef;
|
|
|
|
unsigned SplatBitSize;
|
|
|
|
bool HasAnyUndefs;
|
|
|
|
|
|
|
|
if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
|
|
|
|
HasAnyUndefs, 8,
|
|
|
|
!Subtarget->isLittle())) {
|
|
|
|
SDValue Result;
|
|
|
|
EVT TmpVecTy;
|
|
|
|
EVT ConstTy = MVT::i32;
|
|
|
|
unsigned SplatOp = MipsISD::VSPLAT;
|
|
|
|
|
|
|
|
switch (SplatBitSize) {
|
|
|
|
default:
|
|
|
|
return SDValue();
|
|
|
|
case 64:
|
|
|
|
TmpVecTy = MVT::v2i64;
|
|
|
|
|
|
|
|
// i64 is an illegal type on Mips32, but if it the constant fits into a
|
|
|
|
// signed 10-bit value then we can still handle it using VSPLATD and an
|
|
|
|
// i32 constant
|
|
|
|
if (HasMips64)
|
|
|
|
ConstTy = MVT::i64;
|
|
|
|
else if (isInt<10>(SplatValue.getSExtValue())) {
|
|
|
|
SplatValue = SplatValue.trunc(32);
|
|
|
|
SplatOp = MipsISD::VSPLATD;
|
|
|
|
} else
|
|
|
|
return SDValue();
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
TmpVecTy = MVT::v4i32;
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
TmpVecTy = MVT::v8i16;
|
|
|
|
SplatValue = SplatValue.sext(32);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
TmpVecTy = MVT::v16i8;
|
|
|
|
SplatValue = SplatValue.sext(32);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
Result = DAG.getNode(SplatOp, DL, TmpVecTy,
|
|
|
|
DAG.getConstant(SplatValue, ConstTy));
|
|
|
|
if (ResTy != Result.getValueType())
|
|
|
|
Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
|
|
|
|
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
else if (isSplatVector(Node))
|
|
|
|
return DAG.getNode(MipsISD::VSPLAT, DL, ResTy, Op->getOperand(0));
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2013-03-13 00:54:29 +00:00
|
|
|
MachineBasicBlock * MipsSETargetLowering::
|
|
|
|
emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
|
|
|
|
// $bb:
|
|
|
|
// bposge32_pseudo $vr0
|
|
|
|
// =>
|
|
|
|
// $bb:
|
|
|
|
// bposge32 $tbb
|
|
|
|
// $fbb:
|
|
|
|
// li $vr2, 0
|
|
|
|
// b $sink
|
|
|
|
// $tbb:
|
|
|
|
// li $vr1, 1
|
|
|
|
// $sink:
|
|
|
|
// $vr0 = phi($vr2, $fbb, $vr1, $tbb)
|
|
|
|
|
|
|
|
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
|
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
2013-08-06 23:08:38 +00:00
|
|
|
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
|
2013-03-13 00:54:29 +00:00
|
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
|
|
|
|
MachineFunction *F = BB->getParent();
|
|
|
|
MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
F->insert(It, FBB);
|
|
|
|
F->insert(It, TBB);
|
|
|
|
F->insert(It, Sink);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to Sink.
|
|
|
|
Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
Sink->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
|
|
|
// Add successors.
|
|
|
|
BB->addSuccessor(FBB);
|
|
|
|
BB->addSuccessor(TBB);
|
|
|
|
FBB->addSuccessor(Sink);
|
|
|
|
TBB->addSuccessor(Sink);
|
|
|
|
|
|
|
|
// Insert the real bposge32 instruction to $BB.
|
|
|
|
BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
|
|
|
|
|
|
|
|
// Fill $FBB.
|
|
|
|
unsigned VR2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
|
|
|
|
.addReg(Mips::ZERO).addImm(0);
|
|
|
|
BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
|
|
|
|
|
|
|
|
// Fill $TBB.
|
|
|
|
unsigned VR1 = RegInfo.createVirtualRegister(RC);
|
|
|
|
BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
|
|
|
|
.addReg(Mips::ZERO).addImm(1);
|
|
|
|
|
|
|
|
// Insert phi function to $Sink.
|
|
|
|
BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
|
|
|
|
MI->getOperand(0).getReg())
|
|
|
|
.addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
|
|
|
|
|
|
|
|
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
|
|
|
return Sink;
|
|
|
|
}
|
2013-08-28 12:14:50 +00:00
|
|
|
|
|
|
|
MachineBasicBlock * MipsSETargetLowering::
|
|
|
|
emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
|
|
|
|
unsigned BranchOp) const{
|
|
|
|
// $bb:
|
|
|
|
// vany_nonzero $rd, $ws
|
|
|
|
// =>
|
|
|
|
// $bb:
|
|
|
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// bnz.b $ws, $tbb
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// b $fbb
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// $fbb:
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// li $rd1, 0
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// b $sink
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// $tbb:
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// li $rd2, 1
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// $sink:
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// $rd = phi($rd1, $fbb, $rd2, $tbb)
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const TargetRegisterClass *RC = &Mips::GPR32RegClass;
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DebugLoc DL = MI->getDebugLoc();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, FBB);
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F->insert(It, TBB);
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F->insert(It, Sink);
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// Transfer the remainder of BB and its successor edges to Sink.
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Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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Sink->transferSuccessorsAndUpdatePHIs(BB);
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// Add successors.
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BB->addSuccessor(FBB);
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BB->addSuccessor(TBB);
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FBB->addSuccessor(Sink);
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TBB->addSuccessor(Sink);
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// Insert the real bnz.b instruction to $BB.
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BuildMI(BB, DL, TII->get(BranchOp))
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.addReg(MI->getOperand(1).getReg())
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.addMBB(TBB);
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// Fill $FBB.
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unsigned RD1 = RegInfo.createVirtualRegister(RC);
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BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
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.addReg(Mips::ZERO).addImm(0);
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BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
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// Fill $TBB.
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unsigned RD2 = RegInfo.createVirtualRegister(RC);
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BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
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.addReg(Mips::ZERO).addImm(1);
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// Insert phi function to $Sink.
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BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
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MI->getOperand(0).getReg())
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.addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return Sink;
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}
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