2007-12-08 20:16:06 +00:00
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//===-- LegalizeTypes.h - Definition of the DAG Type Legalizer class ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-12-08 20:16:06 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the DAGTypeLegalizer class. This is a private interface
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// shared between the code that implements the SelectionDAG::LegalizeTypes
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// method.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SELECTIONDAG_LEGALIZETYPES_H
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#define SELECTIONDAG_LEGALIZETYPES_H
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#define DEBUG_TYPE "legalize-types"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/ADT/DenseMap.h"
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2008-12-18 20:03:17 +00:00
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#include "llvm/ADT/DenseSet.h"
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2007-12-08 20:16:06 +00:00
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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namespace llvm {
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//===----------------------------------------------------------------------===//
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2008-07-10 15:25:04 +00:00
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/// DAGTypeLegalizer - This takes an arbitrary SelectionDAG as input and hacks
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/// on it until only value types the target machine can handle are left. This
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/// involves promoting small sizes to large sizes or splitting up large values
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/// into small values.
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2007-12-08 20:16:06 +00:00
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///
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class VISIBILITY_HIDDEN DAGTypeLegalizer {
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TargetLowering &TLI;
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SelectionDAG &DAG;
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2008-02-03 07:13:32 +00:00
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public:
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2008-10-29 17:52:12 +00:00
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// NodeIdFlags - This pass uses the NodeId on the SDNodes to hold information
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2007-12-08 20:16:06 +00:00
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// about the state of the node. The enum has all the values.
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2008-10-29 17:52:12 +00:00
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enum NodeIdFlags {
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2007-12-08 20:16:06 +00:00
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/// ReadyToProcess - All operands have been processed, so this node is ready
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/// to be handled.
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ReadyToProcess = 0,
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2008-06-17 14:27:01 +00:00
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2008-12-09 21:33:20 +00:00
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/// NewNode - This is a new node, not before seen, that was created in the
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/// process of legalizing some other node.
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2007-12-08 20:16:06 +00:00
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NewNode = -1,
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2008-06-17 14:27:01 +00:00
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2008-12-09 21:33:20 +00:00
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/// Unanalyzed - This node's ID needs to be set to the number of its
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/// unprocessed operands.
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Unanalyzed = -2,
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2007-12-08 20:16:06 +00:00
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/// Processed - This is a node that has already been processed.
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2008-12-09 21:33:20 +00:00
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Processed = -3
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2008-06-17 14:27:01 +00:00
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2008-12-09 21:33:20 +00:00
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// 1+ - This is a node which has this many unprocessed operands.
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2007-12-08 20:16:06 +00:00
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};
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2008-02-03 07:13:32 +00:00
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private:
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2007-12-08 20:16:06 +00:00
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enum LegalizeAction {
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2008-07-10 15:25:04 +00:00
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Legal, // The target natively supports this type.
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PromoteInteger, // Replace this integer type with a larger one.
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ExpandInteger, // Split this integer type into two of half the size.
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SoftenFloat, // Convert this float type to a same size integer type.
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ExpandFloat, // Split this float type into two of half the size.
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ScalarizeVector, // Replace this one-element vector with its element type.
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2008-12-18 20:03:17 +00:00
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SplitVector, // This vector type should be split into smaller vectors.
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2009-01-13 14:42:39 +00:00
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WidenVector // This vector type should be widened into a larger vector.
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2007-12-08 20:16:06 +00:00
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};
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LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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2007-12-08 20:16:06 +00:00
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/// ValueTypeActions - This is a bitvector that contains two bits for each
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/// simple value type, where the two bits correspond to the LegalizeAction
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LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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/// enum from TargetLowering. This can be queried with "getTypeAction(VT)".
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2007-12-08 20:16:06 +00:00
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TargetLowering::ValueTypeActionImpl ValueTypeActions;
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2008-06-17 14:27:01 +00:00
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2009-01-13 14:42:39 +00:00
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/// getTypeAction - Return how we should legalize values of this type.
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2008-06-06 12:08:01 +00:00
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LegalizeAction getTypeAction(MVT VT) const {
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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switch (ValueTypeActions.getTypeAction(VT)) {
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default:
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assert(false && "Unknown legalize action!");
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case TargetLowering::Legal:
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return Legal;
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case TargetLowering::Promote:
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2008-10-30 08:01:45 +00:00
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// Promote can mean
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2008-11-06 08:51:32 +00:00
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// 1) For integers, use a larger integer type (e.g. i8 -> i32).
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// 2) For vectors, use a wider vector type (e.g. v3i32 -> v4i32).
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if (!VT.isVector())
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2008-10-30 08:01:45 +00:00
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return PromoteInteger;
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2008-11-06 08:51:32 +00:00
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else
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2008-12-18 20:03:17 +00:00
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return WidenVector;
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
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case TargetLowering::Expand:
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Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
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// Expand can mean
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// 1) split scalar in half, 2) convert a float to an integer,
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|
|
// 3) scalarize a single-element vector, 4) split a vector in two.
|
2008-06-06 12:08:01 +00:00
|
|
|
if (!VT.isVector()) {
|
2008-06-17 14:27:01 +00:00
|
|
|
if (VT.isInteger())
|
|
|
|
return ExpandInteger;
|
|
|
|
else if (VT.getSizeInBits() ==
|
|
|
|
TLI.getTypeToTransformTo(VT).getSizeInBits())
|
2008-06-20 17:49:55 +00:00
|
|
|
return SoftenFloat;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
else
|
2008-06-17 14:27:01 +00:00
|
|
|
return ExpandFloat;
|
2008-06-06 12:08:01 +00:00
|
|
|
} else if (VT.getVectorNumElements() == 1) {
|
2008-07-10 15:25:04 +00:00
|
|
|
return ScalarizeVector;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
} else {
|
2008-07-10 15:25:04 +00:00
|
|
|
return SplitVector;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
}
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
}
|
2007-12-08 20:16:06 +00:00
|
|
|
}
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
/// isTypeLegal - Return true if this type is legal on this target.
|
2008-06-06 12:08:01 +00:00
|
|
|
bool isTypeLegal(MVT VT) const {
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal;
|
2007-12-08 20:16:06 +00:00
|
|
|
}
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2008-07-14 17:15:45 +00:00
|
|
|
/// IgnoreNodeResults - Pretend all of this node's results are legal.
|
2009-01-13 14:42:39 +00:00
|
|
|
/// FIXME: Remove once PR2957 is done.
|
2008-07-14 17:15:45 +00:00
|
|
|
bool IgnoreNodeResults(SDNode *N) const {
|
2008-12-18 20:03:17 +00:00
|
|
|
return N->getOpcode() == ISD::TargetConstant ||
|
|
|
|
IgnoredNodesResultsSet.count(N);
|
2008-07-14 17:15:45 +00:00
|
|
|
}
|
|
|
|
|
2008-12-18 20:03:17 +00:00
|
|
|
/// IgnoredNode - Set of nodes whose result don't need to be legal.
|
2009-01-13 14:42:39 +00:00
|
|
|
/// FIXME: Remove once PR2957 is done.
|
2008-12-18 20:03:17 +00:00
|
|
|
DenseSet<SDNode*> IgnoredNodesResultsSet;
|
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
/// PromotedIntegers - For integer nodes that are below legal width, this map
|
|
|
|
/// indicates what promoted value to use.
|
2008-07-27 21:46:04 +00:00
|
|
|
DenseMap<SDValue, SDValue> PromotedIntegers;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
/// ExpandedIntegers - For integer nodes that need to be expanded this map
|
|
|
|
/// indicates which operands are the expanded version of the input.
|
2008-07-27 21:46:04 +00:00
|
|
|
DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedIntegers;
|
2007-12-08 20:16:06 +00:00
|
|
|
|
2008-06-20 17:49:55 +00:00
|
|
|
/// SoftenedFloats - For floating point nodes converted to integers of
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
/// the same size, this map indicates the converted value to use.
|
2008-07-27 21:46:04 +00:00
|
|
|
DenseMap<SDValue, SDValue> SoftenedFloats;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
/// ExpandedFloats - For float nodes that need to be expanded this map
|
|
|
|
/// indicates which operands are the expanded version of the input.
|
2008-07-27 21:46:04 +00:00
|
|
|
DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedFloats;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
/// ScalarizedVectors - For nodes that are <1 x ty>, this map indicates the
|
2007-12-08 20:16:06 +00:00
|
|
|
/// scalar value of type 'ty' to use.
|
2008-07-27 21:46:04 +00:00
|
|
|
DenseMap<SDValue, SDValue> ScalarizedVectors;
|
2007-12-08 22:40:18 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
/// SplitVectors - For nodes that need to be split this map indicates
|
2007-12-08 22:40:18 +00:00
|
|
|
/// which operands are the expanded version of the input.
|
2008-07-27 21:46:04 +00:00
|
|
|
DenseMap<SDValue, std::pair<SDValue, SDValue> > SplitVectors;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2009-01-13 14:42:39 +00:00
|
|
|
/// WidenedVectors - For vector nodes that need to be widened, indicates
|
|
|
|
/// the widened value to use.
|
2008-12-18 20:03:17 +00:00
|
|
|
DenseMap<SDValue, SDValue> WidenedVectors;
|
|
|
|
|
2008-10-29 06:42:19 +00:00
|
|
|
/// ReplacedValues - For values that have been replaced with another,
|
|
|
|
/// indicates the replacement value to use.
|
|
|
|
DenseMap<SDValue, SDValue> ReplacedValues;
|
2007-12-08 20:16:06 +00:00
|
|
|
|
|
|
|
/// Worklist - This defines a worklist of nodes to process. In order to be
|
|
|
|
/// pushed onto this worklist, all operands of a node must have already been
|
|
|
|
/// processed.
|
|
|
|
SmallVector<SDNode*, 128> Worklist;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
public:
|
|
|
|
explicit DAGTypeLegalizer(SelectionDAG &dag)
|
|
|
|
: TLI(dag.getTargetLoweringInfo()), DAG(dag),
|
|
|
|
ValueTypeActions(TLI.getValueTypeActions()) {
|
|
|
|
assert(MVT::LAST_VALUETYPE <= 32 &&
|
|
|
|
"Too many value types for ValueTypeActions to hold!");
|
2008-06-17 14:27:01 +00:00
|
|
|
}
|
|
|
|
|
2008-11-24 14:53:14 +00:00
|
|
|
/// run - This is the main entry point for the type legalizer. This does a
|
|
|
|
/// top-down traversal of the dag, legalizing types as it goes. Returns
|
|
|
|
/// "true" if it made any changes.
|
|
|
|
bool run();
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-07-02 09:56:41 +00:00
|
|
|
void NoteDeletion(SDNode *Old, SDNode *New) {
|
|
|
|
ExpungeNode(Old);
|
|
|
|
ExpungeNode(New);
|
|
|
|
for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
|
2008-10-29 06:42:19 +00:00
|
|
|
ReplacedValues[SDValue(Old, i)] = SDValue(New, i);
|
2008-06-11 11:42:12 +00:00
|
|
|
}
|
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
private:
|
2008-10-29 06:42:19 +00:00
|
|
|
SDNode *AnalyzeNewNode(SDNode *N);
|
|
|
|
void AnalyzeNewValue(SDValue &Val);
|
2008-07-02 09:56:41 +00:00
|
|
|
void ExpungeNode(SDNode *N);
|
2008-12-09 21:33:20 +00:00
|
|
|
void PerformExpensiveChecks();
|
|
|
|
void RemapValue(SDValue &N);
|
2007-12-08 20:16:06 +00:00
|
|
|
|
2007-12-08 21:59:32 +00:00
|
|
|
// Common routines.
|
2009-01-01 20:36:20 +00:00
|
|
|
SDValue BitConvertToInteger(SDValue Op);
|
2009-03-29 13:51:06 +00:00
|
|
|
SDValue BitConvertVectorToIntegerVector(SDValue Op);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue CreateStackStoreLoad(SDValue Op, MVT DestVT);
|
2009-01-21 09:00:29 +00:00
|
|
|
bool CustomLowerResults(SDNode *N, MVT VT, bool LegalizeResult);
|
2009-01-01 20:36:20 +00:00
|
|
|
SDValue GetVectorElementPointer(SDValue VecPtr, MVT EltVT, SDValue Index);
|
|
|
|
SDValue JoinIntegers(SDValue Lo, SDValue Hi);
|
|
|
|
SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
|
2009-01-31 00:11:23 +00:00
|
|
|
const SDValue *Ops, unsigned NumOps, bool isSigned,
|
|
|
|
DebugLoc dl);
|
2009-01-01 20:36:20 +00:00
|
|
|
SDValue PromoteTargetBoolean(SDValue Bool, MVT VT);
|
|
|
|
void ReplaceValueWith(SDValue From, SDValue To);
|
2009-01-26 21:54:18 +00:00
|
|
|
void ReplaceValueWithHelper(SDValue From, SDValue To);
|
2009-01-01 20:36:20 +00:00
|
|
|
void SetIgnoredNodeResult(SDNode* N);
|
2008-07-27 21:46:04 +00:00
|
|
|
void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT,
|
|
|
|
SDValue &Lo, SDValue &Hi);
|
2008-06-15 20:00:14 +00:00
|
|
|
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Integer Promotion Support: LegalizeIntegerTypes.cpp
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-11-18 20:56:22 +00:00
|
|
|
/// GetPromotedInteger - Given a processed operand Op which was promoted to a
|
2008-11-20 10:34:43 +00:00
|
|
|
/// larger integer type, this returns the promoted value. The low bits of the
|
2008-11-18 20:56:22 +00:00
|
|
|
/// promoted value corresponding to the original type are exactly equal to Op.
|
|
|
|
/// The extra bits contain rubbish, so the promoted value may need to be zero-
|
|
|
|
/// or sign-extended from the original type before it is usable (the helpers
|
|
|
|
/// SExtPromotedInteger and ZExtPromotedInteger can do this for you).
|
|
|
|
/// For example, if Op is an i16 and was promoted to an i32, then this method
|
|
|
|
/// returns an i32, the lower 16 bits of which coincide with Op, and the upper
|
|
|
|
/// 16 bits of which contain rubbish.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue GetPromotedInteger(SDValue Op) {
|
|
|
|
SDValue &PromotedOp = PromotedIntegers[Op];
|
2008-10-29 06:42:19 +00:00
|
|
|
RemapValue(PromotedOp);
|
2008-08-28 21:40:38 +00:00
|
|
|
assert(PromotedOp.getNode() && "Operand wasn't promoted?");
|
2007-12-08 20:16:06 +00:00
|
|
|
return PromotedOp;
|
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
void SetPromotedInteger(SDValue Op, SDValue Result);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-11-18 20:56:22 +00:00
|
|
|
/// SExtPromotedInteger - Get a promoted operand and sign extend it to the
|
|
|
|
/// final size.
|
|
|
|
SDValue SExtPromotedInteger(SDValue Op) {
|
|
|
|
MVT OldVT = Op.getValueType();
|
2009-02-05 00:20:09 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-11-18 20:56:22 +00:00
|
|
|
Op = GetPromotedInteger(Op);
|
2009-02-05 00:20:09 +00:00
|
|
|
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
|
2008-11-18 20:56:22 +00:00
|
|
|
DAG.getValueType(OldVT));
|
|
|
|
}
|
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
/// ZExtPromotedInteger - Get a promoted operand and zero extend it to the
|
|
|
|
/// final size.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ZExtPromotedInteger(SDValue Op) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT OldVT = Op.getValueType();
|
2009-02-05 00:20:09 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-06-17 14:27:01 +00:00
|
|
|
Op = GetPromotedInteger(Op);
|
2009-02-05 00:20:09 +00:00
|
|
|
return DAG.getZeroExtendInReg(Op, dl, OldVT);
|
2008-06-17 14:27:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Integer Result Promotion.
|
|
|
|
void PromoteIntegerResult(SDNode *N, unsigned ResNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntRes_AssertSext(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_AssertZext(SDNode *N);
|
2008-10-20 16:17:42 +00:00
|
|
|
SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
|
|
|
|
SDValue PromoteIntRes_Atomic2(AtomicSDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntRes_BIT_CONVERT(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_BSWAP(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_Constant(SDNode *N);
|
2008-11-11 05:40:06 +00:00
|
|
|
SDValue PromoteIntRes_CONVERT_RNDSAT(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntRes_CTLZ(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_CTPOP(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_CTTZ(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_LOAD(LoadSDNode *N);
|
2008-12-10 12:30:42 +00:00
|
|
|
SDValue PromoteIntRes_Overflow(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntRes_SDIV(SDNode *N);
|
2008-11-18 21:13:59 +00:00
|
|
|
SDValue PromoteIntRes_SELECT(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntRes_SELECT_CC(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_SETCC(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_SHL(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_SRA(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_SRL(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_TRUNCATE(SDNode *N);
|
2008-12-10 12:30:42 +00:00
|
|
|
SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntRes_UDIV(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_UNDEF(SDNode *N);
|
|
|
|
SDValue PromoteIntRes_VAARG(SDNode *N);
|
2008-12-10 12:30:42 +00:00
|
|
|
SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
// Integer Operand Promotion.
|
|
|
|
bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
|
2009-03-04 06:23:34 +00:00
|
|
|
SDValue PromoteIntOp_BIT_CONVERT(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
|
|
|
|
SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
|
|
|
|
SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
|
|
|
|
SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
|
2008-11-17 00:41:12 +00:00
|
|
|
SDValue PromoteIntOp_CONVERT_RNDSAT(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
|
|
|
|
SDValue PromoteIntOp_MEMBARRIER(SDNode *N);
|
2009-03-18 06:24:04 +00:00
|
|
|
SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
|
|
|
|
SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
|
|
|
|
SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
|
2009-02-02 17:19:39 +00:00
|
|
|
SDValue PromoteIntOp_Shift(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
|
2008-11-18 20:56:22 +00:00
|
|
|
SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
|
|
|
|
SDValue PromoteIntOp_TRUNCATE(SDNode *N);
|
2008-11-18 20:56:22 +00:00
|
|
|
SDValue PromoteIntOp_UINT_TO_FP(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
|
|
|
|
|
|
|
|
void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
|
2007-12-08 21:59:32 +00:00
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Integer Expansion Support: LegalizeIntegerTypes.cpp
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-11-20 10:34:43 +00:00
|
|
|
/// GetExpandedInteger - Given a processed operand Op which was expanded into
|
|
|
|
/// two integers of half the size, this returns the two halves. The low bits
|
|
|
|
/// of Op are exactly equal to the bits of Lo; the high bits exactly equal Hi.
|
|
|
|
/// For example, if Op is an i64 which was expanded into two i32's, then this
|
|
|
|
/// method returns the two i32's, with Lo being equal to the lower 32 bits of
|
|
|
|
/// Op, and Hi being equal to the upper 32 bits.
|
2008-07-27 21:46:04 +00:00
|
|
|
void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
// Integer Result Expansion.
|
|
|
|
void ExpandIntegerResult(SDNode *N, unsigned ResNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
|
|
|
|
void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
void ExpandShiftByConstant(SDNode *N, unsigned Amt,
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue &Lo, SDValue &Hi);
|
|
|
|
bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2009-03-31 19:39:24 +00:00
|
|
|
bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2007-12-08 20:16:06 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
// Integer Operand Expansion.
|
|
|
|
bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ExpandIntOp_BIT_CONVERT(SDNode *N);
|
|
|
|
SDValue ExpandIntOp_BR_CC(SDNode *N);
|
|
|
|
SDValue ExpandIntOp_BUILD_VECTOR(SDNode *N);
|
|
|
|
SDValue ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
|
|
|
|
SDValue ExpandIntOp_SELECT_CC(SDNode *N);
|
|
|
|
SDValue ExpandIntOp_SETCC(SDNode *N);
|
2009-02-02 17:19:39 +00:00
|
|
|
SDValue ExpandIntOp_Shift(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ExpandIntOp_SINT_TO_FP(SDNode *N);
|
|
|
|
SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
|
|
|
|
SDValue ExpandIntOp_TRUNCATE(SDNode *N);
|
|
|
|
SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
|
|
|
|
|
|
|
|
void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
|
2009-01-31 00:11:23 +00:00
|
|
|
ISD::CondCode &CCCode, DebugLoc dl);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Float to Integer Conversion Support: LegalizeFloatTypes.cpp
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
2008-11-20 10:34:43 +00:00
|
|
|
/// GetSoftenedFloat - Given a processed operand Op which was converted to an
|
|
|
|
/// integer of the same size, this returns the integer. The integer contains
|
|
|
|
/// exactly the same bits as Op - only the type changed. For example, if Op
|
|
|
|
/// is an f32 which was softened to an i32, then this method returns an i32,
|
|
|
|
/// the bits of which coincide with those of Op.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue GetSoftenedFloat(SDValue Op) {
|
|
|
|
SDValue &SoftenedOp = SoftenedFloats[Op];
|
2008-10-29 06:42:19 +00:00
|
|
|
RemapValue(SoftenedOp);
|
2008-08-28 21:40:38 +00:00
|
|
|
assert(SoftenedOp.getNode() && "Operand wasn't converted to integer?");
|
2008-06-20 17:49:55 +00:00
|
|
|
return SoftenedOp;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
void SetSoftenedFloat(SDValue Op, SDValue Result);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
|
|
|
// Result Float to Integer Conversion.
|
2008-06-20 17:49:55 +00:00
|
|
|
void SoftenFloatResult(SDNode *N, unsigned OpNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_BIT_CONVERT(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_ConstantFP(ConstantFPSDNode *N);
|
2009-03-29 13:51:06 +00:00
|
|
|
SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
|
2008-08-07 19:01:24 +00:00
|
|
|
SDValue SoftenFloatRes_FABS(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_FADD(SDNode *N);
|
2008-11-18 09:15:03 +00:00
|
|
|
SDValue SoftenFloatRes_FCEIL(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N);
|
2008-11-18 09:15:03 +00:00
|
|
|
SDValue SoftenFloatRes_FCOS(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_FDIV(SDNode *N);
|
2008-11-18 09:15:03 +00:00
|
|
|
SDValue SoftenFloatRes_FEXP(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FEXP2(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FFLOOR(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FLOG(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FLOG2(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FLOG10(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_FMUL(SDNode *N);
|
2008-11-18 09:15:03 +00:00
|
|
|
SDValue SoftenFloatRes_FNEARBYINT(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FNEG(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
|
2008-10-22 11:49:09 +00:00
|
|
|
SDValue SoftenFloatRes_FPOW(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_FPOWI(SDNode *N);
|
2009-04-08 16:20:57 +00:00
|
|
|
SDValue SoftenFloatRes_FREM(SDNode *N);
|
2008-11-18 09:15:03 +00:00
|
|
|
SDValue SoftenFloatRes_FRINT(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FSIN(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_FSQRT(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_FSUB(SDNode *N);
|
2008-11-18 09:15:03 +00:00
|
|
|
SDValue SoftenFloatRes_FTRUNC(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatRes_LOAD(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_SELECT(SDNode *N);
|
|
|
|
SDValue SoftenFloatRes_SELECT_CC(SDNode *N);
|
2009-04-08 13:33:37 +00:00
|
|
|
SDValue SoftenFloatRes_UNDEF(SDNode *N);
|
2009-02-21 19:11:18 +00:00
|
|
|
SDValue SoftenFloatRes_VAARG(SDNode *N);
|
2008-11-10 17:36:26 +00:00
|
|
|
SDValue SoftenFloatRes_XINT_TO_FP(SDNode *N);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
|
|
|
// Operand Float to Integer Conversion.
|
2008-06-20 17:49:55 +00:00
|
|
|
bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatOp_BIT_CONVERT(SDNode *N);
|
|
|
|
SDValue SoftenFloatOp_BR_CC(SDNode *N);
|
2008-08-07 19:01:24 +00:00
|
|
|
SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SoftenFloatOp_FP_TO_SINT(SDNode *N);
|
|
|
|
SDValue SoftenFloatOp_FP_TO_UINT(SDNode *N);
|
|
|
|
SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
|
|
|
|
SDValue SoftenFloatOp_SETCC(SDNode *N);
|
|
|
|
SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
|
|
|
|
|
|
|
|
void SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
|
2009-01-31 00:11:23 +00:00
|
|
|
ISD::CondCode &CCCode, DebugLoc dl);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Float Expansion Support: LegalizeFloatTypes.cpp
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-11-20 10:34:43 +00:00
|
|
|
/// GetExpandedFloat - Given a processed operand Op which was expanded into
|
|
|
|
/// two floating point values of half the size, this returns the two halves.
|
|
|
|
/// The low bits of Op are exactly equal to the bits of Lo; the high bits
|
|
|
|
/// exactly equal Hi. For example, if Op is a ppcf128 which was expanded
|
|
|
|
/// into two f64's, then this method returns the two f64's, with Lo being
|
|
|
|
/// equal to the lower 64 bits of Op, and Hi to the upper 64 bits.
|
2008-07-27 21:46:04 +00:00
|
|
|
void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
// Float Result Expansion.
|
|
|
|
void ExpandFloatResult(SDNode *N, unsigned ResNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-10-31 14:06:52 +00:00
|
|
|
void ExpandFloatRes_FCEIL (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FCOS (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-10-31 14:06:52 +00:00
|
|
|
void ExpandFloatRes_FEXP (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FEXP2 (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FFLOOR (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-10-31 14:06:52 +00:00
|
|
|
void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-10-31 14:06:52 +00:00
|
|
|
void ExpandFloatRes_FPOW (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FPOWI (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-10-31 14:06:52 +00:00
|
|
|
void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
// Float Operand Expansion.
|
|
|
|
bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ExpandFloatOp_BR_CC(SDNode *N);
|
|
|
|
SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
|
|
|
|
SDValue ExpandFloatOp_FP_TO_SINT(SDNode *N);
|
|
|
|
SDValue ExpandFloatOp_FP_TO_UINT(SDNode *N);
|
|
|
|
SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
|
|
|
|
SDValue ExpandFloatOp_SETCC(SDNode *N);
|
|
|
|
SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
|
|
|
|
|
|
|
|
void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
|
2009-01-31 00:43:08 +00:00
|
|
|
ISD::CondCode &CCCode, DebugLoc dl);
|
2008-06-25 16:34:21 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Scalarization Support: LegalizeVectorTypes.cpp
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
2008-11-20 10:34:43 +00:00
|
|
|
/// GetScalarizedVector - Given a processed one-element vector Op which was
|
|
|
|
/// scalarized to its element type, this returns the element. For example,
|
|
|
|
/// if Op is a v1i32, Op = < i32 val >, this method returns val, an i32.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue GetScalarizedVector(SDValue Op) {
|
|
|
|
SDValue &ScalarizedOp = ScalarizedVectors[Op];
|
2008-10-29 06:42:19 +00:00
|
|
|
RemapValue(ScalarizedOp);
|
2008-08-28 21:40:38 +00:00
|
|
|
assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
|
2008-06-17 14:27:01 +00:00
|
|
|
return ScalarizedOp;
|
2007-12-08 21:59:32 +00:00
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
void SetScalarizedVector(SDValue Op, SDValue Result);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
// Vector Result Scalarization: <1 x ty> -> ty.
|
2008-07-10 15:25:04 +00:00
|
|
|
void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ScalarizeVecRes_BinOp(SDNode *N);
|
2008-12-15 21:44:00 +00:00
|
|
|
SDValue ScalarizeVecRes_ShiftOp(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
|
|
|
|
|
|
|
|
SDValue ScalarizeVecRes_BIT_CONVERT(SDNode *N);
|
2008-11-10 20:54:11 +00:00
|
|
|
SDValue ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N);
|
2008-10-20 16:31:21 +00:00
|
|
|
SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ScalarizeVecRes_FPOWI(SDNode *N);
|
|
|
|
SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
|
|
|
|
SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
|
2008-11-18 16:40:48 +00:00
|
|
|
SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ScalarizeVecRes_SELECT(SDNode *N);
|
2008-11-04 17:31:08 +00:00
|
|
|
SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ScalarizeVecRes_UNDEF(SDNode *N);
|
|
|
|
SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
|
|
|
|
SDValue ScalarizeVecRes_VSETCC(SDNode *N);
|
2008-02-27 10:18:23 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
// Vector Operand Scalarization: <1 x ty> -> ty.
|
2008-07-10 15:25:04 +00:00
|
|
|
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ScalarizeVecOp_BIT_CONVERT(SDNode *N);
|
2008-10-20 16:31:21 +00:00
|
|
|
SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
|
|
|
|
SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
|
2007-12-08 20:16:06 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Vector Splitting Support: LegalizeVectorTypes.cpp
|
2007-12-08 22:37:41 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-11-20 10:34:43 +00:00
|
|
|
/// GetSplitVector - Given a processed vector Op which was split into smaller
|
|
|
|
/// vectors, this method returns the smaller vectors. The first elements of
|
|
|
|
/// Op coincide with the elements of Lo; the remaining elements of Op coincide
|
|
|
|
/// with the elements of Hi: Op is what you would get by concatenating Lo and
|
|
|
|
/// Hi. For example, if Op is a v8i32 that was split into two v4i32's, then
|
|
|
|
/// this method returns the two v4i32's, with Lo corresponding to the first 4
|
|
|
|
/// elements of Op, and Hi to the last 4 elements.
|
2008-07-27 21:46:04 +00:00
|
|
|
void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
// Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
|
2008-07-10 15:25:04 +00:00
|
|
|
void SplitVectorResult(SDNode *N, unsigned OpNo);
|
2008-07-27 21:46:04 +00:00
|
|
|
void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
|
|
|
|
void SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-11-10 20:54:11 +00:00
|
|
|
void SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-11-10 04:46:22 +00:00
|
|
|
void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-07-27 21:46:04 +00:00
|
|
|
void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-11-18 16:40:48 +00:00
|
|
|
void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-07-27 21:46:04 +00:00
|
|
|
void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitVecRes_VSETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
|
2008-07-10 15:25:04 +00:00
|
|
|
bool SplitVectorOperand(SDNode *N, unsigned OpNo);
|
2008-10-20 16:31:21 +00:00
|
|
|
SDValue SplitVecOp_UnaryOp(SDNode *N);
|
2008-02-20 17:38:09 +00:00
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue SplitVecOp_BIT_CONVERT(SDNode *N);
|
|
|
|
SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
|
|
|
|
SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
|
|
|
|
SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
|
|
|
|
SDValue SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
|
2008-06-20 18:40:50 +00:00
|
|
|
|
2008-12-18 20:03:17 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Vector Widening Support: LegalizeVectorTypes.cpp
|
|
|
|
//===--------------------------------------------------------------------===//
|
2009-01-13 14:42:39 +00:00
|
|
|
|
|
|
|
/// GetWidenedVector - Given a processed vector Op which was widened into a
|
|
|
|
/// larger vector, this method returns the larger vector. The elements of
|
|
|
|
/// the returned vector consist of the elements of Op followed by elements
|
|
|
|
/// containing rubbish. For example, if Op is a v2i32 that was widened to a
|
|
|
|
/// v4i32, then this method returns a v4i32 for which the first two elements
|
|
|
|
/// are the same as those of Op, while the last two elements contain rubbish.
|
2008-12-18 20:03:17 +00:00
|
|
|
SDValue GetWidenedVector(SDValue Op) {
|
|
|
|
SDValue &WidenedOp = WidenedVectors[Op];
|
|
|
|
RemapValue(WidenedOp);
|
|
|
|
assert(WidenedOp.getNode() && "Operand wasn't widened?");
|
|
|
|
return WidenedOp;
|
|
|
|
}
|
|
|
|
void SetWidenedVector(SDValue Op, SDValue Result);
|
|
|
|
|
|
|
|
// Widen Vector Result Promotion.
|
|
|
|
void WidenVectorResult(SDNode *N, unsigned ResNo);
|
|
|
|
SDValue WidenVecRes_BIT_CONVERT(SDNode* N);
|
|
|
|
SDValue WidenVecRes_BUILD_VECTOR(SDNode* N);
|
|
|
|
SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N);
|
|
|
|
SDValue WidenVecRes_CONVERT_RNDSAT(SDNode* N);
|
|
|
|
SDValue WidenVecRes_EXTRACT_SUBVECTOR(SDNode* N);
|
|
|
|
SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
|
|
|
|
SDValue WidenVecRes_LOAD(SDNode* N);
|
|
|
|
SDValue WidenVecRes_SCALAR_TO_VECTOR(SDNode* N);
|
|
|
|
SDValue WidenVecRes_SELECT(SDNode* N);
|
|
|
|
SDValue WidenVecRes_SELECT_CC(SDNode* N);
|
|
|
|
SDValue WidenVecRes_UNDEF(SDNode *N);
|
|
|
|
SDValue WidenVecRes_VECTOR_SHUFFLE(SDNode *N);
|
|
|
|
SDValue WidenVecRes_VSETCC(SDNode* N);
|
|
|
|
|
|
|
|
SDValue WidenVecRes_Binary(SDNode *N);
|
|
|
|
SDValue WidenVecRes_Convert(SDNode *N);
|
|
|
|
SDValue WidenVecRes_Shift(SDNode *N);
|
|
|
|
SDValue WidenVecRes_Unary(SDNode *N);
|
|
|
|
|
|
|
|
// Widen Vector Operand.
|
|
|
|
bool WidenVectorOperand(SDNode *N, unsigned ResNo);
|
2009-01-15 22:43:38 +00:00
|
|
|
SDValue WidenVecOp_BIT_CONVERT(SDNode *N);
|
2008-12-18 20:03:17 +00:00
|
|
|
SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
|
|
|
|
SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
|
|
|
|
SDValue WidenVecOp_STORE(SDNode* N);
|
|
|
|
|
|
|
|
SDValue WidenVecOp_Convert(SDNode *N);
|
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Vector Widening Utilities Support: LegalizeVectorTypes.cpp
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// Helper genWidenVectorLoads - Helper function to generate a set of
|
|
|
|
/// loads to load a vector with a resulting wider type. It takes
|
|
|
|
/// ExtType: Extension type
|
|
|
|
/// LdChain: list of chains for the load we have generated.
|
|
|
|
/// Chain: incoming chain for the ld vector.
|
|
|
|
/// BasePtr: base pointer to load from.
|
|
|
|
/// SV: memory disambiguation source value.
|
|
|
|
/// SVOffset: memory disambiugation offset.
|
|
|
|
/// Alignment: alignment of the memory.
|
|
|
|
/// isVolatile: volatile load.
|
2009-01-01 19:56:02 +00:00
|
|
|
/// LdWidth: width of memory that we want to load.
|
2008-12-18 20:03:17 +00:00
|
|
|
/// ResType: the wider result result type for the resulting vector.
|
2009-01-31 22:04:51 +00:00
|
|
|
/// dl: DebugLoc to be applied to new nodes
|
2008-12-18 20:03:17 +00:00
|
|
|
SDValue GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain, SDValue Chain,
|
|
|
|
SDValue BasePtr, const Value *SV,
|
|
|
|
int SVOffset, unsigned Alignment,
|
|
|
|
bool isVolatile, unsigned LdWidth,
|
2009-01-31 22:04:51 +00:00
|
|
|
MVT ResType, DebugLoc dl);
|
2008-12-18 20:03:17 +00:00
|
|
|
|
|
|
|
/// Helper genWidenVectorStores - Helper function to generate a set of
|
|
|
|
/// stores to store a widen vector into non widen memory
|
|
|
|
/// It takes
|
|
|
|
/// StChain: list of chains for the stores we have generated
|
|
|
|
/// Chain: incoming chain for the ld vector
|
|
|
|
/// BasePtr: base pointer to load from
|
|
|
|
/// SV: memory disambiguation source value
|
|
|
|
/// SVOffset: memory disambiugation offset
|
|
|
|
/// Alignment: alignment of the memory
|
|
|
|
/// isVolatile: volatile lod
|
2009-01-01 19:56:02 +00:00
|
|
|
/// ValOp: value to store
|
|
|
|
/// StWidth: width of memory that we want to store
|
2009-01-31 22:04:51 +00:00
|
|
|
/// dl: DebugLoc to be applied to new nodes
|
2008-12-18 20:03:17 +00:00
|
|
|
void GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, SDValue Chain,
|
|
|
|
SDValue BasePtr, const Value *SV,
|
|
|
|
int SVOffset, unsigned Alignment,
|
|
|
|
bool isVolatile, SDValue ValOp,
|
2009-01-31 22:04:51 +00:00
|
|
|
unsigned StWidth, DebugLoc dl);
|
2008-12-18 20:03:17 +00:00
|
|
|
|
|
|
|
/// Modifies a vector input (widen or narrows) to a vector of NVT. The
|
|
|
|
/// input vector must have the same element type as NVT.
|
|
|
|
SDValue ModifyToType(SDValue InOp, MVT WidenVT);
|
|
|
|
|
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Generic Splitting: LegalizeTypesGeneric.cpp
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// Legalization methods which only use that the illegal type is split into two
|
|
|
|
// not necessarily identical types. As such they can be used for splitting
|
|
|
|
// vectors and expanding integers and floats.
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
|
2008-06-20 18:40:50 +00:00
|
|
|
if (Op.getValueType().isVector())
|
|
|
|
GetSplitVector(Op, Lo, Hi);
|
|
|
|
else if (Op.getValueType().isInteger())
|
|
|
|
GetExpandedInteger(Op, Lo, Hi);
|
|
|
|
else
|
|
|
|
GetExpandedFloat(Op, Lo, Hi);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
|
|
|
|
/// which is split (or expanded) into two not necessarily identical pieces.
|
|
|
|
void GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT);
|
|
|
|
|
2009-04-25 17:55:53 +00:00
|
|
|
/// GetPairElements - Use ISD::EXTRACT_ELEMENT nodes to extract the low and
|
|
|
|
/// high parts of the given value.
|
|
|
|
void GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi);
|
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
// Generic Result Splitting.
|
2008-07-27 21:46:04 +00:00
|
|
|
void SplitRes_MERGE_VALUES(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitRes_SELECT (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-06-20 18:40:50 +00:00
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Generic Expansion: LegalizeTypesGeneric.cpp
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// Legalization methods which only use that the illegal type is split into two
|
|
|
|
// identical types of half the size, and that the Lo/Hi part is stored first
|
|
|
|
// in memory on little/big-endian machines, followed by the Hi/Lo part. As
|
|
|
|
// such they can be used for expanding integers and floats.
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
|
2008-06-20 18:40:50 +00:00
|
|
|
if (Op.getValueType().isInteger())
|
|
|
|
GetExpandedInteger(Op, Lo, Hi);
|
|
|
|
else
|
|
|
|
GetExpandedFloat(Op, Lo, Hi);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Generic Result Expansion.
|
2008-07-27 21:46:04 +00:00
|
|
|
void ExpandRes_BIT_CONVERT (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
|
|
|
|
void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-10-29 14:25:28 +00:00
|
|
|
void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi);
|
2008-06-20 18:40:50 +00:00
|
|
|
|
|
|
|
// Generic Operand Expansion.
|
2008-12-15 06:57:02 +00:00
|
|
|
SDValue ExpandOp_BIT_CONVERT (SDNode *N);
|
|
|
|
SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
|
|
|
|
SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N);
|
|
|
|
SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N);
|
|
|
|
SDValue ExpandOp_SCALAR_TO_VECTOR (SDNode *N);
|
|
|
|
SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
|
2007-12-08 20:16:06 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end namespace llvm.
|
|
|
|
|
|
|
|
#endif
|