2008-02-10 18:45:23 +00:00
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//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
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2005-04-21 22:55:34 +00:00
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//
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2003-10-20 19:43:21 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 22:55:34 +00:00
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//
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2003-10-20 19:43:21 +00:00
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//===----------------------------------------------------------------------===//
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2002-12-17 04:03:08 +00:00
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//
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2008-02-10 18:45:23 +00:00
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// This file implements the TargetRegisterInfo interface.
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2002-12-17 04:03:08 +00:00
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//
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//===----------------------------------------------------------------------===//
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2006-08-03 17:27:09 +00:00
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#include "llvm/Target/TargetMachine.h"
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2008-02-10 18:45:23 +00:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2007-02-15 05:59:24 +00:00
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#include "llvm/ADT/BitVector.h"
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2010-12-14 18:53:39 +00:00
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#include "llvm/Support/raw_ostream.h"
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2006-03-28 13:48:33 +00:00
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2006-02-01 18:10:56 +00:00
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using namespace llvm;
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2003-11-11 22:41:34 +00:00
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2011-12-20 02:50:00 +00:00
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void TargetRegisterClass::anchor() { }
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2011-06-24 01:44:41 +00:00
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TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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2002-12-28 20:34:18 +00:00
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regclass_iterator RCB, regclass_iterator RCE,
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2011-06-28 21:14:33 +00:00
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const char *const *subregindexnames)
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2011-06-24 01:44:41 +00:00
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: InfoDesc(ID), SubRegIndexNames(subregindexnames),
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2010-05-25 19:49:38 +00:00
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RegClassBegin(RCB), RegClassEnd(RCE) {
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2002-12-17 04:03:08 +00:00
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}
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2008-02-10 18:45:23 +00:00
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TargetRegisterInfo::~TargetRegisterInfo() {}
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2004-10-27 06:00:53 +00:00
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2011-01-09 03:05:53 +00:00
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void PrintReg::print(raw_ostream &OS) const {
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if (!Reg)
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OS << "%noreg";
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2011-01-09 21:17:37 +00:00
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else if (TargetRegisterInfo::isStackSlot(Reg))
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OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
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2011-01-09 03:05:53 +00:00
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else if (TargetRegisterInfo::isVirtualRegister(Reg))
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OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
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2011-01-09 21:17:37 +00:00
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else if (TRI && Reg < TRI->getNumRegs())
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2011-01-09 03:05:53 +00:00
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OS << '%' << TRI->getName(Reg);
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2010-12-14 18:53:39 +00:00
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else
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2011-01-09 03:05:53 +00:00
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OS << "%physreg" << Reg;
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if (SubIdx) {
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if (TRI)
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OS << ':' << TRI->getSubRegIndexName(SubIdx);
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else
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OS << ":sub(" << SubIdx << ')';
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}
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2010-12-14 18:53:39 +00:00
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}
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2010-06-02 12:39:06 +00:00
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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2010-07-06 15:31:55 +00:00
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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2010-06-02 12:39:06 +00:00
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const TargetRegisterClass *
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2010-06-29 14:02:34 +00:00
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TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
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2010-06-02 12:39:06 +00:00
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assert(isPhysicalRegister(reg) && "reg must be a physical register");
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// Pick the most sub register class of the right type that contains
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// this physreg.
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const TargetRegisterClass* BestRC = 0;
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for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
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const TargetRegisterClass* RC = *I;
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2010-06-29 14:02:34 +00:00
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if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
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(!BestRC || BestRC->hasSubClass(RC)))
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2010-06-02 12:39:06 +00:00
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BestRC = RC;
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}
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assert(BestRC && "Couldn't find the register class");
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return BestRC;
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}
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2007-04-17 23:33:39 +00:00
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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2009-10-09 22:09:05 +00:00
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static void getAllocatableSetForRC(const MachineFunction &MF,
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2010-09-02 18:44:51 +00:00
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const TargetRegisterClass *RC, BitVector &R){
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2011-06-17 23:17:13 +00:00
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ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
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for (unsigned i = 0; i != Order.size(); ++i)
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R.set(Order[i]);
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2007-04-17 23:33:39 +00:00
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}
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2009-10-09 22:09:05 +00:00
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BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
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2008-02-10 18:45:23 +00:00
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const TargetRegisterClass *RC) const {
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2011-06-24 01:44:41 +00:00
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BitVector Allocatable(getNumRegs());
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2007-04-17 23:33:39 +00:00
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if (RC) {
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getAllocatableSetForRC(MF, RC, Allocatable);
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2010-09-02 18:18:52 +00:00
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} else {
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for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
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2007-04-17 23:33:39 +00:00
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E = regclass_end(); I != E; ++I)
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2011-06-02 23:07:20 +00:00
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if ((*I)->isAllocatable())
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getAllocatableSetForRC(MF, *I, Allocatable);
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2010-09-02 18:18:52 +00:00
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}
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2010-09-02 16:31:21 +00:00
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// Mask out the reserved registers
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BitVector Reserved = getReservedRegs(MF);
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2010-10-28 18:41:23 +00:00
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Allocatable &= Reserved.flip();
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2010-09-02 16:31:21 +00:00
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2004-08-26 22:21:04 +00:00
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return Allocatable;
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2005-04-21 22:55:34 +00:00
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}
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2006-03-28 13:48:33 +00:00
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2009-04-30 21:23:32 +00:00
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const TargetRegisterClass *
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2011-09-30 22:18:51 +00:00
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TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B) const {
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2011-09-30 22:19:07 +00:00
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// First take care of the trivial cases.
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2009-04-30 21:23:32 +00:00
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if (A == B)
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return A;
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if (!A || !B)
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return 0;
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2011-09-30 22:19:07 +00:00
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// Register classes are ordered topologically, so the largest common
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// sub-class it the common sub-class with the smallest ID.
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const unsigned *SubA = A->getSubClassMask();
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const unsigned *SubB = B->getSubClassMask();
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2009-04-30 21:23:32 +00:00
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2011-09-30 22:19:07 +00:00
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// We could start the search from max(A.ID, B.ID), but we are only going to
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// execute 2-3 iterations anyway.
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for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32)
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if (unsigned Common = *SubA++ & *SubB++)
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return getRegClass(Base + CountTrailingZeros_32(Common));
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// No common sub-class exists.
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return NULL;
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2009-04-30 21:23:32 +00:00
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}
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