2010-08-17 16:20:04 +00:00
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//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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//===----------------------------------------------------------------------===//
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2007-08-18 02:18:07 +00:00
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// This is the top level entry point for the Mips target.
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//===----------------------------------------------------------------------===//
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2007-08-18 02:18:07 +00:00
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// Target-independent interfaces
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2007-06-06 07:42:06 +00:00
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//===----------------------------------------------------------------------===//
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2008-11-24 07:34:46 +00:00
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include "llvm/Target/Target.td"
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2007-06-06 07:42:06 +00:00
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//===----------------------------------------------------------------------===//
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// Register File, Calling Conv, Instruction Descriptions
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2007-06-06 07:42:06 +00:00
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//===----------------------------------------------------------------------===//
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include "MipsRegisterInfo.td"
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2007-08-18 02:18:07 +00:00
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include "MipsSchedule.td"
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2007-06-06 07:42:06 +00:00
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include "MipsInstrInfo.td"
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2007-08-18 02:18:07 +00:00
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include "MipsCallingConv.td"
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2007-06-06 07:42:06 +00:00
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2010-04-05 03:10:20 +00:00
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def MipsInstrInfo : InstrInfo;
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2007-08-18 02:18:07 +00:00
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2007-06-06 07:42:06 +00:00
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//===----------------------------------------------------------------------===//
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// Mips Subtarget features //
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2007-06-06 07:42:06 +00:00
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//===----------------------------------------------------------------------===//
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2008-07-09 05:32:22 +00:00
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"General Purpose Registers are 64-bit wide.">;
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2008-07-09 05:32:22 +00:00
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"Support 64-bit FP registers.">;
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2008-07-09 05:32:22 +00:00
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"true", "Only supports single precision float">;
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2008-07-09 05:32:22 +00:00
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def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"Enable o32 ABI">;
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2008-07-09 05:32:22 +00:00
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def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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"Enable eabi ABI">;
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2010-11-08 21:42:32 +00:00
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def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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2008-07-09 05:32:22 +00:00
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"true", "Enable vector FPU instructions.">;
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2010-11-08 21:42:32 +00:00
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def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
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2008-07-09 05:32:22 +00:00
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"Enable 'signext in register' instructions.">;
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2010-11-08 21:42:32 +00:00
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def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
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2008-07-30 17:01:06 +00:00
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"Enable 'conditional move' instructions.">;
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def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
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"Enable 'multiply add/sub' instructions.">;
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def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true",
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"Enable 'min/max' instructions.">;
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def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
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"Enable 'byte/half swap' instructions.">;
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def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
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"Enable 'count leading bits' instructions.">;
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2010-11-08 21:42:32 +00:00
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def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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"Mips1 ISA Support">;
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips2 ISA Support">;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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2010-11-10 02:13:22 +00:00
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"Mips32 ISA Support",
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[FeatureCondMov, FeatureBitCount]>;
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2010-11-08 21:42:32 +00:00
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips32, FeatureSEInReg]>;
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2007-06-06 07:42:06 +00:00
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//===----------------------------------------------------------------------===//
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// Mips processors supported.
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//===----------------------------------------------------------------------===//
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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2009-05-27 17:23:44 +00:00
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def : Proc<"mips1", [FeatureMips1]>;
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def : Proc<"r2000", [FeatureMips1]>;
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def : Proc<"r3000", [FeatureMips1]>;
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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def : Proc<"mips2", [FeatureMips2]>;
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def : Proc<"r6000", [FeatureMips2]>;
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2010-11-08 21:42:32 +00:00
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def : Proc<"4ke", [FeatureMips32r2]>;
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// Allegrex is a 32bit subset of r4000, both for interger and fp registers,
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// but much more similar to Mips2 than Mips3. It also contains some of
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// Mips32/Mips32r2 instructions and a custom vector fpu processor.
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def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
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2008-07-30 17:01:06 +00:00
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FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
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FeatureMinMax, FeatureSwap, FeatureBitCount]>;
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2007-06-06 07:42:06 +00:00
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def Mips : Target {
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let InstructionSet = MipsInstrInfo;
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}
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