2002-02-03 07:11:59 +00:00
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//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
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//
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// This file contains the declaration of the MachineInstr class, which is the
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// basic representation for all target dependant machine instructions used by
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// the back end.
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//
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//===----------------------------------------------------------------------===//
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2001-07-21 12:39:03 +00:00
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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2002-05-19 15:39:59 +00:00
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#include "llvm/Annotation.h"
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2002-10-28 02:11:53 +00:00
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#include "Support/iterator"
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2002-10-28 02:29:46 +00:00
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#include "Support/NonCopyable.h"
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#include <vector>
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class Value;
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class Function;
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typedef int MachineOpCode;
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typedef int OpCodeMask;
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2001-07-28 04:06:37 +00:00
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2001-07-21 12:39:03 +00:00
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//---------------------------------------------------------------------------
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// class MachineOperand
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//
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// Purpose:
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// Representation of each machine instruction operand.
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// This class is designed so that you can allocate a vector of operands
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// first and initialize each one later.
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//
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// E.g, for this VM instruction:
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// ptr = alloca type, numElements
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// we generate 2 machine instructions on the SPARC:
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//
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// mul Constant, Numelements -> Reg
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// add %sp, Reg -> Ptr
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//
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// Each instruction has 3 operands, listed above. Of those:
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// - Reg, NumElements, and Ptr are of operand type MO_Register.
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// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
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//
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// For the register operands, the virtual register type is as follows:
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//
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// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
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// MachineInstr* minstr will point to the instruction that computes reg.
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//
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// - %sp will be of virtual register type MO_MachineReg.
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// The field regNum identifies the machine register.
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//
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// - NumElements will be of virtual register type MO_VirtualReg.
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// The field Value* value identifies the value.
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//
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// - Ptr will also be of virtual register type MO_VirtualReg.
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// Again, the field Value* value identifies the value.
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//
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//---------------------------------------------------------------------------
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class MachineOperand {
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public:
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enum MachineOperandType {
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2001-07-28 04:06:37 +00:00
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MO_VirtualRegister, // virtual register for *value
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MO_MachineRegister, // pre-assigned machine register `regNum'
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2001-07-21 12:39:03 +00:00
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MO_CCRegister,
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MO_SignExtendedImmed,
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MO_UnextendedImmed,
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MO_PCRelativeDisp,
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};
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2002-07-10 21:50:57 +00:00
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private:
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// Bit fields of the flags variable used for different operand properties
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static const char DEFFLAG = 0x1; // this is a def of the operand
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static const char DEFUSEFLAG = 0x2; // this is both a def and a use
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static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
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static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
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static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
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static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
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2001-07-28 04:06:37 +00:00
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private:
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union {
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Value* value; // BasicBlockVal for a label operand.
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2001-07-21 12:39:03 +00:00
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// ConstantVal for a non-address immediate.
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2001-07-28 04:06:37 +00:00
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// Virtual register for an SSA operand,
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// including hidden operands required for
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2001-09-15 20:16:41 +00:00
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// the generated machine code.
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2001-07-28 04:06:37 +00:00
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int64_t immedVal; // constant value for an explicit constant
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};
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2001-08-07 20:14:30 +00:00
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2002-10-22 00:15:13 +00:00
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MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
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char flags; // see bit field definitions above
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2001-10-15 16:22:44 +00:00
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int regNum; // register number for an explicit register
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2001-09-15 20:16:41 +00:00
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// will be set for a value after reg allocation
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2002-10-28 20:48:39 +00:00
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private:
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MachineOperand()
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: immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1) {}
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MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
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: immedVal(ImmVal), opType(OpTy), flags(0), regNum(-1) {}
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MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false)
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: immedVal(0), opType(OpTy), flags(isDef ? DEFFLAG : 0), regNum(Reg) {}
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MachineOperand(Value *V, MachineOperandType OpTy,
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bool isDef = false, bool isDNU = false)
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: value(V), opType(OpTy), regNum(-1) {
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flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0);
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}
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public:
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2002-10-28 04:24:49 +00:00
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MachineOperand(const MachineOperand &M)
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: immedVal(M.immedVal), opType(M.opType), flags(M.flags), regNum(M.regNum) {
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}
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~MachineOperand() {}
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2001-07-21 12:39:03 +00:00
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2001-07-28 04:06:37 +00:00
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// Accessor methods. Caller is responsible for checking the
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// operand type before invoking the corresponding accessor.
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//
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MachineOperandType getType() const { return opType; }
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2002-10-28 04:24:49 +00:00
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2001-08-09 19:18:33 +00:00
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inline Value* getVRegValue () const {
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2001-09-10 20:02:12 +00:00
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_PCRelativeDisp);
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2001-07-28 04:06:37 +00:00
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return value;
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}
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2002-08-14 16:54:11 +00:00
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inline Value* getVRegValueOrNull() const {
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return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_PCRelativeDisp)? value : NULL;
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}
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2001-11-05 03:56:02 +00:00
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inline int getMachineRegNum() const {
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2001-07-28 04:06:37 +00:00
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assert(opType == MO_MachineRegister);
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2001-11-05 03:56:02 +00:00
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return regNum;
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2001-07-28 04:06:37 +00:00
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}
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2001-08-09 19:18:33 +00:00
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inline int64_t getImmedValue () const {
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2001-10-28 21:24:50 +00:00
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assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
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2001-07-28 04:06:37 +00:00
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return immedVal;
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}
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2002-10-28 04:24:49 +00:00
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bool opIsDef () const { return flags & DEFFLAG; }
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bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
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bool opHiBits32 () const { return flags & HIFLAG32; }
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bool opLoBits32 () const { return flags & LOFLAG32; }
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bool opHiBits64 () const { return flags & HIFLAG64; }
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bool opLoBits64 () const { return flags & LOFLAG64; }
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2002-09-16 15:58:54 +00:00
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// used to check if a machine register has been allocated to this operand
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inline bool hasAllocatedReg() const {
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return (regNum >= 0 &&
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(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister));
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}
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// used to get the reg number if when one is allocated
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2002-07-10 21:50:57 +00:00
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inline int getAllocatedRegNum() const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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return regNum;
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2002-07-08 22:38:45 +00:00
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}
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2002-09-16 15:58:54 +00:00
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2001-07-28 04:06:37 +00:00
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2002-01-20 22:54:45 +00:00
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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2001-08-09 19:18:33 +00:00
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2001-07-28 04:06:37 +00:00
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private:
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2002-07-10 21:50:57 +00:00
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// Construction methods needed for fine-grain control.
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// These must be accessed via coresponding methods in MachineInstr.
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void markDef() { flags |= DEFFLAG; }
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void markDefAndUse() { flags |= DEFUSEFLAG; }
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void markHi32() { flags |= HIFLAG32; }
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void markLo32() { flags |= LOFLAG32; }
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void markHi64() { flags |= HIFLAG64; }
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void markLo64() { flags |= LOFLAG64; }
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2002-07-08 22:38:45 +00:00
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// Replaces the Value with its corresponding physical register after
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2001-09-15 20:16:41 +00:00
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// register allocation is complete
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2001-09-18 22:54:47 +00:00
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void setRegForValue(int reg) {
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2001-10-22 13:57:39 +00:00
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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2001-09-15 20:16:41 +00:00
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regNum = reg;
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}
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2002-07-08 22:38:45 +00:00
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2002-07-10 21:50:57 +00:00
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friend class MachineInstr;
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2001-07-21 12:39:03 +00:00
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};
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//---------------------------------------------------------------------------
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// class MachineInstr
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//
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// Purpose:
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// Representation of each machine instruction.
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//
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// MachineOpCode must be an enum, defined separately for each target.
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// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
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//
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// opCodeMask is used to record variants of an instruction.
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// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
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// ANNUL: if 1: Annul delay slot instruction.
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// PREDICT-NOT-TAKEN: if 1: predict branch not taken.
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// Instead of creating 4 different opcodes for BNZ, we create a single
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// opcode and set bits in opCodeMask for each of these flags.
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2001-10-11 04:23:19 +00:00
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//
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// There are 2 kinds of operands:
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//
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// (1) Explicit operands of the machine instruction in vector operands[]
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//
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// (2) "Implicit operands" are values implicitly used or defined by the
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// machine instruction, such as arguments to a CALL, return value of
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// a CALL (if any), and return value of a RETURN.
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2001-07-21 12:39:03 +00:00
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//---------------------------------------------------------------------------
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2002-10-22 23:16:21 +00:00
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class MachineInstr : public Annotable, // MachineInstrs are annotable
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public NonCopyable { // Disable copy operations
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2002-07-08 22:38:45 +00:00
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MachineOpCode opCode; // the opcode
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OpCodeMask opCodeMask; // extra bits for variants of an opcode
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2002-10-21 13:24:50 +00:00
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std::vector<MachineOperand> operands; // the operands
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2002-10-22 23:16:21 +00:00
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struct ImplicitRef {
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Value *Val;
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bool isDef, isDefAndUse;
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ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
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};
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// implicitRefs - Values implicitly referenced by this machine instruction
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// (eg, call args)
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std::vector<ImplicitRef> implicitRefs;
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// regsUsed - all machine registers used for this instruction, including regs
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// used to save values across the instruction. This is a bitset of registers.
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std::vector<bool> regsUsed;
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2002-10-28 20:48:39 +00:00
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// OperandComplete - Return true if it's illegal to add a new operand
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bool OperandsComplete() const;
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2001-07-21 12:39:03 +00:00
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public:
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2002-10-28 20:59:49 +00:00
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MachineInstr(MachineOpCode Opcode);
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MachineInstr(MachineOpCode Opcode, unsigned numOperands);
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2002-10-28 20:48:39 +00:00
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/// MachineInstr ctor - This constructor only does a _reserve_ of the
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/// operands, not a resize for them. It is expected that if you use this that
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/// you call add* methods below to fill up the operands, instead of the Set
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/// methods.
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///
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MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
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2002-09-20 00:47:49 +00:00
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//
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// Support to rewrite a machine instruction in place: for now, simply
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// replace() and then set new operands with Set.*Operand methods below.
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//
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2002-10-28 20:48:39 +00:00
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void replace(MachineOpCode Opcode, unsigned numOperands,
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OpCodeMask Mask = 0x0);
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2002-09-20 00:47:49 +00:00
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//
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2002-10-28 04:24:49 +00:00
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// The opcode.
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//
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2002-10-28 04:24:49 +00:00
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const MachineOpCode getOpCode() const { return opCode; }
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2001-10-13 06:30:10 +00:00
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2001-10-11 04:23:19 +00:00
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//
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// Information about explicit operands of the instruction
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//
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2002-10-28 04:24:49 +00:00
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unsigned getNumOperands() const { return operands.size(); }
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2001-10-11 04:23:19 +00:00
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2002-10-28 04:24:49 +00:00
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const MachineOperand& getOperand(unsigned i) const {
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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}
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MachineOperand& getOperand(unsigned i) {
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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}
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2002-10-28 04:30:20 +00:00
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MachineOperand::MachineOperandType getOperandType(unsigned i) const {
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2002-10-28 04:45:29 +00:00
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return getOperand(i).getType();
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2002-10-28 04:30:20 +00:00
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}
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bool operandIsDefined(unsigned i) const {
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return getOperand(i).opIsDef();
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}
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bool operandIsDefinedAndUsed(unsigned i) const {
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return getOperand(i).opIsDefAndUse();
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}
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2001-07-21 12:39:03 +00:00
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2001-10-11 04:23:19 +00:00
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//
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// Information about implicit operands of the instruction
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//
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2002-10-28 04:24:49 +00:00
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unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
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2001-10-11 04:23:19 +00:00
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2002-10-28 04:24:49 +00:00
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const Value* getImplicitRef(unsigned i) const {
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assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
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return implicitRefs[i].Val;
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}
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Value* getImplicitRef(unsigned i) {
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assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
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return implicitRefs[i].Val;
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}
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bool implicitRefIsDefined(unsigned i) const {
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assert(i < implicitRefs.size() && "implicitRefIsDefined() out of range!");
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return implicitRefs[i].isDef;
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}
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bool implicitRefIsDefinedAndUsed(unsigned i) const {
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assert(i < implicitRefs.size() && "implicitRefIsDef&Used() out of range!");
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return implicitRefs[i].isDefAndUse;
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}
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2001-08-28 23:11:46 +00:00
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2002-10-28 04:24:49 +00:00
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void addImplicitRef(Value* V, bool isDef=false, bool isDefAndUse=false) {
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implicitRefs.push_back(ImplicitRef(V, isDef, isDefAndUse));
|
|
|
|
}
|
|
|
|
|
|
|
|
void setImplicitRef(unsigned i, Value* V, bool isDef=false,
|
|
|
|
bool isDefAndUse=false) {
|
|
|
|
assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
|
|
|
|
implicitRefs[i] = ImplicitRef(V, isDef, isDefAndUse);
|
|
|
|
}
|
2001-10-11 04:23:19 +00:00
|
|
|
|
2002-07-08 22:38:45 +00:00
|
|
|
//
|
|
|
|
// Information about registers used in this instruction
|
|
|
|
//
|
2002-10-28 04:24:49 +00:00
|
|
|
const std::vector<bool> &getRegsUsed() const { return regsUsed; }
|
2002-07-08 22:38:45 +00:00
|
|
|
|
2002-10-22 23:16:21 +00:00
|
|
|
// insertUsedReg - Add a register to the Used registers set...
|
|
|
|
void insertUsedReg(unsigned Reg) {
|
|
|
|
if (Reg >= regsUsed.size())
|
|
|
|
regsUsed.resize(Reg+1);
|
|
|
|
regsUsed[Reg] = true;
|
|
|
|
}
|
|
|
|
|
2001-10-11 04:23:19 +00:00
|
|
|
//
|
|
|
|
// Debugging support
|
|
|
|
//
|
2002-10-28 04:24:49 +00:00
|
|
|
void dump() const;
|
|
|
|
friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
|
2002-02-05 06:02:59 +00:00
|
|
|
|
|
|
|
//
|
|
|
|
// Define iterators to access the Value operands of the Machine Instruction.
|
|
|
|
// begin() and end() are defined to produce these iterators...
|
|
|
|
//
|
|
|
|
template<class _MI, class _V> class ValOpIterator;
|
|
|
|
typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
|
|
|
|
typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
|
|
|
|
|
|
|
|
|
2001-07-21 12:39:03 +00:00
|
|
|
// Access to set the operands when building the machine instruction
|
2002-07-08 22:38:45 +00:00
|
|
|
//
|
2002-10-28 04:24:49 +00:00
|
|
|
void SetMachineOperandVal(unsigned i,
|
|
|
|
MachineOperand::MachineOperandType operandType,
|
|
|
|
Value* V, bool isDef=false, bool isDefAndUse=false);
|
|
|
|
void SetMachineOperandConst(unsigned i,
|
|
|
|
MachineOperand::MachineOperandType operandType,
|
|
|
|
int64_t intValue);
|
2002-10-28 19:46:59 +00:00
|
|
|
void SetMachineOperandReg(unsigned i, int regNum, bool isDef=false);
|
2002-10-28 04:24:49 +00:00
|
|
|
|
2002-10-28 20:48:39 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Accessors to add operands when building up machine instructions
|
|
|
|
//
|
|
|
|
|
|
|
|
/// addRegOperand - Add a MO_VirtualRegister operand to the end of the
|
|
|
|
/// operands list...
|
|
|
|
///
|
|
|
|
void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) {
|
|
|
|
assert(!OperandsComplete() &&
|
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
|
|
operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
|
|
|
|
isDef, isDefAndUse));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// addRegOperand - Add a symbolic virtual register reference...
|
|
|
|
///
|
|
|
|
void addRegOperand(int reg) {
|
|
|
|
assert(!OperandsComplete() &&
|
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
|
|
operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// addPCDispOperand - Add a PC relative displacement operand to the MI
|
|
|
|
///
|
|
|
|
void addPCDispOperand(Value *V) {
|
|
|
|
assert(!OperandsComplete() &&
|
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
|
|
operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// addMachineRegOperand - Add a virtual register operand to this MachineInstr
|
|
|
|
///
|
|
|
|
void addMachineRegOperand(int reg, bool isDef=false) {
|
|
|
|
assert(!OperandsComplete() &&
|
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
|
|
operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
|
|
|
|
isDef));
|
|
|
|
insertUsedReg(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// addZeroExtImmOperand - Add a zero extended constant argument to the
|
|
|
|
/// machine instruction.
|
|
|
|
///
|
|
|
|
void addZeroExtImmOperand(int64_t intValue) {
|
|
|
|
assert(!OperandsComplete() &&
|
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
|
|
operands.push_back(MachineOperand(intValue,
|
|
|
|
MachineOperand::MO_UnextendedImmed));
|
|
|
|
}
|
|
|
|
|
|
|
|
/// addSignExtImmOperand - Add a zero extended constant argument to the
|
|
|
|
/// machine instruction.
|
|
|
|
///
|
|
|
|
void addSignExtImmOperand(int64_t intValue) {
|
|
|
|
assert(!OperandsComplete() &&
|
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
|
|
|
operands.push_back(MachineOperand(intValue,
|
|
|
|
MachineOperand::MO_SignExtendedImmed));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2002-10-28 04:24:49 +00:00
|
|
|
unsigned substituteValue(const Value* oldVal, Value* newVal,
|
|
|
|
bool defsOnly = true);
|
|
|
|
|
|
|
|
void setOperandHi32(unsigned i) { operands[i].markHi32(); }
|
|
|
|
void setOperandLo32(unsigned i) { operands[i].markLo32(); }
|
|
|
|
void setOperandHi64(unsigned i) { operands[i].markHi64(); }
|
|
|
|
void setOperandLo64(unsigned i) { operands[i].markLo64(); }
|
2001-10-11 04:23:19 +00:00
|
|
|
|
2002-07-10 21:50:57 +00:00
|
|
|
|
2002-10-28 04:24:49 +00:00
|
|
|
// SetRegForOperand - Replaces the Value for the operand with its allocated
|
2002-07-08 22:38:45 +00:00
|
|
|
// physical register after register allocation is complete.
|
|
|
|
//
|
2002-10-28 04:24:49 +00:00
|
|
|
void SetRegForOperand(unsigned i, int regNum);
|
2002-10-28 04:30:20 +00:00
|
|
|
|
2002-07-08 22:38:45 +00:00
|
|
|
//
|
|
|
|
// Iterator to enumerate machine operands.
|
|
|
|
//
|
2002-02-05 06:02:59 +00:00
|
|
|
template<class MITy, class VTy>
|
2002-07-24 22:20:06 +00:00
|
|
|
class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
|
2002-02-05 06:02:59 +00:00
|
|
|
unsigned i;
|
|
|
|
MITy MI;
|
|
|
|
|
2002-10-28 04:30:20 +00:00
|
|
|
void skipToNextVal() {
|
2002-02-05 06:02:59 +00:00
|
|
|
while (i < MI->getNumOperands() &&
|
2002-10-28 04:30:20 +00:00
|
|
|
!((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
|
|
|
|
MI->getOperandType(i) == MachineOperand::MO_CCRegister)
|
2002-02-05 06:02:59 +00:00
|
|
|
&& MI->getOperand(i).getVRegValue() != 0))
|
|
|
|
++i;
|
|
|
|
}
|
|
|
|
|
|
|
|
inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
|
|
|
|
skipToNextVal();
|
|
|
|
}
|
|
|
|
|
|
|
|
public:
|
|
|
|
typedef ValOpIterator<MITy, VTy> _Self;
|
|
|
|
|
2002-08-14 16:54:11 +00:00
|
|
|
inline VTy operator*() const {
|
|
|
|
return MI->getOperand(i).getVRegValue();
|
2002-02-05 06:02:59 +00:00
|
|
|
}
|
|
|
|
|
2002-08-14 16:54:11 +00:00
|
|
|
const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
|
|
|
|
MachineOperand &getMachineOperand() { return MI->getOperand(i);}
|
|
|
|
|
2002-02-05 06:02:59 +00:00
|
|
|
inline VTy operator->() const { return operator*(); }
|
2002-08-14 16:54:11 +00:00
|
|
|
|
|
|
|
inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
|
|
|
|
inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
|
|
|
|
|
2002-02-05 06:02:59 +00:00
|
|
|
inline _Self& operator++() { i++; skipToNextVal(); return *this; }
|
|
|
|
inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
|
|
|
|
|
|
|
|
inline bool operator==(const _Self &y) const {
|
|
|
|
return i == y.i;
|
|
|
|
}
|
|
|
|
inline bool operator!=(const _Self &y) const {
|
|
|
|
return !operator==(y);
|
|
|
|
}
|
|
|
|
|
|
|
|
static _Self begin(MITy MI) {
|
|
|
|
return _Self(MI, 0);
|
|
|
|
}
|
|
|
|
static _Self end(MITy MI) {
|
|
|
|
return _Self(MI, MI->getNumOperands());
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
// define begin() and end()
|
|
|
|
val_op_iterator begin() { return val_op_iterator::begin(this); }
|
|
|
|
val_op_iterator end() { return val_op_iterator::end(this); }
|
|
|
|
|
|
|
|
const_val_op_iterator begin() const {
|
|
|
|
return const_val_op_iterator::begin(this);
|
|
|
|
}
|
|
|
|
const_val_op_iterator end() const {
|
|
|
|
return const_val_op_iterator::end(this);
|
|
|
|
}
|
2001-10-11 04:23:19 +00:00
|
|
|
};
|
2001-07-21 12:39:03 +00:00
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
2001-10-10 20:50:20 +00:00
|
|
|
// Debugging Support
|
2001-07-21 12:39:03 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
2002-10-28 04:24:49 +00:00
|
|
|
std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
|
2001-10-10 20:50:20 +00:00
|
|
|
|
2002-10-28 04:24:49 +00:00
|
|
|
std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
|
2001-07-21 12:39:03 +00:00
|
|
|
|
2002-10-28 04:24:49 +00:00
|
|
|
void PrintMachineInstructions(const Function *F);
|
2001-08-28 23:11:46 +00:00
|
|
|
|
2001-07-21 12:39:03 +00:00
|
|
|
#endif
|