2012-12-07 16:50:23 +00:00
|
|
|
//===- lib/MC/ARMELFStreamer.cpp - ELF Object Output for ARM --------------===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file assembles .s files and emits ARM ELF .o object files. Different
|
|
|
|
// from generic ELF streamer in emitting mapping symbols ($a, $t and $d) to
|
|
|
|
// delimit regions of data and code.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-04-16 12:02:21 +00:00
|
|
|
#include "ARMRegisterInfo.h"
|
|
|
|
#include "ARMUnwindOpAsm.h"
|
2013-12-19 05:17:58 +00:00
|
|
|
#include "llvm/ADT/StringExtras.h"
|
2012-12-08 10:45:24 +00:00
|
|
|
#include "llvm/ADT/Twine.h"
|
|
|
|
#include "llvm/MC/MCAsmBackend.h"
|
2013-12-19 05:17:58 +00:00
|
|
|
#include "llvm/MC/MCAsmInfo.h"
|
2012-12-07 16:50:23 +00:00
|
|
|
#include "llvm/MC/MCAssembler.h"
|
|
|
|
#include "llvm/MC/MCCodeEmitter.h"
|
|
|
|
#include "llvm/MC/MCContext.h"
|
|
|
|
#include "llvm/MC/MCELFStreamer.h"
|
|
|
|
#include "llvm/MC/MCExpr.h"
|
|
|
|
#include "llvm/MC/MCInst.h"
|
2013-10-08 13:08:17 +00:00
|
|
|
#include "llvm/MC/MCInstPrinter.h"
|
2014-04-27 17:10:46 +00:00
|
|
|
#include "llvm/MC/MCObjectFileInfo.h"
|
2012-12-07 16:50:23 +00:00
|
|
|
#include "llvm/MC/MCObjectStreamer.h"
|
2013-04-16 12:02:21 +00:00
|
|
|
#include "llvm/MC/MCRegisterInfo.h"
|
2012-12-07 16:50:23 +00:00
|
|
|
#include "llvm/MC/MCSection.h"
|
2012-12-08 10:45:24 +00:00
|
|
|
#include "llvm/MC/MCSectionELF.h"
|
|
|
|
#include "llvm/MC/MCStreamer.h"
|
2015-06-02 20:38:46 +00:00
|
|
|
#include "llvm/MC/MCSymbolELF.h"
|
2012-12-07 16:50:23 +00:00
|
|
|
#include "llvm/MC/MCValue.h"
|
2014-01-19 08:25:27 +00:00
|
|
|
#include "llvm/Support/ARMBuildAttributes.h"
|
2014-01-06 00:15:00 +00:00
|
|
|
#include "llvm/Support/ARMEHABI.h"
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
#include "llvm/Support/TargetParser.h"
|
2012-12-07 16:50:23 +00:00
|
|
|
#include "llvm/Support/Debug.h"
|
|
|
|
#include "llvm/Support/ELF.h"
|
2013-10-08 13:08:17 +00:00
|
|
|
#include "llvm/Support/FormattedStream.h"
|
2014-02-22 14:00:39 +00:00
|
|
|
#include "llvm/Support/LEB128.h"
|
2012-12-07 16:50:23 +00:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
#include <algorithm>
|
2012-12-07 16:50:23 +00:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2013-04-16 12:02:21 +00:00
|
|
|
static std::string GetAEABIUnwindPersonalityName(unsigned Index) {
|
2014-01-06 00:15:00 +00:00
|
|
|
assert(Index < ARM::EHABI::NUM_PERSONALITY_INDEX &&
|
|
|
|
"Invalid personality index");
|
2013-04-16 12:02:21 +00:00
|
|
|
return (Twine("__aeabi_unwind_cpp_pr") + Twine(Index)).str();
|
|
|
|
}
|
|
|
|
|
2012-12-07 16:50:23 +00:00
|
|
|
namespace {
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
class ARMELFStreamer;
|
|
|
|
|
|
|
|
class ARMTargetAsmStreamer : public ARMTargetStreamer {
|
|
|
|
formatted_raw_ostream &OS;
|
|
|
|
MCInstPrinter &InstPrinter;
|
2014-01-07 02:28:50 +00:00
|
|
|
bool IsVerboseAsm;
|
2013-10-08 13:08:17 +00:00
|
|
|
|
2014-03-10 03:19:03 +00:00
|
|
|
void emitFnStart() override;
|
|
|
|
void emitFnEnd() override;
|
|
|
|
void emitCantUnwind() override;
|
|
|
|
void emitPersonality(const MCSymbol *Personality) override;
|
|
|
|
void emitPersonalityIndex(unsigned Index) override;
|
|
|
|
void emitHandlerData() override;
|
|
|
|
void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
|
|
|
|
void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
|
|
|
|
void emitPad(int64_t Offset) override;
|
|
|
|
void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
|
|
|
|
bool isVector) override;
|
|
|
|
void emitUnwindRaw(int64_t Offset,
|
|
|
|
const SmallVectorImpl<uint8_t> &Opcodes) override;
|
|
|
|
|
|
|
|
void switchVendor(StringRef Vendor) override;
|
|
|
|
void emitAttribute(unsigned Attribute, unsigned Value) override;
|
|
|
|
void emitTextAttribute(unsigned Attribute, StringRef String) override;
|
|
|
|
void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
|
|
|
|
StringRef StrinValue) override;
|
|
|
|
void emitArch(unsigned Arch) override;
|
2015-02-26 18:07:35 +00:00
|
|
|
void emitArchExtension(unsigned ArchExt) override;
|
2014-03-10 03:19:03 +00:00
|
|
|
void emitObjectArch(unsigned Arch) override;
|
|
|
|
void emitFPU(unsigned FPU) override;
|
|
|
|
void emitInst(uint32_t Inst, char Suffix = '\0') override;
|
|
|
|
void finishAttributeSection() override;
|
|
|
|
|
|
|
|
void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
|
2014-04-27 20:23:58 +00:00
|
|
|
void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) override;
|
2014-01-30 04:02:47 +00:00
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
public:
|
2014-01-26 06:06:37 +00:00
|
|
|
ARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,
|
|
|
|
MCInstPrinter &InstPrinter, bool VerboseAsm);
|
2013-10-08 13:08:17 +00:00
|
|
|
};
|
|
|
|
|
2014-01-26 06:06:37 +00:00
|
|
|
ARMTargetAsmStreamer::ARMTargetAsmStreamer(MCStreamer &S,
|
|
|
|
formatted_raw_ostream &OS,
|
2014-01-07 02:28:50 +00:00
|
|
|
MCInstPrinter &InstPrinter,
|
|
|
|
bool VerboseAsm)
|
2014-01-26 06:06:37 +00:00
|
|
|
: ARMTargetStreamer(S), OS(OS), InstPrinter(InstPrinter),
|
|
|
|
IsVerboseAsm(VerboseAsm) {}
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMTargetAsmStreamer::emitFnStart() { OS << "\t.fnstart\n"; }
|
|
|
|
void ARMTargetAsmStreamer::emitFnEnd() { OS << "\t.fnend\n"; }
|
|
|
|
void ARMTargetAsmStreamer::emitCantUnwind() { OS << "\t.cantunwind\n"; }
|
|
|
|
void ARMTargetAsmStreamer::emitPersonality(const MCSymbol *Personality) {
|
|
|
|
OS << "\t.personality " << Personality->getName() << '\n';
|
|
|
|
}
|
2014-01-21 02:33:02 +00:00
|
|
|
void ARMTargetAsmStreamer::emitPersonalityIndex(unsigned Index) {
|
|
|
|
OS << "\t.personalityindex " << Index << '\n';
|
|
|
|
}
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMTargetAsmStreamer::emitHandlerData() { OS << "\t.handlerdata\n"; }
|
|
|
|
void ARMTargetAsmStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
|
|
|
|
int64_t Offset) {
|
|
|
|
OS << "\t.setfp\t";
|
|
|
|
InstPrinter.printRegName(OS, FpReg);
|
|
|
|
OS << ", ";
|
|
|
|
InstPrinter.printRegName(OS, SpReg);
|
|
|
|
if (Offset)
|
|
|
|
OS << ", #" << Offset;
|
|
|
|
OS << '\n';
|
|
|
|
}
|
2014-01-30 04:46:24 +00:00
|
|
|
void ARMTargetAsmStreamer::emitMovSP(unsigned Reg, int64_t Offset) {
|
|
|
|
assert((Reg != ARM::SP && Reg != ARM::PC) &&
|
|
|
|
"the operand of .movsp cannot be either sp or pc");
|
|
|
|
|
|
|
|
OS << "\t.movsp\t";
|
|
|
|
InstPrinter.printRegName(OS, Reg);
|
|
|
|
if (Offset)
|
|
|
|
OS << ", #" << Offset;
|
|
|
|
OS << '\n';
|
|
|
|
}
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMTargetAsmStreamer::emitPad(int64_t Offset) {
|
|
|
|
OS << "\t.pad\t#" << Offset << '\n';
|
|
|
|
}
|
|
|
|
void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
|
|
|
|
bool isVector) {
|
|
|
|
assert(RegList.size() && "RegList should not be empty");
|
|
|
|
if (isVector)
|
|
|
|
OS << "\t.vsave\t{";
|
|
|
|
else
|
|
|
|
OS << "\t.save\t{";
|
|
|
|
|
|
|
|
InstPrinter.printRegName(OS, RegList[0]);
|
|
|
|
|
|
|
|
for (unsigned i = 1, e = RegList.size(); i != e; ++i) {
|
|
|
|
OS << ", ";
|
|
|
|
InstPrinter.printRegName(OS, RegList[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
OS << "}\n";
|
|
|
|
}
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
void ARMTargetAsmStreamer::switchVendor(StringRef Vendor) {
|
|
|
|
}
|
|
|
|
void ARMTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
|
2014-01-07 02:28:50 +00:00
|
|
|
OS << "\t.eabi_attribute\t" << Attribute << ", " << Twine(Value);
|
|
|
|
if (IsVerboseAsm) {
|
|
|
|
StringRef Name = ARMBuildAttrs::AttrTypeAsString(Attribute);
|
|
|
|
if (!Name.empty())
|
|
|
|
OS << "\t@ " << Name;
|
|
|
|
}
|
|
|
|
OS << "\n";
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
|
|
|
void ARMTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
|
|
|
|
StringRef String) {
|
|
|
|
switch (Attribute) {
|
|
|
|
case ARMBuildAttrs::CPU_name:
|
2014-01-07 02:28:42 +00:00
|
|
|
OS << "\t.cpu\t" << String.lower();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
OS << "\t.eabi_attribute\t" << Attribute << ", \"" << String << "\"";
|
2014-01-07 02:28:50 +00:00
|
|
|
if (IsVerboseAsm) {
|
|
|
|
StringRef Name = ARMBuildAttrs::AttrTypeAsString(Attribute);
|
|
|
|
if (!Name.empty())
|
|
|
|
OS << "\t@ " << Name;
|
|
|
|
}
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
break;
|
|
|
|
}
|
2014-01-07 02:28:42 +00:00
|
|
|
OS << "\n";
|
|
|
|
}
|
|
|
|
void ARMTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
|
|
|
|
unsigned IntValue,
|
|
|
|
StringRef StringValue) {
|
|
|
|
switch (Attribute) {
|
|
|
|
default: llvm_unreachable("unsupported multi-value attribute in asm mode");
|
|
|
|
case ARMBuildAttrs::compatibility:
|
|
|
|
OS << "\t.eabi_attribute\t" << Attribute << ", " << IntValue;
|
|
|
|
if (!StringValue.empty())
|
|
|
|
OS << ", \"" << StringValue << "\"";
|
2014-01-07 02:28:50 +00:00
|
|
|
if (IsVerboseAsm)
|
|
|
|
OS << "\t@ " << ARMBuildAttrs::AttrTypeAsString(Attribute);
|
2014-01-07 02:28:42 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
OS << "\n";
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
2013-12-11 17:16:25 +00:00
|
|
|
void ARMTargetAsmStreamer::emitArch(unsigned Arch) {
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
OS << "\t.arch\t" << ARMTargetParser::getArchName(Arch) << "\n";
|
2013-12-11 17:16:25 +00:00
|
|
|
}
|
2015-02-26 18:07:35 +00:00
|
|
|
void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) {
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
OS << "\t.arch_extension\t" << ARMTargetParser::getArchExtName(ArchExt) << "\n";
|
2015-02-26 18:07:35 +00:00
|
|
|
}
|
2014-01-30 04:46:41 +00:00
|
|
|
void ARMTargetAsmStreamer::emitObjectArch(unsigned Arch) {
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
OS << "\t.object_arch\t" << ARMTargetParser::getArchName(Arch) << '\n';
|
2014-01-30 04:46:41 +00:00
|
|
|
}
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
void ARMTargetAsmStreamer::emitFPU(unsigned FPU) {
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
OS << "\t.fpu\t" << ARMTargetParser::getFPUName(FPU) << "\n";
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
|
|
|
void ARMTargetAsmStreamer::finishAttributeSection() {
|
|
|
|
}
|
2014-01-30 04:02:47 +00:00
|
|
|
void
|
|
|
|
ARMTargetAsmStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *S) {
|
|
|
|
OS << "\t.tlsdescseq\t" << S->getSymbol().getName();
|
|
|
|
}
|
2013-10-08 13:08:17 +00:00
|
|
|
|
2014-04-27 20:23:58 +00:00
|
|
|
void ARMTargetAsmStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {
|
2015-06-09 00:31:39 +00:00
|
|
|
const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
|
|
|
|
|
|
|
|
OS << "\t.thumb_set\t";
|
|
|
|
Symbol->print(OS, MAI);
|
|
|
|
OS << ", ";
|
|
|
|
Value->print(OS, MAI);
|
|
|
|
OS << '\n';
|
2014-04-27 20:23:58 +00:00
|
|
|
}
|
|
|
|
|
2013-12-19 05:17:58 +00:00
|
|
|
void ARMTargetAsmStreamer::emitInst(uint32_t Inst, char Suffix) {
|
|
|
|
OS << "\t.inst";
|
|
|
|
if (Suffix)
|
|
|
|
OS << "." << Suffix;
|
2015-05-23 16:39:10 +00:00
|
|
|
OS << "\t0x" << Twine::utohexstr(Inst) << "\n";
|
2013-12-19 05:17:58 +00:00
|
|
|
}
|
|
|
|
|
2014-01-21 02:33:10 +00:00
|
|
|
void ARMTargetAsmStreamer::emitUnwindRaw(int64_t Offset,
|
|
|
|
const SmallVectorImpl<uint8_t> &Opcodes) {
|
|
|
|
OS << "\t.unwind_raw " << Offset;
|
|
|
|
for (SmallVectorImpl<uint8_t>::const_iterator OCI = Opcodes.begin(),
|
|
|
|
OCE = Opcodes.end();
|
|
|
|
OCI != OCE; ++OCI)
|
2015-05-23 16:39:10 +00:00
|
|
|
OS << ", 0x" << Twine::utohexstr(*OCI);
|
2014-01-21 02:33:10 +00:00
|
|
|
OS << '\n';
|
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
class ARMTargetELFStreamer : public ARMTargetStreamer {
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
private:
|
|
|
|
// This structure holds all attributes, accounting for
|
|
|
|
// their string/numeric value, so we can later emmit them
|
|
|
|
// in declaration order, keeping all in the same vector
|
|
|
|
struct AttributeItem {
|
|
|
|
enum {
|
|
|
|
HiddenAttribute = 0,
|
|
|
|
NumericAttribute,
|
2014-01-07 02:28:42 +00:00
|
|
|
TextAttribute,
|
|
|
|
NumericAndTextAttributes
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
} Type;
|
|
|
|
unsigned Tag;
|
|
|
|
unsigned IntValue;
|
|
|
|
StringRef StringValue;
|
|
|
|
|
|
|
|
static bool LessTag(const AttributeItem &LHS, const AttributeItem &RHS) {
|
2015-01-05 13:12:17 +00:00
|
|
|
// The conformance tag must be emitted first when serialised
|
|
|
|
// into an object file. Specifically, the addenda to the ARM ABI
|
|
|
|
// states that (2.3.7.4):
|
|
|
|
//
|
|
|
|
// "To simplify recognition by consumers in the common case of
|
|
|
|
// claiming conformity for the whole file, this tag should be
|
|
|
|
// emitted first in a file-scope sub-subsection of the first
|
|
|
|
// public subsection of the attributes section."
|
|
|
|
//
|
|
|
|
// So it is special-cased in this comparison predicate when the
|
|
|
|
// attributes are sorted in finishAttributeSection().
|
|
|
|
return (RHS.Tag != ARMBuildAttrs::conformance) &&
|
|
|
|
((LHS.Tag == ARMBuildAttrs::conformance) || (LHS.Tag < RHS.Tag));
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
StringRef CurrentVendor;
|
|
|
|
unsigned FPU;
|
2013-12-11 17:16:25 +00:00
|
|
|
unsigned Arch;
|
2014-01-30 04:46:41 +00:00
|
|
|
unsigned EmittedArch;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
SmallVector<AttributeItem, 64> Contents;
|
|
|
|
|
2015-05-21 19:20:38 +00:00
|
|
|
MCSection *AttributeSection;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
|
|
|
|
AttributeItem *getAttributeItem(unsigned Attribute) {
|
|
|
|
for (size_t i = 0; i < Contents.size(); ++i)
|
|
|
|
if (Contents[i].Tag == Attribute)
|
|
|
|
return &Contents[i];
|
2014-04-25 05:30:21 +00:00
|
|
|
return nullptr;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void setAttributeItem(unsigned Attribute, unsigned Value,
|
|
|
|
bool OverwriteExisting) {
|
|
|
|
// Look for existing attribute item
|
|
|
|
if (AttributeItem *Item = getAttributeItem(Attribute)) {
|
|
|
|
if (!OverwriteExisting)
|
|
|
|
return;
|
2014-01-19 08:25:41 +00:00
|
|
|
Item->Type = AttributeItem::NumericAttribute;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
Item->IntValue = Value;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create new attribute item
|
|
|
|
AttributeItem Item = {
|
|
|
|
AttributeItem::NumericAttribute,
|
|
|
|
Attribute,
|
|
|
|
Value,
|
|
|
|
StringRef("")
|
|
|
|
};
|
|
|
|
Contents.push_back(Item);
|
|
|
|
}
|
|
|
|
|
|
|
|
void setAttributeItem(unsigned Attribute, StringRef Value,
|
|
|
|
bool OverwriteExisting) {
|
|
|
|
// Look for existing attribute item
|
|
|
|
if (AttributeItem *Item = getAttributeItem(Attribute)) {
|
|
|
|
if (!OverwriteExisting)
|
|
|
|
return;
|
2014-01-19 08:25:41 +00:00
|
|
|
Item->Type = AttributeItem::TextAttribute;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
Item->StringValue = Value;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create new attribute item
|
|
|
|
AttributeItem Item = {
|
|
|
|
AttributeItem::TextAttribute,
|
|
|
|
Attribute,
|
|
|
|
0,
|
|
|
|
Value
|
|
|
|
};
|
|
|
|
Contents.push_back(Item);
|
|
|
|
}
|
|
|
|
|
2014-01-07 02:28:42 +00:00
|
|
|
void setAttributeItems(unsigned Attribute, unsigned IntValue,
|
|
|
|
StringRef StringValue, bool OverwriteExisting) {
|
|
|
|
// Look for existing attribute item
|
|
|
|
if (AttributeItem *Item = getAttributeItem(Attribute)) {
|
|
|
|
if (!OverwriteExisting)
|
|
|
|
return;
|
2014-01-19 08:25:41 +00:00
|
|
|
Item->Type = AttributeItem::NumericAndTextAttributes;
|
2014-01-07 02:28:42 +00:00
|
|
|
Item->IntValue = IntValue;
|
|
|
|
Item->StringValue = StringValue;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Create new attribute item
|
|
|
|
AttributeItem Item = {
|
|
|
|
AttributeItem::NumericAndTextAttributes,
|
|
|
|
Attribute,
|
|
|
|
IntValue,
|
|
|
|
StringValue
|
|
|
|
};
|
|
|
|
Contents.push_back(Item);
|
|
|
|
}
|
|
|
|
|
2013-12-11 17:16:25 +00:00
|
|
|
void emitArchDefaultAttributes();
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
void emitFPUDefaultAttributes();
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
ARMELFStreamer &getStreamer();
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
|
2014-03-10 03:19:03 +00:00
|
|
|
void emitFnStart() override;
|
|
|
|
void emitFnEnd() override;
|
|
|
|
void emitCantUnwind() override;
|
|
|
|
void emitPersonality(const MCSymbol *Personality) override;
|
|
|
|
void emitPersonalityIndex(unsigned Index) override;
|
|
|
|
void emitHandlerData() override;
|
|
|
|
void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset = 0) override;
|
|
|
|
void emitMovSP(unsigned Reg, int64_t Offset = 0) override;
|
|
|
|
void emitPad(int64_t Offset) override;
|
|
|
|
void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
|
|
|
|
bool isVector) override;
|
|
|
|
void emitUnwindRaw(int64_t Offset,
|
|
|
|
const SmallVectorImpl<uint8_t> &Opcodes) override;
|
|
|
|
|
|
|
|
void switchVendor(StringRef Vendor) override;
|
|
|
|
void emitAttribute(unsigned Attribute, unsigned Value) override;
|
|
|
|
void emitTextAttribute(unsigned Attribute, StringRef String) override;
|
|
|
|
void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
|
|
|
|
StringRef StringValue) override;
|
|
|
|
void emitArch(unsigned Arch) override;
|
|
|
|
void emitObjectArch(unsigned Arch) override;
|
|
|
|
void emitFPU(unsigned FPU) override;
|
|
|
|
void emitInst(uint32_t Inst, char Suffix = '\0') override;
|
|
|
|
void finishAttributeSection() override;
|
2014-04-27 17:10:46 +00:00
|
|
|
void emitLabel(MCSymbol *Symbol) override;
|
2014-03-10 03:19:03 +00:00
|
|
|
|
|
|
|
void AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) override;
|
2014-04-27 20:23:58 +00:00
|
|
|
void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) override;
|
2014-01-30 04:02:47 +00:00
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
size_t calculateContentSize() const;
|
|
|
|
|
|
|
|
public:
|
2014-01-26 06:06:37 +00:00
|
|
|
ARMTargetELFStreamer(MCStreamer &S)
|
2015-05-12 10:33:58 +00:00
|
|
|
: ARMTargetStreamer(S), CurrentVendor("aeabi"), FPU(ARM::FK_INVALID),
|
|
|
|
Arch(ARM::AK_INVALID), EmittedArch(ARM::AK_INVALID),
|
2014-04-25 05:30:21 +00:00
|
|
|
AttributeSection(nullptr) {}
|
2013-10-08 13:08:17 +00:00
|
|
|
};
|
|
|
|
|
2012-12-07 16:50:23 +00:00
|
|
|
/// Extend the generic ELFStreamer class so that it can emit mapping symbols at
|
|
|
|
/// the appropriate points in the object files. These symbols are defined in the
|
|
|
|
/// ARM ELF ABI: infocenter.arm.com/help/topic/com.arm.../IHI0044D_aaelf.pdf.
|
|
|
|
///
|
|
|
|
/// In brief: $a, $t or $d should be emitted at the start of each contiguous
|
|
|
|
/// region of ARM code, Thumb code or data in a section. In practice, this
|
|
|
|
/// emission does not rely on explicit assembler directives but on inherent
|
|
|
|
/// properties of the directives doing the emission (e.g. ".byte" is data, "add
|
|
|
|
/// r0, r0, r0" an instruction).
|
|
|
|
///
|
|
|
|
/// As a result this system is orthogonal to the DataRegion infrastructure used
|
|
|
|
/// by MachO. Beware!
|
|
|
|
class ARMELFStreamer : public MCELFStreamer {
|
|
|
|
public:
|
2013-10-08 13:08:17 +00:00
|
|
|
friend class ARMTargetELFStreamer;
|
|
|
|
|
2015-04-14 22:14:34 +00:00
|
|
|
ARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS,
|
2014-01-26 06:06:37 +00:00
|
|
|
MCCodeEmitter *Emitter, bool IsThumb)
|
|
|
|
: MCELFStreamer(Context, TAB, OS, Emitter), IsThumb(IsThumb),
|
|
|
|
MappingSymbolCounter(0), LastEMS(EMS_None) {
|
2013-04-16 12:02:21 +00:00
|
|
|
Reset();
|
|
|
|
}
|
2012-12-07 16:50:23 +00:00
|
|
|
|
|
|
|
~ARMELFStreamer() {}
|
|
|
|
|
2014-03-10 03:19:03 +00:00
|
|
|
void FinishImpl() override;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
|
2013-01-30 15:39:04 +00:00
|
|
|
// ARM exception handling directives
|
2013-10-08 13:08:17 +00:00
|
|
|
void emitFnStart();
|
|
|
|
void emitFnEnd();
|
|
|
|
void emitCantUnwind();
|
|
|
|
void emitPersonality(const MCSymbol *Per);
|
2014-01-21 02:33:02 +00:00
|
|
|
void emitPersonalityIndex(unsigned index);
|
2013-10-08 13:08:17 +00:00
|
|
|
void emitHandlerData();
|
|
|
|
void emitSetFP(unsigned NewFpReg, unsigned NewSpReg, int64_t Offset = 0);
|
2014-01-30 04:46:24 +00:00
|
|
|
void emitMovSP(unsigned Reg, int64_t Offset = 0);
|
2013-10-08 13:08:17 +00:00
|
|
|
void emitPad(int64_t Offset);
|
|
|
|
void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
|
2014-01-21 02:33:10 +00:00
|
|
|
void emitUnwindRaw(int64_t Offset, const SmallVectorImpl<uint8_t> &Opcodes);
|
2013-01-30 15:39:04 +00:00
|
|
|
|
2015-05-21 19:20:38 +00:00
|
|
|
void ChangeSection(MCSection *Section, const MCExpr *Subsection) override {
|
2012-12-07 16:50:23 +00:00
|
|
|
// We have to keep track of the mapping symbol state of any sections we
|
|
|
|
// use. Each one should start off as EMS_None, which is provided as the
|
|
|
|
// default constructor by DenseMap::lookup.
|
2013-04-17 21:18:16 +00:00
|
|
|
LastMappingSymbols[getPreviousSection().first] = LastEMS;
|
2012-12-07 16:50:23 +00:00
|
|
|
LastEMS = LastMappingSymbols.lookup(Section);
|
|
|
|
|
2013-04-17 21:18:16 +00:00
|
|
|
MCELFStreamer::ChangeSection(Section, Subsection);
|
2012-12-07 16:50:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// This function is the one used to emit instruction data into the ELF
|
|
|
|
/// streamer. We override it to add the appropriate mapping symbol if
|
|
|
|
/// necessary.
|
2014-03-10 03:19:03 +00:00
|
|
|
void EmitInstruction(const MCInst& Inst,
|
|
|
|
const MCSubtargetInfo &STI) override {
|
2012-12-07 16:50:23 +00:00
|
|
|
if (IsThumb)
|
|
|
|
EmitThumbMappingSymbol();
|
|
|
|
else
|
|
|
|
EmitARMMappingSymbol();
|
|
|
|
|
2014-01-28 23:12:42 +00:00
|
|
|
MCELFStreamer::EmitInstruction(Inst, STI);
|
2012-12-07 16:50:23 +00:00
|
|
|
}
|
|
|
|
|
2014-03-10 03:22:59 +00:00
|
|
|
void emitInst(uint32_t Inst, char Suffix) {
|
2013-12-19 05:17:58 +00:00
|
|
|
unsigned Size;
|
|
|
|
char Buffer[4];
|
|
|
|
const bool LittleEndian = getContext().getAsmInfo()->isLittleEndian();
|
|
|
|
|
|
|
|
switch (Suffix) {
|
|
|
|
case '\0':
|
|
|
|
Size = 4;
|
|
|
|
|
|
|
|
assert(!IsThumb);
|
|
|
|
EmitARMMappingSymbol();
|
|
|
|
for (unsigned II = 0, IE = Size; II != IE; II++) {
|
|
|
|
const unsigned I = LittleEndian ? (Size - II - 1) : II;
|
|
|
|
Buffer[Size - II - 1] = uint8_t(Inst >> I * CHAR_BIT);
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
case 'n':
|
|
|
|
case 'w':
|
|
|
|
Size = (Suffix == 'n' ? 2 : 4);
|
|
|
|
|
|
|
|
assert(IsThumb);
|
|
|
|
EmitThumbMappingSymbol();
|
|
|
|
for (unsigned II = 0, IE = Size; II != IE; II = II + 2) {
|
|
|
|
const unsigned I0 = LittleEndian ? II + 0 : (Size - II - 1);
|
|
|
|
const unsigned I1 = LittleEndian ? II + 1 : (Size - II - 2);
|
|
|
|
Buffer[Size - II - 2] = uint8_t(Inst >> I0 * CHAR_BIT);
|
|
|
|
Buffer[Size - II - 1] = uint8_t(Inst >> I1 * CHAR_BIT);
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Invalid Suffix");
|
|
|
|
}
|
|
|
|
|
|
|
|
MCELFStreamer::EmitBytes(StringRef(Buffer, Size));
|
|
|
|
}
|
|
|
|
|
2012-12-07 16:50:23 +00:00
|
|
|
/// This is one of the functions used to emit data into an ELF section, so the
|
|
|
|
/// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
|
|
|
|
/// necessary.
|
2014-03-10 03:19:03 +00:00
|
|
|
void EmitBytes(StringRef Data) override {
|
2012-12-07 16:50:23 +00:00
|
|
|
EmitDataMappingSymbol();
|
2013-07-02 15:49:13 +00:00
|
|
|
MCELFStreamer::EmitBytes(Data);
|
2012-12-07 16:50:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/// This is one of the functions used to emit data into an ELF section, so the
|
|
|
|
/// ARM streamer overrides it to add the appropriate mapping symbol ($d) if
|
|
|
|
/// necessary.
|
2014-04-22 17:27:29 +00:00
|
|
|
void EmitValueImpl(const MCExpr *Value, unsigned Size,
|
|
|
|
const SMLoc &Loc) override {
|
2015-01-11 04:39:18 +00:00
|
|
|
if (const MCSymbolRefExpr *SRE = dyn_cast_or_null<MCSymbolRefExpr>(Value))
|
|
|
|
if (SRE->getKind() == MCSymbolRefExpr::VK_ARM_SBREL && !(Size == 4))
|
2015-05-18 18:43:14 +00:00
|
|
|
getContext().reportFatalError(Loc, "relocated expression must be 32-bit");
|
2015-01-11 04:39:18 +00:00
|
|
|
|
2012-12-07 16:50:23 +00:00
|
|
|
EmitDataMappingSymbol();
|
2013-07-02 15:49:13 +00:00
|
|
|
MCELFStreamer::EmitValueImpl(Value, Size);
|
2012-12-07 16:50:23 +00:00
|
|
|
}
|
|
|
|
|
2014-03-10 03:19:03 +00:00
|
|
|
void EmitAssemblerFlag(MCAssemblerFlag Flag) override {
|
2012-12-07 16:50:23 +00:00
|
|
|
MCELFStreamer::EmitAssemblerFlag(Flag);
|
|
|
|
|
|
|
|
switch (Flag) {
|
|
|
|
case MCAF_SyntaxUnified:
|
|
|
|
return; // no-op here.
|
|
|
|
case MCAF_Code16:
|
|
|
|
IsThumb = true;
|
|
|
|
return; // Change to Thumb mode
|
|
|
|
case MCAF_Code32:
|
|
|
|
IsThumb = false;
|
|
|
|
return; // Change to ARM mode
|
|
|
|
case MCAF_Code64:
|
|
|
|
return;
|
|
|
|
case MCAF_SubsectionsViaSymbols:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
enum ElfMappingSymbol {
|
|
|
|
EMS_None,
|
|
|
|
EMS_ARM,
|
|
|
|
EMS_Thumb,
|
|
|
|
EMS_Data
|
|
|
|
};
|
|
|
|
|
|
|
|
void EmitDataMappingSymbol() {
|
|
|
|
if (LastEMS == EMS_Data) return;
|
|
|
|
EmitMappingSymbol("$d");
|
|
|
|
LastEMS = EMS_Data;
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitThumbMappingSymbol() {
|
|
|
|
if (LastEMS == EMS_Thumb) return;
|
|
|
|
EmitMappingSymbol("$t");
|
|
|
|
LastEMS = EMS_Thumb;
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitARMMappingSymbol() {
|
|
|
|
if (LastEMS == EMS_ARM) return;
|
|
|
|
EmitMappingSymbol("$a");
|
|
|
|
LastEMS = EMS_ARM;
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitMappingSymbol(StringRef Name) {
|
2015-06-02 20:38:46 +00:00
|
|
|
auto *Symbol = cast<MCSymbolELF>(getContext().getOrCreateSymbol(
|
|
|
|
Name + "." + Twine(MappingSymbolCounter++)));
|
2015-06-26 11:31:13 +00:00
|
|
|
EmitLabel(Symbol);
|
2012-12-07 16:50:23 +00:00
|
|
|
|
2015-06-02 20:38:46 +00:00
|
|
|
Symbol->setType(ELF::STT_NOTYPE);
|
|
|
|
Symbol->setBinding(ELF::STB_LOCAL);
|
2015-05-29 21:45:01 +00:00
|
|
|
Symbol->setExternal(false);
|
2012-12-07 16:50:23 +00:00
|
|
|
}
|
|
|
|
|
2014-03-10 03:19:03 +00:00
|
|
|
void EmitThumbFunc(MCSymbol *Func) override {
|
2012-12-07 16:50:23 +00:00
|
|
|
getAssembler().setIsThumbFunc(Func);
|
2014-04-29 12:46:50 +00:00
|
|
|
EmitSymbolAttribute(Func, MCSA_ELF_TypeFunction);
|
2012-12-07 16:50:23 +00:00
|
|
|
}
|
|
|
|
|
2013-01-30 15:39:04 +00:00
|
|
|
// Helper functions for ARM exception handling directives
|
|
|
|
void Reset();
|
|
|
|
|
|
|
|
void EmitPersonalityFixup(StringRef Name);
|
2013-06-09 12:22:30 +00:00
|
|
|
void FlushPendingOffset();
|
2013-07-02 12:43:27 +00:00
|
|
|
void FlushUnwindOpcodes(bool NoHandlerData);
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
void SwitchToEHSection(const char *Prefix, unsigned Type, unsigned Flags,
|
|
|
|
SectionKind Kind, const MCSymbol &Fn);
|
|
|
|
void SwitchToExTabSection(const MCSymbol &FnStart);
|
|
|
|
void SwitchToExIdxSection(const MCSymbol &FnStart);
|
2012-12-07 16:50:23 +00:00
|
|
|
|
2014-01-30 04:02:47 +00:00
|
|
|
void EmitFixup(const MCExpr *Expr, MCFixupKind Kind);
|
|
|
|
|
2012-12-07 16:50:23 +00:00
|
|
|
bool IsThumb;
|
|
|
|
int64_t MappingSymbolCounter;
|
|
|
|
|
|
|
|
DenseMap<const MCSection *, ElfMappingSymbol> LastMappingSymbols;
|
|
|
|
ElfMappingSymbol LastEMS;
|
|
|
|
|
2013-01-30 15:39:04 +00:00
|
|
|
// ARM Exception Handling Frame Information
|
|
|
|
MCSymbol *ExTab;
|
|
|
|
MCSymbol *FnStart;
|
|
|
|
const MCSymbol *Personality;
|
2013-06-09 12:22:30 +00:00
|
|
|
unsigned PersonalityIndex;
|
|
|
|
unsigned FPReg; // Frame pointer register
|
|
|
|
int64_t FPOffset; // Offset: (final frame pointer) - (initial $sp)
|
|
|
|
int64_t SPOffset; // Offset: (final $sp) - (initial $sp)
|
|
|
|
int64_t PendingOffset; // Offset: (final $sp) - (emitted $sp)
|
2013-04-16 12:02:21 +00:00
|
|
|
bool UsedFP;
|
2013-01-30 15:39:04 +00:00
|
|
|
bool CantUnwind;
|
2013-06-09 12:22:30 +00:00
|
|
|
SmallVector<uint8_t, 64> Opcodes;
|
2013-04-16 12:02:21 +00:00
|
|
|
UnwindOpcodeAssembler UnwindOpAsm;
|
2012-12-07 16:50:23 +00:00
|
|
|
};
|
2013-04-16 12:02:21 +00:00
|
|
|
} // end anonymous namespace
|
2012-12-07 16:50:23 +00:00
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
ARMELFStreamer &ARMTargetELFStreamer::getStreamer() {
|
2014-01-26 06:06:37 +00:00
|
|
|
return static_cast<ARMELFStreamer &>(Streamer);
|
2013-10-08 13:08:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void ARMTargetELFStreamer::emitFnStart() { getStreamer().emitFnStart(); }
|
|
|
|
void ARMTargetELFStreamer::emitFnEnd() { getStreamer().emitFnEnd(); }
|
|
|
|
void ARMTargetELFStreamer::emitCantUnwind() { getStreamer().emitCantUnwind(); }
|
|
|
|
void ARMTargetELFStreamer::emitPersonality(const MCSymbol *Personality) {
|
|
|
|
getStreamer().emitPersonality(Personality);
|
|
|
|
}
|
2014-01-21 02:33:02 +00:00
|
|
|
void ARMTargetELFStreamer::emitPersonalityIndex(unsigned Index) {
|
|
|
|
getStreamer().emitPersonalityIndex(Index);
|
|
|
|
}
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMTargetELFStreamer::emitHandlerData() {
|
|
|
|
getStreamer().emitHandlerData();
|
|
|
|
}
|
|
|
|
void ARMTargetELFStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
|
|
|
|
int64_t Offset) {
|
|
|
|
getStreamer().emitSetFP(FpReg, SpReg, Offset);
|
|
|
|
}
|
2014-01-30 04:46:24 +00:00
|
|
|
void ARMTargetELFStreamer::emitMovSP(unsigned Reg, int64_t Offset) {
|
|
|
|
getStreamer().emitMovSP(Reg, Offset);
|
|
|
|
}
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMTargetELFStreamer::emitPad(int64_t Offset) {
|
|
|
|
getStreamer().emitPad(Offset);
|
|
|
|
}
|
|
|
|
void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
|
|
|
|
bool isVector) {
|
|
|
|
getStreamer().emitRegSave(RegList, isVector);
|
|
|
|
}
|
2014-01-21 02:33:10 +00:00
|
|
|
void ARMTargetELFStreamer::emitUnwindRaw(int64_t Offset,
|
|
|
|
const SmallVectorImpl<uint8_t> &Opcodes) {
|
|
|
|
getStreamer().emitUnwindRaw(Offset, Opcodes);
|
|
|
|
}
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
void ARMTargetELFStreamer::switchVendor(StringRef Vendor) {
|
|
|
|
assert(!Vendor.empty() && "Vendor cannot be empty.");
|
|
|
|
|
|
|
|
if (CurrentVendor == Vendor)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!CurrentVendor.empty())
|
|
|
|
finishAttributeSection();
|
|
|
|
|
|
|
|
assert(Contents.empty() &&
|
|
|
|
".ARM.attributes should be flushed before changing vendor");
|
|
|
|
CurrentVendor = Vendor;
|
|
|
|
|
|
|
|
}
|
|
|
|
void ARMTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
|
|
|
|
setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true);
|
|
|
|
}
|
|
|
|
void ARMTargetELFStreamer::emitTextAttribute(unsigned Attribute,
|
|
|
|
StringRef Value) {
|
|
|
|
setAttributeItem(Attribute, Value, /* OverwriteExisting= */ true);
|
|
|
|
}
|
2014-01-07 02:28:42 +00:00
|
|
|
void ARMTargetELFStreamer::emitIntTextAttribute(unsigned Attribute,
|
|
|
|
unsigned IntValue,
|
|
|
|
StringRef StringValue) {
|
|
|
|
setAttributeItems(Attribute, IntValue, StringValue,
|
|
|
|
/* OverwriteExisting= */ true);
|
|
|
|
}
|
2013-12-11 17:16:25 +00:00
|
|
|
void ARMTargetELFStreamer::emitArch(unsigned Value) {
|
|
|
|
Arch = Value;
|
|
|
|
}
|
2014-01-30 04:46:41 +00:00
|
|
|
void ARMTargetELFStreamer::emitObjectArch(unsigned Value) {
|
|
|
|
EmittedArch = Value;
|
|
|
|
}
|
2013-12-11 17:16:25 +00:00
|
|
|
void ARMTargetELFStreamer::emitArchDefaultAttributes() {
|
|
|
|
using namespace ARMBuildAttrs;
|
2014-01-30 04:46:41 +00:00
|
|
|
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
setAttributeItem(CPU_name,
|
2015-05-27 18:15:37 +00:00
|
|
|
ARMTargetParser::getCPUAttr(Arch),
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
false);
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
if (EmittedArch == ARM::AK_INVALID)
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
setAttributeItem(CPU_arch,
|
2015-05-27 18:15:37 +00:00
|
|
|
ARMTargetParser::getArchAttr(Arch),
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
false);
|
2014-01-30 04:46:41 +00:00
|
|
|
else
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
setAttributeItem(CPU_arch,
|
2015-05-27 18:15:37 +00:00
|
|
|
ARMTargetParser::getArchAttr(EmittedArch),
|
TargetParser: FPU/ARCH/EXT parsing refactory - NFC
This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.
Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).
The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.
The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.
The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:
* A bogus neon-vfpv3 alias (neon defaults to vfp3)
* armv5/v6
* {fp4/fp5}-{sp/dp}-d16
Next steps:
* Port Clang's ARCH/EXT parsing to use this library.
* Create a TableGen back-end to generate this information.
* Run this TableGen process regardless of which back-ends are built.
* Expose more information and rename it to TargetDescription.
* Continue re-factoring Clang to use as much of it as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 21:04:27 +00:00
|
|
|
false);
|
2013-12-11 17:16:25 +00:00
|
|
|
|
|
|
|
switch (Arch) {
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV2:
|
|
|
|
case ARM::AK_ARMV2A:
|
|
|
|
case ARM::AK_ARMV3:
|
|
|
|
case ARM::AK_ARMV3M:
|
|
|
|
case ARM::AK_ARMV4:
|
|
|
|
case ARM::AK_ARMV5:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV4T:
|
|
|
|
case ARM::AK_ARMV5T:
|
|
|
|
case ARM::AK_ARMV5TE:
|
|
|
|
case ARM::AK_ARMV6:
|
|
|
|
case ARM::AK_ARMV6J:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV6T2:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV6K:
|
|
|
|
case ARM::AK_ARMV6Z:
|
|
|
|
case ARM::AK_ARMV6ZK:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(Virtualization_use, AllowTZ, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV6M:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV7:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV7A:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
|
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV7R:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(CPU_arch_profile, RealTimeProfile, false);
|
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV7M:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(CPU_arch_profile, MicroControllerProfile, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_ARMV8A:
|
|
|
|
case ARM::AK_ARMV8_1A:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(CPU_arch_profile, ApplicationProfile, false);
|
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, AllowThumb32, false);
|
|
|
|
setAttributeItem(MPextension_use, Allowed, false);
|
|
|
|
setAttributeItem(Virtualization_use, AllowTZVirtualization, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_IWMMXT:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(WMMX_arch, AllowWMMXv1, false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::AK_IWMMXT2:
|
2013-12-11 17:16:25 +00:00
|
|
|
setAttributeItem(ARM_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(THUMB_ISA_use, Allowed, false);
|
|
|
|
setAttributeItem(WMMX_arch, AllowWMMXv2, false);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
report_fatal_error("Unknown Arch: " + Twine(Arch));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
void ARMTargetELFStreamer::emitFPU(unsigned Value) {
|
|
|
|
FPU = Value;
|
|
|
|
}
|
|
|
|
void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
|
|
|
|
switch (FPU) {
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_VFP:
|
|
|
|
case ARM::FK_VFPV2:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPv2,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_VFPV3:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPv3A,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-06-29 09:32:29 +00:00
|
|
|
case ARM::FK_VFPV3_FP16:
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
|
|
|
ARMBuildAttrs::AllowFPv3A,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_HP_extension,
|
|
|
|
ARMBuildAttrs::AllowHPFP,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_VFPV3_D16:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPv3B,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-06-29 09:32:29 +00:00
|
|
|
case ARM::FK_VFPV3_D16_FP16:
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
|
|
|
ARMBuildAttrs::AllowFPv3B,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_HP_extension,
|
|
|
|
ARMBuildAttrs::AllowHPFP,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case ARM::FK_VFPV3XD:
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
|
|
|
ARMBuildAttrs::AllowFPv3B,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
case ARM::FK_VFPV3XD_FP16:
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
|
|
|
ARMBuildAttrs::AllowFPv3B,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_HP_extension,
|
|
|
|
ARMBuildAttrs::AllowHPFP,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_VFPV4:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPv4A,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-06-05 13:31:19 +00:00
|
|
|
// ABI_HardFP_use is handled in ARMAsmPrinter, so _SP_D16 is treated the same
|
|
|
|
// as _D16 here.
|
|
|
|
case ARM::FK_FPV4_SP_D16:
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_VFPV4_D16:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPv4B,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_FP_ARMV8:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPARMv8A,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2014-10-01 09:02:17 +00:00
|
|
|
// FPV5_D16 is identical to FP_ARMV8 except for the number of D registers, so
|
|
|
|
// uses the FP_ARMV8_D16 build attribute.
|
2015-06-05 13:31:19 +00:00
|
|
|
case ARM::FK_FPV5_SP_D16:
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_FPV5_D16:
|
2014-10-01 09:02:17 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
|
|
|
ARMBuildAttrs::AllowFPARMv8B,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_NEON:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPv3A,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
setAttributeItem(ARMBuildAttrs::Advanced_SIMD_arch,
|
|
|
|
ARMBuildAttrs::AllowNeon,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-06-29 09:32:29 +00:00
|
|
|
case ARM::FK_NEON_FP16:
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
|
|
|
ARMBuildAttrs::AllowFPv3A,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
setAttributeItem(ARMBuildAttrs::Advanced_SIMD_arch,
|
|
|
|
ARMBuildAttrs::AllowNeon,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
setAttributeItem(ARMBuildAttrs::FP_HP_extension,
|
|
|
|
ARMBuildAttrs::AllowHPFP,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_NEON_VFPV4:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPv4A,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
setAttributeItem(ARMBuildAttrs::Advanced_SIMD_arch,
|
|
|
|
ARMBuildAttrs::AllowNeon2,
|
|
|
|
/* OverwriteExisting= */ false);
|
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_NEON_FP_ARMV8:
|
|
|
|
case ARM::FK_CRYPTO_NEON_FP_ARMV8:
|
2013-12-18 17:23:15 +00:00
|
|
|
setAttributeItem(ARMBuildAttrs::FP_arch,
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMBuildAttrs::AllowFPARMv8A,
|
|
|
|
/* OverwriteExisting= */ false);
|
2015-03-26 17:05:54 +00:00
|
|
|
// 'Advanced_SIMD_arch' must be emitted not here, but within
|
|
|
|
// ARMAsmPrinter::emitAttributes(), depending on hasV8Ops() and hasV8_1a()
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
break;
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
case ARM::FK_SOFTVFP:
|
2015-06-05 13:31:19 +00:00
|
|
|
case ARM::FK_NONE:
|
2014-01-02 15:50:02 +00:00
|
|
|
break;
|
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
default:
|
|
|
|
report_fatal_error("Unknown FPU: " + Twine(FPU));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
size_t ARMTargetELFStreamer::calculateContentSize() const {
|
|
|
|
size_t Result = 0;
|
|
|
|
for (size_t i = 0; i < Contents.size(); ++i) {
|
|
|
|
AttributeItem item = Contents[i];
|
|
|
|
switch (item.Type) {
|
|
|
|
case AttributeItem::HiddenAttribute:
|
|
|
|
break;
|
|
|
|
case AttributeItem::NumericAttribute:
|
2014-02-22 14:00:39 +00:00
|
|
|
Result += getULEB128Size(item.Tag);
|
|
|
|
Result += getULEB128Size(item.IntValue);
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
break;
|
|
|
|
case AttributeItem::TextAttribute:
|
2014-02-22 14:00:39 +00:00
|
|
|
Result += getULEB128Size(item.Tag);
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
Result += item.StringValue.size() + 1; // string + '\0'
|
|
|
|
break;
|
2014-01-07 02:28:42 +00:00
|
|
|
case AttributeItem::NumericAndTextAttributes:
|
2014-02-22 14:00:39 +00:00
|
|
|
Result += getULEB128Size(item.Tag);
|
|
|
|
Result += getULEB128Size(item.IntValue);
|
2014-01-07 02:28:42 +00:00
|
|
|
Result += item.StringValue.size() + 1; // string + '\0';
|
|
|
|
break;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
void ARMTargetELFStreamer::finishAttributeSection() {
|
|
|
|
// <format-version>
|
|
|
|
// [ <section-length> "vendor-name"
|
|
|
|
// [ <file-tag> <size> <attribute>*
|
|
|
|
// | <section-tag> <size> <section-number>* 0 <attribute>*
|
|
|
|
// | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
|
|
|
|
// ]+
|
|
|
|
// ]*
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
if (FPU != ARM::FK_INVALID)
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
emitFPUDefaultAttributes();
|
|
|
|
|
2015-05-12 10:33:58 +00:00
|
|
|
if (Arch != ARM::AK_INVALID)
|
2013-12-11 17:16:25 +00:00
|
|
|
emitArchDefaultAttributes();
|
|
|
|
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
if (Contents.empty())
|
|
|
|
return;
|
|
|
|
|
|
|
|
std::sort(Contents.begin(), Contents.end(), AttributeItem::LessTag);
|
|
|
|
|
|
|
|
ARMELFStreamer &Streamer = getStreamer();
|
|
|
|
|
|
|
|
// Switch to .ARM.attributes section
|
|
|
|
if (AttributeSection) {
|
|
|
|
Streamer.SwitchSection(AttributeSection);
|
|
|
|
} else {
|
2015-01-29 17:33:21 +00:00
|
|
|
AttributeSection = Streamer.getContext().getELFSection(
|
|
|
|
".ARM.attributes", ELF::SHT_ARM_ATTRIBUTES, 0);
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
Streamer.SwitchSection(AttributeSection);
|
|
|
|
|
|
|
|
// Format version
|
|
|
|
Streamer.EmitIntValue(0x41, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Vendor size + Vendor name + '\0'
|
|
|
|
const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
|
|
|
|
|
|
|
|
// Tag + Tag Size
|
|
|
|
const size_t TagHeaderSize = 1 + 4;
|
|
|
|
|
|
|
|
const size_t ContentsSize = calculateContentSize();
|
|
|
|
|
|
|
|
Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
|
|
|
|
Streamer.EmitBytes(CurrentVendor);
|
|
|
|
Streamer.EmitIntValue(0, 1); // '\0'
|
|
|
|
|
|
|
|
Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
|
|
|
|
Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
|
|
|
|
|
|
|
|
// Size should have been accounted for already, now
|
|
|
|
// emit each field as its type (ULEB or String)
|
|
|
|
for (size_t i = 0; i < Contents.size(); ++i) {
|
|
|
|
AttributeItem item = Contents[i];
|
|
|
|
Streamer.EmitULEB128IntValue(item.Tag);
|
|
|
|
switch (item.Type) {
|
|
|
|
default: llvm_unreachable("Invalid attribute type");
|
|
|
|
case AttributeItem::NumericAttribute:
|
|
|
|
Streamer.EmitULEB128IntValue(item.IntValue);
|
|
|
|
break;
|
|
|
|
case AttributeItem::TextAttribute:
|
2014-11-27 12:13:56 +00:00
|
|
|
Streamer.EmitBytes(item.StringValue);
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
Streamer.EmitIntValue(0, 1); // '\0'
|
|
|
|
break;
|
2014-01-07 02:28:42 +00:00
|
|
|
case AttributeItem::NumericAndTextAttributes:
|
|
|
|
Streamer.EmitULEB128IntValue(item.IntValue);
|
2014-11-27 12:13:56 +00:00
|
|
|
Streamer.EmitBytes(item.StringValue);
|
2014-01-07 02:28:42 +00:00
|
|
|
Streamer.EmitIntValue(0, 1); // '\0'
|
|
|
|
break;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Contents.clear();
|
2015-05-12 10:33:58 +00:00
|
|
|
FPU = ARM::FK_INVALID;
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
}
|
2014-04-27 17:10:46 +00:00
|
|
|
|
|
|
|
void ARMTargetELFStreamer::emitLabel(MCSymbol *Symbol) {
|
|
|
|
ARMELFStreamer &Streamer = getStreamer();
|
|
|
|
if (!Streamer.IsThumb)
|
|
|
|
return;
|
|
|
|
|
2015-06-03 19:03:11 +00:00
|
|
|
Streamer.getAssembler().registerSymbol(*Symbol);
|
2015-06-02 20:38:46 +00:00
|
|
|
unsigned Type = cast<MCSymbolELF>(Symbol)->getType();
|
2015-06-04 00:47:43 +00:00
|
|
|
if (Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)
|
2014-04-27 17:10:46 +00:00
|
|
|
Streamer.EmitThumbFunc(Symbol);
|
|
|
|
}
|
|
|
|
|
2014-01-30 04:02:47 +00:00
|
|
|
void
|
|
|
|
ARMTargetELFStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *S) {
|
|
|
|
getStreamer().EmitFixup(S, FK_Data_4);
|
|
|
|
}
|
2014-04-27 20:23:58 +00:00
|
|
|
|
|
|
|
void ARMTargetELFStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {
|
|
|
|
if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Value)) {
|
2014-05-01 12:45:43 +00:00
|
|
|
const MCSymbol &Sym = SRE->getSymbol();
|
|
|
|
if (!Sym.isDefined()) {
|
2014-04-27 20:23:58 +00:00
|
|
|
getStreamer().EmitAssignment(Symbol, Value);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
getStreamer().EmitThumbFunc(Symbol);
|
|
|
|
getStreamer().EmitAssignment(Symbol, Value);
|
|
|
|
}
|
|
|
|
|
2013-12-19 05:17:58 +00:00
|
|
|
void ARMTargetELFStreamer::emitInst(uint32_t Inst, char Suffix) {
|
|
|
|
getStreamer().emitInst(Inst, Suffix);
|
|
|
|
}
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
|
|
|
|
void ARMELFStreamer::FinishImpl() {
|
2014-01-14 01:21:46 +00:00
|
|
|
MCTargetStreamer &TS = *getTargetStreamer();
|
[arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.
To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.
Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.
This commit changes the test cases:
* Several .eabi_attribute directives in
2010-09-29-mc-asm-header-test.ll are removed because the .fpu
directive already cover the functionality.
* In the Cortex-A15 test case, the value for
Tag_Advanced_SIMD_arch has be changed from 1 to 2,
which is more precise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
|
|
|
ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
|
|
|
|
ATS.finishAttributeSection();
|
|
|
|
|
|
|
|
MCELFStreamer::FinishImpl();
|
|
|
|
}
|
2013-10-08 13:08:17 +00:00
|
|
|
|
2013-01-30 15:39:04 +00:00
|
|
|
inline void ARMELFStreamer::SwitchToEHSection(const char *Prefix,
|
|
|
|
unsigned Type,
|
|
|
|
unsigned Flags,
|
|
|
|
SectionKind Kind,
|
|
|
|
const MCSymbol &Fn) {
|
|
|
|
const MCSectionELF &FnSection =
|
|
|
|
static_cast<const MCSectionELF &>(Fn.getSection());
|
|
|
|
|
|
|
|
// Create the name for new section
|
|
|
|
StringRef FnSecName(FnSection.getSectionName());
|
|
|
|
SmallString<128> EHSecName(Prefix);
|
|
|
|
if (FnSecName != ".text") {
|
|
|
|
EHSecName += FnSecName;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get .ARM.extab or .ARM.exidx section
|
2015-06-02 21:30:13 +00:00
|
|
|
const MCSymbolELF *Group = FnSection.getGroup();
|
2015-04-06 04:25:18 +00:00
|
|
|
if (Group)
|
|
|
|
Flags |= ELF::SHF_GROUP;
|
2015-05-21 19:20:38 +00:00
|
|
|
MCSectionELF *EHSection =
|
2015-04-06 04:25:18 +00:00
|
|
|
getContext().getELFSection(EHSecName, Type, Flags, 0, Group,
|
|
|
|
FnSection.getUniqueID(), nullptr, &FnSection);
|
|
|
|
|
2013-04-16 12:02:21 +00:00
|
|
|
assert(EHSection && "Failed to get the required EH section");
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
// Switch to .ARM.extab or .ARM.exidx section
|
|
|
|
SwitchSection(EHSection);
|
2014-02-04 18:34:04 +00:00
|
|
|
EmitCodeAlignment(4);
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
inline void ARMELFStreamer::SwitchToExTabSection(const MCSymbol &FnStart) {
|
|
|
|
SwitchToEHSection(".ARM.extab",
|
|
|
|
ELF::SHT_PROGBITS,
|
|
|
|
ELF::SHF_ALLOC,
|
|
|
|
SectionKind::getDataRel(),
|
|
|
|
FnStart);
|
|
|
|
}
|
|
|
|
|
|
|
|
inline void ARMELFStreamer::SwitchToExIdxSection(const MCSymbol &FnStart) {
|
|
|
|
SwitchToEHSection(".ARM.exidx",
|
|
|
|
ELF::SHT_ARM_EXIDX,
|
|
|
|
ELF::SHF_ALLOC | ELF::SHF_LINK_ORDER,
|
|
|
|
SectionKind::getDataRel(),
|
|
|
|
FnStart);
|
|
|
|
}
|
2014-01-30 04:02:47 +00:00
|
|
|
void ARMELFStreamer::EmitFixup(const MCExpr *Expr, MCFixupKind Kind) {
|
|
|
|
MCDataFragment *Frag = getOrCreateDataFragment();
|
2015-05-15 19:13:05 +00:00
|
|
|
Frag->getFixups().push_back(MCFixup::create(Frag->getContents().size(), Expr,
|
2014-01-30 04:02:47 +00:00
|
|
|
Kind));
|
|
|
|
}
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
void ARMELFStreamer::Reset() {
|
2014-04-25 05:30:21 +00:00
|
|
|
ExTab = nullptr;
|
|
|
|
FnStart = nullptr;
|
|
|
|
Personality = nullptr;
|
2014-01-06 00:15:00 +00:00
|
|
|
PersonalityIndex = ARM::EHABI::NUM_PERSONALITY_INDEX;
|
2013-06-09 12:22:30 +00:00
|
|
|
FPReg = ARM::SP;
|
2013-04-16 12:02:21 +00:00
|
|
|
FPOffset = 0;
|
|
|
|
SPOffset = 0;
|
2013-06-09 12:22:30 +00:00
|
|
|
PendingOffset = 0;
|
2013-04-16 12:02:21 +00:00
|
|
|
UsedFP = false;
|
2013-01-30 15:39:04 +00:00
|
|
|
CantUnwind = false;
|
2013-04-16 12:02:21 +00:00
|
|
|
|
2013-06-09 12:22:30 +00:00
|
|
|
Opcodes.clear();
|
2013-04-16 12:02:21 +00:00
|
|
|
UnwindOpAsm.Reset();
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitFnStart() {
|
2014-04-28 04:05:08 +00:00
|
|
|
assert(FnStart == nullptr);
|
2015-05-18 18:43:14 +00:00
|
|
|
FnStart = getContext().createTempSymbol();
|
2013-01-30 15:39:04 +00:00
|
|
|
EmitLabel(FnStart);
|
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitFnEnd() {
|
2014-01-24 17:20:08 +00:00
|
|
|
assert(FnStart && ".fnstart must precedes .fnend");
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
// Emit unwind opcodes if there is no .handlerdata directive
|
2013-05-10 16:17:24 +00:00
|
|
|
if (!ExTab && !CantUnwind)
|
|
|
|
FlushUnwindOpcodes(true);
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
// Emit the exception index table entry
|
|
|
|
SwitchToExIdxSection(*FnStart);
|
|
|
|
|
2014-01-06 00:15:00 +00:00
|
|
|
if (PersonalityIndex < ARM::EHABI::NUM_PERSONALITY_INDEX)
|
2013-04-16 12:02:21 +00:00
|
|
|
EmitPersonalityFixup(GetAEABIUnwindPersonalityName(PersonalityIndex));
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
const MCSymbolRefExpr *FnStartRef =
|
2015-05-30 01:25:56 +00:00
|
|
|
MCSymbolRefExpr::create(FnStart,
|
2013-01-30 15:39:04 +00:00
|
|
|
MCSymbolRefExpr::VK_ARM_PREL31,
|
|
|
|
getContext());
|
|
|
|
|
2013-07-02 15:49:13 +00:00
|
|
|
EmitValue(FnStartRef, 4);
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
if (CantUnwind) {
|
2014-01-06 00:15:00 +00:00
|
|
|
EmitIntValue(ARM::EHABI::EXIDX_CANTUNWIND, 4);
|
2013-04-16 12:02:21 +00:00
|
|
|
} else if (ExTab) {
|
|
|
|
// Emit a reference to the unwind opcodes in the ".ARM.extab" section.
|
2013-01-30 15:39:04 +00:00
|
|
|
const MCSymbolRefExpr *ExTabEntryRef =
|
2015-05-30 01:25:56 +00:00
|
|
|
MCSymbolRefExpr::create(ExTab,
|
2013-01-30 15:39:04 +00:00
|
|
|
MCSymbolRefExpr::VK_ARM_PREL31,
|
|
|
|
getContext());
|
2013-07-02 15:49:13 +00:00
|
|
|
EmitValue(ExTabEntryRef, 4);
|
2013-04-16 12:02:21 +00:00
|
|
|
} else {
|
|
|
|
// For the __aeabi_unwind_cpp_pr0, we have to emit the unwind opcodes in
|
|
|
|
// the second word of exception index table entry. The size of the unwind
|
|
|
|
// opcodes should always be 4 bytes.
|
2014-01-06 00:15:00 +00:00
|
|
|
assert(PersonalityIndex == ARM::EHABI::AEABI_UNWIND_CPP_PR0 &&
|
2014-05-15 02:24:50 +00:00
|
|
|
"Compact model must use __aeabi_unwind_cpp_pr0 as personality");
|
2013-06-09 12:22:30 +00:00
|
|
|
assert(Opcodes.size() == 4u &&
|
2014-05-15 02:24:50 +00:00
|
|
|
"Unwind opcode size for __aeabi_unwind_cpp_pr0 must be equal to 4");
|
2014-05-13 16:44:30 +00:00
|
|
|
uint64_t Intval = Opcodes[0] |
|
|
|
|
Opcodes[1] << 8 |
|
|
|
|
Opcodes[2] << 16 |
|
|
|
|
Opcodes[3] << 24;
|
|
|
|
EmitIntValue(Intval, Opcodes.size());
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2013-05-10 16:17:24 +00:00
|
|
|
// Switch to the section containing FnStart
|
|
|
|
SwitchSection(&FnStart->getSection());
|
|
|
|
|
2013-01-30 15:39:04 +00:00
|
|
|
// Clean exception handling frame information
|
|
|
|
Reset();
|
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitCantUnwind() { CantUnwind = true; }
|
|
|
|
|
|
|
|
// Add the R_ARM_NONE fixup at the same position
|
|
|
|
void ARMELFStreamer::EmitPersonalityFixup(StringRef Name) {
|
2015-05-18 18:43:14 +00:00
|
|
|
const MCSymbol *PersonalitySym = getContext().getOrCreateSymbol(Name);
|
2013-10-08 13:08:17 +00:00
|
|
|
|
2015-05-30 01:25:56 +00:00
|
|
|
const MCSymbolRefExpr *PersonalityRef = MCSymbolRefExpr::create(
|
2013-10-08 13:08:17 +00:00
|
|
|
PersonalitySym, MCSymbolRefExpr::VK_ARM_NONE, getContext());
|
|
|
|
|
2014-06-25 15:29:54 +00:00
|
|
|
visitUsedExpr(*PersonalityRef);
|
2013-10-08 13:08:17 +00:00
|
|
|
MCDataFragment *DF = getOrCreateDataFragment();
|
2015-05-15 19:13:05 +00:00
|
|
|
DF->getFixups().push_back(MCFixup::create(DF->getContents().size(),
|
2013-10-08 13:08:17 +00:00
|
|
|
PersonalityRef,
|
|
|
|
MCFixup::getKindForSize(4, false)));
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2013-06-09 12:22:30 +00:00
|
|
|
void ARMELFStreamer::FlushPendingOffset() {
|
|
|
|
if (PendingOffset != 0) {
|
|
|
|
UnwindOpAsm.EmitSPOffset(-PendingOffset);
|
|
|
|
PendingOffset = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-02 12:43:27 +00:00
|
|
|
void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) {
|
2013-06-09 12:22:30 +00:00
|
|
|
// Emit the unwind opcode to restore $sp.
|
|
|
|
if (UsedFP) {
|
2013-06-18 07:20:20 +00:00
|
|
|
const MCRegisterInfo *MRI = getContext().getRegisterInfo();
|
2013-06-09 12:22:30 +00:00
|
|
|
int64_t LastRegSaveSPOffset = SPOffset - PendingOffset;
|
|
|
|
UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset);
|
2013-06-18 07:20:20 +00:00
|
|
|
UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg));
|
2013-06-09 12:22:30 +00:00
|
|
|
} else {
|
|
|
|
FlushPendingOffset();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Finalize the unwind opcode sequence
|
|
|
|
UnwindOpAsm.Finalize(PersonalityIndex, Opcodes);
|
2013-05-10 16:17:24 +00:00
|
|
|
|
|
|
|
// For compact model 0, we have to emit the unwind opcodes in the .ARM.exidx
|
|
|
|
// section. Thus, we don't have to create an entry in the .ARM.extab
|
|
|
|
// section.
|
2014-01-06 00:15:00 +00:00
|
|
|
if (NoHandlerData && PersonalityIndex == ARM::EHABI::AEABI_UNWIND_CPP_PR0)
|
2013-05-10 16:17:24 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
// Switch to .ARM.extab section.
|
2013-01-30 15:39:04 +00:00
|
|
|
SwitchToExTabSection(*FnStart);
|
|
|
|
|
|
|
|
// Create .ARM.extab label for offset in .ARM.exidx
|
|
|
|
assert(!ExTab);
|
2015-05-18 18:43:14 +00:00
|
|
|
ExTab = getContext().createTempSymbol();
|
2013-01-30 15:39:04 +00:00
|
|
|
EmitLabel(ExTab);
|
|
|
|
|
2013-05-10 16:17:24 +00:00
|
|
|
// Emit personality
|
|
|
|
if (Personality) {
|
|
|
|
const MCSymbolRefExpr *PersonalityRef =
|
2015-05-30 01:25:56 +00:00
|
|
|
MCSymbolRefExpr::create(Personality,
|
2013-05-10 16:17:24 +00:00
|
|
|
MCSymbolRefExpr::VK_ARM_PREL31,
|
|
|
|
getContext());
|
2013-01-30 15:39:04 +00:00
|
|
|
|
2013-07-02 15:49:13 +00:00
|
|
|
EmitValue(PersonalityRef, 4);
|
2013-05-10 16:17:24 +00:00
|
|
|
}
|
2013-01-30 15:39:04 +00:00
|
|
|
|
|
|
|
// Emit unwind opcodes
|
2014-05-13 16:44:30 +00:00
|
|
|
assert((Opcodes.size() % 4) == 0 &&
|
|
|
|
"Unwind opcode size for __aeabi_cpp_unwind_pr0 must be multiple of 4");
|
|
|
|
for (unsigned I = 0; I != Opcodes.size(); I += 4) {
|
|
|
|
uint64_t Intval = Opcodes[I] |
|
|
|
|
Opcodes[I + 1] << 8 |
|
|
|
|
Opcodes[I + 2] << 16 |
|
|
|
|
Opcodes[I + 3] << 24;
|
|
|
|
EmitIntValue(Intval, 4);
|
|
|
|
}
|
2013-07-02 12:43:27 +00:00
|
|
|
|
|
|
|
// According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or
|
|
|
|
// __aeabi_unwind_cpp_pr2() is used, then the handler data must be emitted
|
|
|
|
// after the unwind opcodes. The handler data consists of several 32-bit
|
|
|
|
// words, and should be terminated by zero.
|
|
|
|
//
|
|
|
|
// In case that the .handlerdata directive is not specified by the
|
|
|
|
// programmer, we should emit zero to terminate the handler data.
|
|
|
|
if (NoHandlerData && !Personality)
|
|
|
|
EmitIntValue(0, 4);
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitHandlerData() { FlushUnwindOpcodes(false); }
|
2013-05-10 16:17:24 +00:00
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitPersonality(const MCSymbol *Per) {
|
2013-01-30 15:39:04 +00:00
|
|
|
Personality = Per;
|
2013-04-16 12:02:21 +00:00
|
|
|
UnwindOpAsm.setPersonality(Per);
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2014-01-21 02:33:02 +00:00
|
|
|
void ARMELFStreamer::emitPersonalityIndex(unsigned Index) {
|
|
|
|
assert(Index < ARM::EHABI::NUM_PERSONALITY_INDEX && "invalid index");
|
|
|
|
PersonalityIndex = Index;
|
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitSetFP(unsigned NewFPReg, unsigned NewSPReg,
|
2013-01-30 15:39:04 +00:00
|
|
|
int64_t Offset) {
|
2013-06-09 12:22:30 +00:00
|
|
|
assert((NewSPReg == ARM::SP || NewSPReg == FPReg) &&
|
2013-04-16 12:02:21 +00:00
|
|
|
"the operand of .setfp directive should be either $sp or $fp");
|
|
|
|
|
|
|
|
UsedFP = true;
|
2013-06-09 12:22:30 +00:00
|
|
|
FPReg = NewFPReg;
|
|
|
|
|
|
|
|
if (NewSPReg == ARM::SP)
|
|
|
|
FPOffset = SPOffset + Offset;
|
|
|
|
else
|
|
|
|
FPOffset += Offset;
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2014-01-30 04:46:24 +00:00
|
|
|
void ARMELFStreamer::emitMovSP(unsigned Reg, int64_t Offset) {
|
|
|
|
assert((Reg != ARM::SP && Reg != ARM::PC) &&
|
|
|
|
"the operand of .movsp cannot be either sp or pc");
|
|
|
|
assert(FPReg == ARM::SP && "current FP must be SP");
|
|
|
|
|
|
|
|
FlushPendingOffset();
|
|
|
|
|
|
|
|
FPReg = Reg;
|
|
|
|
FPOffset = SPOffset + Offset;
|
|
|
|
|
|
|
|
const MCRegisterInfo *MRI = getContext().getRegisterInfo();
|
|
|
|
UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg));
|
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitPad(int64_t Offset) {
|
2013-06-09 12:22:30 +00:00
|
|
|
// Track the change of the $sp offset
|
|
|
|
SPOffset -= Offset;
|
|
|
|
|
|
|
|
// To squash multiple .pad directives, we should delay the unwind opcode
|
|
|
|
// until the .save, .vsave, .handlerdata, or .fnend directives.
|
|
|
|
PendingOffset -= Offset;
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2013-10-08 13:08:17 +00:00
|
|
|
void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
|
2013-01-30 15:39:04 +00:00
|
|
|
bool IsVector) {
|
2013-06-09 12:22:30 +00:00
|
|
|
// Collect the registers in the register list
|
|
|
|
unsigned Count = 0;
|
|
|
|
uint32_t Mask = 0;
|
2013-06-18 07:20:20 +00:00
|
|
|
const MCRegisterInfo *MRI = getContext().getRegisterInfo();
|
2013-04-16 12:02:21 +00:00
|
|
|
for (size_t i = 0; i < RegList.size(); ++i) {
|
2013-06-18 07:20:20 +00:00
|
|
|
unsigned Reg = MRI->getEncodingValue(RegList[i]);
|
2013-06-10 16:45:40 +00:00
|
|
|
assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
|
2013-06-09 12:22:30 +00:00
|
|
|
unsigned Bit = (1u << Reg);
|
|
|
|
if ((Mask & Bit) == 0) {
|
|
|
|
Mask |= Bit;
|
|
|
|
++Count;
|
|
|
|
}
|
2013-04-16 12:02:21 +00:00
|
|
|
}
|
2013-06-09 12:22:30 +00:00
|
|
|
|
|
|
|
// Track the change the $sp offset: For the .save directive, the
|
|
|
|
// corresponding push instruction will decrease the $sp by (4 * Count).
|
|
|
|
// For the .vsave directive, the corresponding vpush instruction will
|
|
|
|
// decrease $sp by (8 * Count).
|
|
|
|
SPOffset -= Count * (IsVector ? 8 : 4);
|
|
|
|
|
|
|
|
// Emit the opcode
|
|
|
|
FlushPendingOffset();
|
|
|
|
if (IsVector)
|
|
|
|
UnwindOpAsm.EmitVFPRegSave(Mask);
|
|
|
|
else
|
|
|
|
UnwindOpAsm.EmitRegSave(Mask);
|
2013-01-30 15:39:04 +00:00
|
|
|
}
|
|
|
|
|
2014-01-21 02:33:10 +00:00
|
|
|
void ARMELFStreamer::emitUnwindRaw(int64_t Offset,
|
|
|
|
const SmallVectorImpl<uint8_t> &Opcodes) {
|
|
|
|
FlushPendingOffset();
|
|
|
|
SPOffset = SPOffset - Offset;
|
|
|
|
UnwindOpAsm.EmitRaw(Opcodes);
|
|
|
|
}
|
|
|
|
|
2012-12-07 16:50:23 +00:00
|
|
|
namespace llvm {
|
2013-10-08 13:08:17 +00:00
|
|
|
|
2015-03-16 21:43:42 +00:00
|
|
|
MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
|
|
|
|
formatted_raw_ostream &OS,
|
|
|
|
MCInstPrinter *InstPrint,
|
|
|
|
bool isVerboseAsm) {
|
|
|
|
return new ARMTargetAsmStreamer(S, OS, *InstPrint, isVerboseAsm);
|
2013-10-08 13:08:17 +00:00
|
|
|
}
|
|
|
|
|
2015-02-19 00:45:02 +00:00
|
|
|
MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S) {
|
|
|
|
return new ARMTargetStreamer(S);
|
|
|
|
}
|
|
|
|
|
2015-03-19 01:50:16 +00:00
|
|
|
MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
|
|
|
|
const MCSubtargetInfo &STI) {
|
2015-06-16 15:44:21 +00:00
|
|
|
const Triple &TT = STI.getTargetTriple();
|
2015-07-06 16:33:18 +00:00
|
|
|
if (TT.isOSBinFormatELF())
|
2015-03-19 01:50:16 +00:00
|
|
|
return new ARMTargetELFStreamer(S);
|
|
|
|
return new ARMTargetStreamer(S);
|
|
|
|
}
|
|
|
|
|
2014-10-15 16:12:52 +00:00
|
|
|
MCELFStreamer *createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB,
|
2015-04-14 22:14:34 +00:00
|
|
|
raw_pwrite_stream &OS,
|
|
|
|
MCCodeEmitter *Emitter, bool RelaxAll,
|
|
|
|
bool IsThumb) {
|
2014-01-26 06:06:37 +00:00
|
|
|
ARMELFStreamer *S = new ARMELFStreamer(Context, TAB, OS, Emitter, IsThumb);
|
2013-10-05 16:42:21 +00:00
|
|
|
// FIXME: This should eventually end up somewhere else where more
|
|
|
|
// intelligent flag decisions can be made. For now we are just maintaining
|
|
|
|
// the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
|
|
|
|
S->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
|
|
|
|
|
2012-12-07 16:50:23 +00:00
|
|
|
if (RelaxAll)
|
|
|
|
S->getAssembler().setRelaxAll(true);
|
|
|
|
return S;
|
|
|
|
}
|
|
|
|
|
2015-06-23 09:49:53 +00:00
|
|
|
}
|
2012-12-07 16:50:23 +00:00
|
|
|
|
|
|
|
|