2004-02-25 18:44:15 +00:00
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//===-- SparcV9InstrInfo.cpp ------------------------------------------------===//
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2003-10-20 19:43:21 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2002-08-09 20:08:06 +00:00
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//
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//===----------------------------------------------------------------------===//
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2001-10-18 00:01:48 +00:00
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2003-11-07 17:29:48 +00:00
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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2001-10-18 00:01:48 +00:00
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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2003-11-07 17:29:48 +00:00
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#include "llvm/CodeGen/MachineConstantPool.h"
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2002-10-28 00:28:31 +00:00
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#include "llvm/CodeGen/MachineFunction.h"
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2002-12-28 20:18:21 +00:00
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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2002-05-19 15:25:51 +00:00
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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2003-01-15 00:03:28 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2004-02-25 18:44:15 +00:00
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#include "SparcV9Internals.h"
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#include "SparcV9InstrSelectionSupport.h"
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#include "SparcV9InstrInfo.h"
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2001-10-18 00:01:48 +00:00
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2003-11-11 22:41:34 +00:00
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namespace llvm {
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2002-07-10 21:39:50 +00:00
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static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
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static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
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2001-10-18 00:01:48 +00:00
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2003-01-15 21:36:50 +00:00
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//---------------------------------------------------------------------------
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2003-07-29 19:59:23 +00:00
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// Function ConvertConstantToIntType
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2003-01-15 21:36:50 +00:00
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//
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2003-07-29 19:59:23 +00:00
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// Function to get the value of an integral constant in the form
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// that must be put into the machine register. The specified constant is
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// interpreted as (i.e., converted if necessary to) the specified destination
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// type. The result is always returned as an uint64_t, since the representation
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// of int64_t and uint64_t are identical. The argument can be any known const.
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2003-01-15 21:36:50 +00:00
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//
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// isValidConstant is set to true if a valid constant was found.
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//---------------------------------------------------------------------------
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2003-07-29 19:59:23 +00:00
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uint64_t
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2004-02-25 18:44:15 +00:00
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SparcV9InstrInfo::ConvertConstantToIntType(const TargetMachine &target,
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2003-07-29 19:59:23 +00:00
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const Value *V,
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const Type *destType,
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bool &isValidConstant) const
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2003-01-15 21:36:50 +00:00
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{
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2003-07-29 19:59:23 +00:00
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isValidConstant = false;
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uint64_t C = 0;
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2003-01-15 21:36:50 +00:00
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2003-07-29 19:59:23 +00:00
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if (! destType->isIntegral() && ! isa<PointerType>(destType))
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return C;
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2003-01-15 21:36:50 +00:00
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2003-07-29 19:59:23 +00:00
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if (! isa<Constant>(V))
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return C;
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2003-01-15 21:36:50 +00:00
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2003-07-29 19:59:23 +00:00
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// ConstantPointerRef: no conversions needed: get value and return it
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if (const ConstantPointerRef* CPR = dyn_cast<ConstantPointerRef>(V)) {
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// A ConstantPointerRef is just a reference to GlobalValue.
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isValidConstant = true; // may be overwritten by recursive call
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return (CPR->isNullValue()? 0
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: ConvertConstantToIntType(target, CPR->getValue(), destType,
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isValidConstant));
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}
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// ConstantBool: no conversions needed: get value and return it
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if (const ConstantBool *CB = dyn_cast<ConstantBool>(V)) {
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isValidConstant = true;
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return (uint64_t) CB->getValue();
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}
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// For other types of constants, some conversion may be needed.
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// First, extract the constant operand according to its own type
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if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
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switch(CE->getOpcode()) {
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case Instruction::Cast: // recursively get the value as cast
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C = ConvertConstantToIntType(target, CE->getOperand(0), CE->getType(),
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isValidConstant);
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break;
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default: // not simplifying other ConstantExprs
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break;
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}
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else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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isValidConstant = true;
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C = CI->getRawValue();
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}
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else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(V)) {
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isValidConstant = true;
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double fC = CFP->getValue();
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C = (destType->isSigned()? (uint64_t) (int64_t) fC
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: (uint64_t) fC);
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}
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// Now if a valid value was found, convert it to destType.
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2003-01-15 21:36:50 +00:00
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if (isValidConstant) {
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2003-07-29 19:59:23 +00:00
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unsigned opSize = target.getTargetData().getTypeSize(V->getType());
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unsigned destSize = target.getTargetData().getTypeSize(destType);
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uint64_t maskHi = (destSize < 8)? (1U << 8*destSize) - 1 : ~0;
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assert(opSize <= 8 && destSize <= 8 && ">8-byte int type unexpected");
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if (destType->isSigned()) {
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if (opSize > destSize) // operand is larger than dest:
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C = C & maskHi; // mask high bits
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if (opSize > destSize ||
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(opSize == destSize && ! V->getType()->isSigned()))
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if (C & (1U << (8*destSize - 1)))
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C = C | ~maskHi; // sign-extend from destSize to 64 bits
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}
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else {
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if (opSize > destSize || (V->getType()->isSigned() && destSize < 8)) {
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// operand is larger than dest,
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// OR both are equal but smaller than the full register size
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// AND operand is signed, so it may have extra sign bits:
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// mask high bits
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C = C & maskHi;
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}
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}
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2003-01-15 21:36:50 +00:00
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}
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2003-07-29 19:59:23 +00:00
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return C;
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2003-01-15 21:36:50 +00:00
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}
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2002-08-13 18:04:08 +00:00
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//----------------------------------------------------------------------------
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// Function: CreateSETUWConst
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2002-07-10 21:39:50 +00:00
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//
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2002-08-13 18:04:08 +00:00
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// Set a 32-bit unsigned constant in the register `dest', using
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// SETHI, OR in the worst case. This function correctly emulates
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// the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
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//
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// The isSigned=true case is used to implement SETSW without duplicating code.
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//
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// Optimize some common cases:
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// (1) Small value that fits in simm13 field of OR: don't need SETHI.
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// (2) isSigned = true and C is a small negative signed value, i.e.,
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// high bits are 1, and the remaining bits fit in simm13(OR).
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//----------------------------------------------------------------------------
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2002-07-10 21:39:50 +00:00
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static inline void
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CreateSETUWConst(const TargetMachine& target, uint32_t C,
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2003-05-20 20:32:24 +00:00
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Instruction* dest, std::vector<MachineInstr*>& mvec,
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2002-08-13 18:04:08 +00:00
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bool isSigned = false)
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2002-07-10 21:39:50 +00:00
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{
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MachineInstr *miSETHI = NULL, *miOR = NULL;
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2002-08-13 18:04:08 +00:00
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2002-07-10 21:39:50 +00:00
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// In order to get efficient code, we should not generate the SETHI if
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// all high bits are 1 (i.e., this is a small signed value that fits in
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// the simm13 field of OR). So we check for and handle that case specially.
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// NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
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// In fact, sC == -sC, so we have to check for this explicitly.
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int32_t sC = (int32_t) C;
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2002-08-13 18:04:08 +00:00
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bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
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2002-07-10 21:39:50 +00:00
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// Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
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2003-05-21 18:48:06 +00:00
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if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
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miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
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miSETHI->setOperandHi32(0);
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mvec.push_back(miSETHI);
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}
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2002-07-10 21:39:50 +00:00
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// Set the low 10 or 12 bits in dest. This is necessary if no SETHI
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// was generated, or if the low 10 bits are non-zero.
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2003-05-21 18:48:06 +00:00
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if (miSETHI==NULL || C & MAXLO) {
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if (miSETHI) {
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// unsigned value with high-order bits set using SETHI
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2003-05-27 22:35:43 +00:00
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miOR = BuildMI(V9::ORi,3).addReg(dest).addZImm(C).addRegDef(dest);
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2003-05-21 18:48:06 +00:00
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miOR->setOperandLo32(1);
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} else {
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// unsigned or small signed value that fits in simm13 field of OR
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assert(smallNegValue || (C & ~MAXSIMM) == 0);
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2003-05-27 22:35:43 +00:00
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miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()
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2003-05-21 18:48:06 +00:00
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.getZeroRegNum())
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.addSImm(sC).addRegDef(dest);
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2002-07-10 21:39:50 +00:00
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}
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2003-05-21 18:48:06 +00:00
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mvec.push_back(miOR);
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}
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2002-07-10 21:39:50 +00:00
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assert((miSETHI || miOR) && "Oops, no code was generated!");
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}
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2002-08-13 18:04:08 +00:00
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//----------------------------------------------------------------------------
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// Function: CreateSETSWConst
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//
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// Set a 32-bit signed constant in the register `dest', with sign-extension
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// to 64 bits. This uses SETHI, OR, SRA in the worst case.
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// This function correctly emulates the SETSW pseudo-op for SPARC v9.
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//
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// Optimize the same cases as SETUWConst, plus:
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// (1) SRA is not needed for positive or small negative values.
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//----------------------------------------------------------------------------
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2002-07-10 21:39:50 +00:00
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2002-05-19 15:25:51 +00:00
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static inline void
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2002-07-10 21:39:50 +00:00
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CreateSETSWConst(const TargetMachine& target, int32_t C,
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2003-05-20 20:32:24 +00:00
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Instruction* dest, std::vector<MachineInstr*>& mvec)
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2002-07-10 21:39:50 +00:00
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{
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// Set the low 32 bits of dest
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2002-08-13 18:04:08 +00:00
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CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
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2003-05-25 21:58:11 +00:00
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// Sign-extend to the high 32 bits if needed.
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// NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
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if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
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2003-06-06 09:52:23 +00:00
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mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
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2002-07-10 21:39:50 +00:00
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}
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2002-08-13 18:04:08 +00:00
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//----------------------------------------------------------------------------
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// Function: CreateSETXConst
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//
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2002-07-10 21:39:50 +00:00
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// Set a 64-bit signed or unsigned constant in the register `dest'.
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2002-08-13 18:04:08 +00:00
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// Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
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// This function correctly emulates the SETX pseudo-op for SPARC v9.
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//
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// Optimize the same cases as SETUWConst for each 32 bit word.
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//----------------------------------------------------------------------------
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2002-07-10 21:39:50 +00:00
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static inline void
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CreateSETXConst(const TargetMachine& target, uint64_t C,
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Instruction* tmpReg, Instruction* dest,
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2003-05-20 20:32:24 +00:00
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std::vector<MachineInstr*>& mvec)
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2002-07-10 21:39:50 +00:00
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{
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assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
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MachineInstr* MI;
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// Code to set the upper 32 bits of the value in register `tmpReg'
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CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
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// Shift tmpReg left by 32 bits
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2003-05-27 22:35:43 +00:00
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mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
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2003-05-20 20:32:24 +00:00
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.addRegDef(tmpReg));
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2002-07-10 21:39:50 +00:00
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// Code to set the low 32 bits of the value in register `dest'
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CreateSETUWConst(target, C, dest, mvec);
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// dest = OR(tmpReg, dest)
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2003-05-27 22:35:43 +00:00
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mvec.push_back(BuildMI(V9::ORr,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
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2002-07-10 21:39:50 +00:00
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}
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2002-08-13 18:04:08 +00:00
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//----------------------------------------------------------------------------
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// Function: CreateSETUWLabel
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//
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// Set a 32-bit constant (given by a symbolic label) in the register `dest'.
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//----------------------------------------------------------------------------
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static inline void
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CreateSETUWLabel(const TargetMachine& target, Value* val,
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2003-05-20 20:32:24 +00:00
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Instruction* dest, std::vector<MachineInstr*>& mvec)
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2002-08-13 18:04:08 +00:00
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{
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MachineInstr* MI;
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// Set the high 22 bits in dest
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2003-05-20 20:32:24 +00:00
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MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(dest);
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2002-08-13 18:04:08 +00:00
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MI->setOperandHi32(0);
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mvec.push_back(MI);
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// Set the low 10 bits in dest
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2003-05-27 22:35:43 +00:00
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MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(val).addRegDef(dest);
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2002-08-13 18:04:08 +00:00
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MI->setOperandLo32(1);
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mvec.push_back(MI);
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}
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//----------------------------------------------------------------------------
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// Function: CreateSETXLabel
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//
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2002-07-10 21:39:50 +00:00
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// Set a 64-bit constant (given by a symbolic label) in the register `dest'.
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2002-08-13 18:04:08 +00:00
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//----------------------------------------------------------------------------
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2002-07-10 21:39:50 +00:00
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static inline void
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CreateSETXLabel(const TargetMachine& target,
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Value* val, Instruction* tmpReg, Instruction* dest,
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2003-05-20 20:32:24 +00:00
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std::vector<MachineInstr*>& mvec)
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2002-07-10 21:39:50 +00:00
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{
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assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
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"I only know about constant values and global addresses");
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MachineInstr* MI;
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2003-05-20 20:32:24 +00:00
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MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
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2002-07-10 21:39:50 +00:00
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MI->setOperandHi64(0);
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mvec.push_back(MI);
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2003-05-27 22:35:43 +00:00
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|
|
MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
|
2002-07-10 21:39:50 +00:00
|
|
|
MI->setOperandLo64(1);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
|
2003-05-27 22:35:43 +00:00
|
|
|
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
|
2003-05-20 20:32:24 +00:00
|
|
|
.addRegDef(tmpReg));
|
|
|
|
MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest);
|
2002-07-10 21:39:50 +00:00
|
|
|
MI->setOperandHi32(0);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
|
2003-05-27 22:35:43 +00:00
|
|
|
MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
|
2002-07-10 21:39:50 +00:00
|
|
|
mvec.push_back(MI);
|
|
|
|
|
2003-05-27 22:35:43 +00:00
|
|
|
MI = BuildMI(V9::ORi, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
|
2002-07-10 21:39:50 +00:00
|
|
|
MI->setOperandLo32(1);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2002-08-13 18:04:08 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// Function: CreateUIntSetInstruction
|
|
|
|
//
|
|
|
|
// Create code to Set an unsigned constant in the register `dest'.
|
|
|
|
// Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
|
|
|
|
// CreateSETSWConst is an optimization for the case that the unsigned value
|
|
|
|
// has all ones in the 33 high bits (so that sign-extension sets them all).
|
|
|
|
//----------------------------------------------------------------------------
|
2002-07-10 21:39:50 +00:00
|
|
|
|
2002-05-19 15:25:51 +00:00
|
|
|
static inline void
|
2002-07-10 21:39:50 +00:00
|
|
|
CreateUIntSetInstruction(const TargetMachine& target,
|
2002-05-19 15:25:51 +00:00
|
|
|
uint64_t C, Instruction* dest,
|
2002-08-13 18:04:08 +00:00
|
|
|
std::vector<MachineInstr*>& mvec,
|
2002-05-19 15:25:51 +00:00
|
|
|
MachineCodeForInstruction& mcfi)
|
2001-12-15 00:33:36 +00:00
|
|
|
{
|
2002-08-13 18:04:08 +00:00
|
|
|
static const uint64_t lo32 = (uint32_t) ~0;
|
|
|
|
if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
|
|
|
|
CreateSETUWConst(target, (uint32_t) C, dest, mvec);
|
2003-07-10 19:48:19 +00:00
|
|
|
else if ((C & ~lo32) == ~lo32 && (C & (1U << 31))) {
|
2003-05-21 18:48:06 +00:00
|
|
|
// All high 33 (not 32) bits are 1s: sign-extension will take care
|
|
|
|
// of high 32 bits, so use the sequence for signed int
|
|
|
|
CreateSETSWConst(target, (int32_t) C, dest, mvec);
|
|
|
|
} else if (C > lo32) {
|
|
|
|
// C does not fit in 32 bits
|
2003-05-31 07:32:01 +00:00
|
|
|
TmpInstruction* tmpReg = new TmpInstruction(mcfi, Type::IntTy);
|
2003-05-21 18:48:06 +00:00
|
|
|
CreateSETXConst(target, C, tmpReg, dest, mvec);
|
|
|
|
}
|
2001-10-18 00:01:48 +00:00
|
|
|
}
|
|
|
|
|
2002-07-10 21:39:50 +00:00
|
|
|
|
2002-08-13 18:04:08 +00:00
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
// Function: CreateIntSetInstruction
|
|
|
|
//
|
|
|
|
// Create code to Set a signed constant in the register `dest'.
|
|
|
|
// Really the same as CreateUIntSetInstruction.
|
|
|
|
//----------------------------------------------------------------------------
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
CreateIntSetInstruction(const TargetMachine& target,
|
|
|
|
int64_t C, Instruction* dest,
|
|
|
|
std::vector<MachineInstr*>& mvec,
|
|
|
|
MachineCodeForInstruction& mcfi)
|
|
|
|
{
|
|
|
|
CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
|
|
|
|
}
|
2002-08-09 20:08:06 +00:00
|
|
|
|
2001-10-18 00:01:48 +00:00
|
|
|
|
2002-09-16 15:56:01 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
// Create a table of LLVM opcode -> max. immediate constant likely to
|
|
|
|
// be usable for that operation.
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
|
|
// Entry == 0 ==> no immediate constant field exists at all.
|
|
|
|
// Entry > 0 ==> abs(immediate constant) <= Entry
|
|
|
|
//
|
2003-05-20 20:32:24 +00:00
|
|
|
std::vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
|
2002-09-16 15:56:01 +00:00
|
|
|
|
|
|
|
static int
|
|
|
|
MaxConstantForInstr(unsigned llvmOpCode)
|
|
|
|
{
|
|
|
|
int modelOpCode = -1;
|
|
|
|
|
2002-10-13 19:39:16 +00:00
|
|
|
if (llvmOpCode >= Instruction::BinaryOpsBegin &&
|
|
|
|
llvmOpCode < Instruction::BinaryOpsEnd)
|
2003-05-27 22:35:43 +00:00
|
|
|
modelOpCode = V9::ADDi;
|
2002-09-16 15:56:01 +00:00
|
|
|
else
|
|
|
|
switch(llvmOpCode) {
|
2003-05-27 22:35:43 +00:00
|
|
|
case Instruction::Ret: modelOpCode = V9::JMPLCALLi; break;
|
2002-09-16 15:56:01 +00:00
|
|
|
|
|
|
|
case Instruction::Malloc:
|
|
|
|
case Instruction::Alloca:
|
|
|
|
case Instruction::GetElementPtr:
|
2003-10-19 21:34:28 +00:00
|
|
|
case Instruction::PHI:
|
2002-09-16 15:56:01 +00:00
|
|
|
case Instruction::Cast:
|
2003-05-27 22:35:43 +00:00
|
|
|
case Instruction::Call: modelOpCode = V9::ADDi; break;
|
2002-09-16 15:56:01 +00:00
|
|
|
|
|
|
|
case Instruction::Shl:
|
2003-05-27 22:35:43 +00:00
|
|
|
case Instruction::Shr: modelOpCode = V9::SLLXi6; break;
|
2002-09-16 15:56:01 +00:00
|
|
|
|
|
|
|
default: break;
|
|
|
|
};
|
|
|
|
|
2004-02-25 18:44:15 +00:00
|
|
|
return (modelOpCode < 0)? 0: SparcV9MachineInstrDesc[modelOpCode].maxImmedConst;
|
2002-09-16 15:56:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
InitializeMaxConstantsTable()
|
|
|
|
{
|
|
|
|
unsigned op;
|
2002-10-13 19:39:16 +00:00
|
|
|
assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
|
2002-09-16 15:56:01 +00:00
|
|
|
"assignments below will be illegal!");
|
2002-10-13 19:39:16 +00:00
|
|
|
for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
|
2002-09-16 15:56:01 +00:00
|
|
|
MaxConstantsTable[op] = MaxConstantForInstr(op);
|
2002-10-13 19:39:16 +00:00
|
|
|
for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
|
2002-09-16 15:56:01 +00:00
|
|
|
MaxConstantsTable[op] = MaxConstantForInstr(op);
|
2002-10-13 19:39:16 +00:00
|
|
|
for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
|
2002-09-16 15:56:01 +00:00
|
|
|
MaxConstantsTable[op] = MaxConstantForInstr(op);
|
2002-10-13 19:39:16 +00:00
|
|
|
for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
|
2002-09-16 15:56:01 +00:00
|
|
|
MaxConstantsTable[op] = MaxConstantForInstr(op);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2001-10-18 00:01:48 +00:00
|
|
|
//---------------------------------------------------------------------------
|
2004-02-25 18:44:15 +00:00
|
|
|
// class SparcV9InstrInfo
|
2001-10-18 00:01:48 +00:00
|
|
|
//
|
|
|
|
// Purpose:
|
|
|
|
// Information about individual instructions.
|
2004-02-25 18:44:15 +00:00
|
|
|
// Most information is stored in the SparcV9MachineInstrDesc array above.
|
2001-10-18 00:01:48 +00:00
|
|
|
// Other information is computed on demand, and most such functions
|
2003-01-14 22:00:31 +00:00
|
|
|
// default to member functions in base class TargetInstrInfo.
|
2001-10-18 00:01:48 +00:00
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::SparcV9InstrInfo()
|
2004-02-29 06:31:44 +00:00
|
|
|
: TargetInstrInfo(SparcV9MachineInstrDesc, V9::NUM_TOTAL_OPCODES) {
|
2002-09-16 15:56:01 +00:00
|
|
|
InitializeMaxConstantsTable();
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
|
2002-09-16 15:56:01 +00:00
|
|
|
const Instruction* I) const
|
|
|
|
{
|
|
|
|
if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (isa<ConstantPointerNull>(CV)) // can always use %g0
|
|
|
|
return false;
|
|
|
|
|
2003-10-21 16:29:23 +00:00
|
|
|
if (isa<SwitchInst>(I)) // Switch instructions will be lowered!
|
|
|
|
return false;
|
|
|
|
|
2003-07-23 15:22:26 +00:00
|
|
|
if (const ConstantInt* CI = dyn_cast<ConstantInt>(CV))
|
|
|
|
return labs((int64_t)CI->getRawValue()) > MaxConstantsTable[I->getOpcode()];
|
2002-09-16 15:56:01 +00:00
|
|
|
|
|
|
|
if (isa<ConstantBool>(CV))
|
2003-07-23 15:22:26 +00:00
|
|
|
return 1 > MaxConstantsTable[I->getOpcode()];
|
2002-09-16 15:56:01 +00:00
|
|
|
|
|
|
|
return true;
|
2001-10-18 00:01:48 +00:00
|
|
|
}
|
|
|
|
|
2002-03-18 03:09:15 +00:00
|
|
|
//
|
2001-10-18 00:01:48 +00:00
|
|
|
// Create an instruction sequence to put the constant `val' into
|
2001-12-03 22:26:30 +00:00
|
|
|
// the virtual register `dest'. `val' may be a Constant or a
|
2001-10-18 00:01:48 +00:00
|
|
|
// GlobalValue, viz., the constant address of a global variable or function.
|
2002-05-19 15:25:51 +00:00
|
|
|
// The generated instructions are returned in `mvec'.
|
|
|
|
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
|
2002-10-28 00:28:31 +00:00
|
|
|
// Any stack space required is allocated via MachineFunction.
|
2001-10-18 00:01:48 +00:00
|
|
|
//
|
|
|
|
void
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
|
2003-12-17 22:04:00 +00:00
|
|
|
Function* F,
|
|
|
|
Value* val,
|
|
|
|
Instruction* dest,
|
|
|
|
std::vector<MachineInstr*>& mvec,
|
|
|
|
MachineCodeForInstruction& mcfi) const
|
2001-10-18 00:01:48 +00:00
|
|
|
{
|
2001-12-03 22:26:30 +00:00
|
|
|
assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
|
2001-10-18 00:01:48 +00:00
|
|
|
"I only know about constant values and global addresses");
|
|
|
|
|
2002-07-10 21:39:50 +00:00
|
|
|
// Use a "set" instruction for known constants or symbolic constants (labels)
|
|
|
|
// that can go in an integer reg.
|
|
|
|
// We have to use a "load" instruction for all other constants,
|
|
|
|
// in particular, floating point constants.
|
2001-10-18 00:01:48 +00:00
|
|
|
//
|
|
|
|
const Type* valType = val->getType();
|
|
|
|
|
2003-07-29 19:59:23 +00:00
|
|
|
// A ConstantPointerRef is just a reference to GlobalValue.
|
|
|
|
while (isa<ConstantPointerRef>(val))
|
2002-10-13 00:04:26 +00:00
|
|
|
val = cast<ConstantPointerRef>(val)->getValue();
|
|
|
|
|
2003-05-21 18:48:06 +00:00
|
|
|
if (isa<GlobalValue>(val)) {
|
2002-08-13 18:04:08 +00:00
|
|
|
TmpInstruction* tmpReg =
|
2003-05-31 07:32:01 +00:00
|
|
|
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
|
2002-08-13 18:04:08 +00:00
|
|
|
CreateSETXLabel(target, val, tmpReg, dest, mvec);
|
2003-07-29 19:59:23 +00:00
|
|
|
return;
|
|
|
|
}
|
2003-05-21 18:48:06 +00:00
|
|
|
|
2003-07-29 19:59:23 +00:00
|
|
|
bool isValid;
|
|
|
|
uint64_t C = ConvertConstantToIntType(target, val, dest->getType(), isValid);
|
|
|
|
if (isValid) {
|
|
|
|
if (dest->getType()->isSigned())
|
2003-05-21 18:48:06 +00:00
|
|
|
CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
|
2003-07-29 19:59:23 +00:00
|
|
|
else
|
|
|
|
CreateIntSetInstruction(target, (int64_t) C, dest, mvec, mcfi);
|
2003-05-21 18:48:06 +00:00
|
|
|
|
|
|
|
} else {
|
|
|
|
// Make an instruction sequence to load the constant, viz:
|
|
|
|
// SETX <addr-of-constant>, tmpReg, addrReg
|
|
|
|
// LOAD /*addr*/ addrReg, /*offset*/ 0, dest
|
2001-10-18 00:01:48 +00:00
|
|
|
|
2003-05-21 18:48:06 +00:00
|
|
|
// First, create a tmp register to be used by the SETX sequence.
|
|
|
|
TmpInstruction* tmpReg =
|
2003-11-07 17:29:48 +00:00
|
|
|
new TmpInstruction(mcfi, PointerType::get(val->getType()));
|
2001-10-28 21:41:46 +00:00
|
|
|
|
2003-05-21 18:48:06 +00:00
|
|
|
// Create another TmpInstruction for the address register
|
|
|
|
TmpInstruction* addrReg =
|
2003-11-07 17:29:48 +00:00
|
|
|
new TmpInstruction(mcfi, PointerType::get(val->getType()));
|
2003-07-29 19:59:23 +00:00
|
|
|
|
2003-11-07 17:29:48 +00:00
|
|
|
// Get the constant pool index for this constant
|
|
|
|
MachineConstantPool *CP = MachineFunction::get(F).getConstantPool();
|
|
|
|
Constant *C = cast<Constant>(val);
|
|
|
|
unsigned CPI = CP->getConstantPoolIndex(C);
|
|
|
|
|
|
|
|
// Put the address of the constant into a register
|
|
|
|
MachineInstr* MI;
|
|
|
|
|
|
|
|
MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(tmpReg);
|
|
|
|
MI->setOperandHi64(0);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
|
|
|
|
MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI)
|
|
|
|
.addRegDef(tmpReg);
|
|
|
|
MI->setOperandLo64(1);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
|
|
|
|
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
|
|
|
|
.addRegDef(tmpReg));
|
|
|
|
MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg);
|
|
|
|
MI->setOperandHi32(0);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
|
|
|
|
MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg).addRegDef(addrReg);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
|
|
|
|
MI = BuildMI(V9::ORi, 3).addReg(addrReg).addConstantPoolIndex(CPI)
|
|
|
|
.addRegDef(addrReg);
|
|
|
|
MI->setOperandLo32(1);
|
|
|
|
mvec.push_back(MI);
|
|
|
|
|
|
|
|
// Now load the constant from out ConstantPool label
|
2003-05-21 18:48:06 +00:00
|
|
|
unsigned Opcode = ChooseLoadInstruction(val->getType());
|
2003-06-03 03:20:57 +00:00
|
|
|
Opcode = convertOpcodeFromRegToImm(Opcode);
|
2003-11-07 17:29:48 +00:00
|
|
|
mvec.push_back(BuildMI(Opcode, 3)
|
|
|
|
.addReg(addrReg).addSImm((int64_t)0).addRegDef(dest));
|
2003-05-21 18:48:06 +00:00
|
|
|
}
|
2001-10-18 00:01:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2002-09-05 18:33:59 +00:00
|
|
|
// Create an instruction sequence to copy an integer register `val'
|
|
|
|
// to a floating point register `dest' by copying to memory and back.
|
2001-11-09 02:16:40 +00:00
|
|
|
// val must be an integral type. dest must be a Float or Double.
|
2002-05-19 15:25:51 +00:00
|
|
|
// The generated instructions are returned in `mvec'.
|
|
|
|
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
|
2002-10-28 00:28:31 +00:00
|
|
|
// Any stack space required is allocated via MachineFunction.
|
2001-11-08 04:57:53 +00:00
|
|
|
//
|
|
|
|
void
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
|
2002-05-19 15:25:51 +00:00
|
|
|
Function* F,
|
|
|
|
Value* val,
|
|
|
|
Instruction* dest,
|
2003-05-20 20:32:24 +00:00
|
|
|
std::vector<MachineInstr*>& mvec,
|
2002-05-19 15:25:51 +00:00
|
|
|
MachineCodeForInstruction& mcfi) const
|
2001-11-08 04:57:53 +00:00
|
|
|
{
|
2002-09-05 18:33:59 +00:00
|
|
|
assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
|
|
|
|
&& "Source type must be integral (integer or bool) or pointer");
|
2002-05-06 16:15:30 +00:00
|
|
|
assert(dest->getType()->isFloatingPoint()
|
2001-11-08 04:57:53 +00:00
|
|
|
&& "Dest type must be float/double");
|
2002-09-05 18:33:59 +00:00
|
|
|
|
|
|
|
// Get a stack slot to use for the copy
|
2002-12-28 20:18:21 +00:00
|
|
|
int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
|
2002-09-05 18:33:59 +00:00
|
|
|
|
|
|
|
// Get the size of the source value being copied.
|
2002-12-28 20:18:21 +00:00
|
|
|
size_t srcSize = target.getTargetData().getTypeSize(val->getType());
|
2002-09-05 18:33:59 +00:00
|
|
|
|
2001-11-08 04:57:53 +00:00
|
|
|
// Store instruction stores `val' to [%fp+offset].
|
2002-09-05 18:33:59 +00:00
|
|
|
// The store and load opCodes are based on the size of the source value.
|
|
|
|
// If the value is smaller than 32 bits, we must sign- or zero-extend it
|
|
|
|
// to 32 bits since the load-float will load 32 bits.
|
2002-07-31 21:13:31 +00:00
|
|
|
// Note that the store instruction is the same for signed and unsigned ints.
|
2002-09-05 18:33:59 +00:00
|
|
|
const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
|
|
|
|
Value* storeVal = val;
|
2003-05-21 18:48:06 +00:00
|
|
|
if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
|
|
|
|
// sign- or zero-extend respectively
|
2003-05-31 07:32:01 +00:00
|
|
|
storeVal = new TmpInstruction(mcfi, storeType, val);
|
2003-05-21 18:48:06 +00:00
|
|
|
if (val->getType()->isSigned())
|
|
|
|
CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
|
|
|
|
mvec, mcfi);
|
|
|
|
else
|
|
|
|
CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
|
|
|
|
mvec, mcfi);
|
|
|
|
}
|
2003-01-15 19:23:34 +00:00
|
|
|
|
|
|
|
unsigned FPReg = target.getRegInfo().getFramePointer();
|
2003-06-03 03:20:57 +00:00
|
|
|
unsigned StoreOpcode = ChooseStoreInstruction(storeType);
|
|
|
|
StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
|
|
|
|
mvec.push_back(BuildMI(StoreOpcode, 3)
|
2003-01-15 19:23:34 +00:00
|
|
|
.addReg(storeVal).addMReg(FPReg).addSImm(offset));
|
2001-10-18 00:01:48 +00:00
|
|
|
|
2001-11-08 04:57:53 +00:00
|
|
|
// Load instruction loads [%fp+offset] to `dest'.
|
2002-09-05 18:33:59 +00:00
|
|
|
// The type of the load opCode is the floating point type that matches the
|
|
|
|
// stored type in size:
|
|
|
|
// On SparcV9: float for int or smaller, double for long.
|
2001-11-09 02:16:40 +00:00
|
|
|
//
|
2002-09-05 18:33:59 +00:00
|
|
|
const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
|
2003-06-03 03:20:57 +00:00
|
|
|
unsigned LoadOpcode = ChooseLoadInstruction(loadType);
|
|
|
|
LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
|
|
|
|
mvec.push_back(BuildMI(LoadOpcode, 3)
|
2003-01-15 19:23:34 +00:00
|
|
|
.addMReg(FPReg).addSImm(offset).addRegDef(dest));
|
2001-11-09 02:16:40 +00:00
|
|
|
}
|
|
|
|
|
2002-09-05 18:33:59 +00:00
|
|
|
// Similarly, create an instruction sequence to copy an FP register
|
|
|
|
// `val' to an integer register `dest' by copying to memory and back.
|
2002-05-19 15:25:51 +00:00
|
|
|
// The generated instructions are returned in `mvec'.
|
2003-05-31 07:32:01 +00:00
|
|
|
// Any temp. virtual registers (TmpInstruction) created are recorded in mcfi.
|
|
|
|
// Temporary stack space required is allocated via MachineFunction.
|
2001-11-09 02:16:40 +00:00
|
|
|
//
|
|
|
|
void
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
|
2002-05-19 15:25:51 +00:00
|
|
|
Function* F,
|
2002-01-20 22:54:45 +00:00
|
|
|
Value* val,
|
|
|
|
Instruction* dest,
|
2003-05-20 20:32:24 +00:00
|
|
|
std::vector<MachineInstr*>& mvec,
|
2002-05-19 15:25:51 +00:00
|
|
|
MachineCodeForInstruction& mcfi) const
|
2001-11-09 02:16:40 +00:00
|
|
|
{
|
2002-07-31 21:13:31 +00:00
|
|
|
const Type* opTy = val->getType();
|
|
|
|
const Type* destTy = dest->getType();
|
2002-09-05 18:33:59 +00:00
|
|
|
|
2002-07-31 21:13:31 +00:00
|
|
|
assert(opTy->isFloatingPoint() && "Source type must be float/double");
|
2002-09-05 18:33:59 +00:00
|
|
|
assert((destTy->isIntegral() || isa<PointerType>(destTy))
|
|
|
|
&& "Dest type must be integer, bool or pointer");
|
2002-07-31 21:13:31 +00:00
|
|
|
|
2003-05-31 07:32:01 +00:00
|
|
|
// FIXME: For now, we allocate permanent space because the stack frame
|
|
|
|
// manager does not allow locals to be allocated (e.g., for alloca) after
|
|
|
|
// a temp is allocated!
|
|
|
|
//
|
2002-12-28 20:18:21 +00:00
|
|
|
int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
|
2002-09-05 18:33:59 +00:00
|
|
|
|
2003-01-15 19:23:34 +00:00
|
|
|
unsigned FPReg = target.getRegInfo().getFramePointer();
|
|
|
|
|
2001-11-09 02:16:40 +00:00
|
|
|
// Store instruction stores `val' to [%fp+offset].
|
2002-07-31 21:13:31 +00:00
|
|
|
// The store opCode is based only the source value being copied.
|
2001-11-09 02:16:40 +00:00
|
|
|
//
|
2003-06-03 03:20:57 +00:00
|
|
|
unsigned StoreOpcode = ChooseStoreInstruction(opTy);
|
|
|
|
StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
|
|
|
|
mvec.push_back(BuildMI(StoreOpcode, 3)
|
2003-01-15 19:23:34 +00:00
|
|
|
.addReg(val).addMReg(FPReg).addSImm(offset));
|
2002-09-05 18:33:59 +00:00
|
|
|
|
2001-11-09 02:16:40 +00:00
|
|
|
// Load instruction loads [%fp+offset] to `dest'.
|
2002-07-31 21:13:31 +00:00
|
|
|
// The type of the load opCode is the integer type that matches the
|
2002-09-05 18:33:59 +00:00
|
|
|
// source type in size:
|
2002-07-31 21:13:31 +00:00
|
|
|
// On SparcV9: int for float, long for double.
|
|
|
|
// Note that we *must* use signed loads even for unsigned dest types, to
|
2002-09-05 18:33:59 +00:00
|
|
|
// ensure correct sign-extension for UByte, UShort or UInt:
|
|
|
|
//
|
|
|
|
const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
|
2003-06-03 03:20:57 +00:00
|
|
|
unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
|
|
|
|
LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
|
|
|
|
mvec.push_back(BuildMI(LoadOpcode, 3).addMReg(FPReg)
|
2003-01-15 19:23:34 +00:00
|
|
|
.addSImm(offset).addRegDef(dest));
|
2002-05-19 15:25:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Create instruction(s) to copy src to dest, for arbitrary types
|
|
|
|
// The generated instructions are returned in `mvec'.
|
|
|
|
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
|
2002-10-28 00:28:31 +00:00
|
|
|
// Any stack space required is allocated via MachineFunction.
|
2002-05-19 15:25:51 +00:00
|
|
|
//
|
|
|
|
void
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
|
2003-12-17 22:04:00 +00:00
|
|
|
Function *F,
|
|
|
|
Value* src,
|
|
|
|
Instruction* dest,
|
|
|
|
std::vector<MachineInstr*>& mvec,
|
2002-05-19 15:25:51 +00:00
|
|
|
MachineCodeForInstruction& mcfi) const
|
|
|
|
{
|
|
|
|
bool loadConstantToReg = false;
|
|
|
|
|
|
|
|
const Type* resultType = dest->getType();
|
|
|
|
|
|
|
|
MachineOpCode opCode = ChooseAddInstructionByType(resultType);
|
2003-05-21 18:48:06 +00:00
|
|
|
if (opCode == V9::INVALID_OPCODE) {
|
2003-05-20 20:32:24 +00:00
|
|
|
assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
|
|
|
|
return;
|
|
|
|
}
|
2002-05-19 15:25:51 +00:00
|
|
|
|
|
|
|
// if `src' is a constant that doesn't fit in the immed field or if it is
|
|
|
|
// a global variable (i.e., a constant address), generate a load
|
|
|
|
// instruction instead of an add
|
|
|
|
//
|
2003-05-21 18:48:06 +00:00
|
|
|
if (isa<Constant>(src)) {
|
2003-05-20 20:32:24 +00:00
|
|
|
unsigned int machineRegNum;
|
|
|
|
int64_t immedValue;
|
|
|
|
MachineOperand::MachineOperandType opType =
|
|
|
|
ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
|
|
|
|
machineRegNum, immedValue);
|
2002-05-19 15:25:51 +00:00
|
|
|
|
2003-05-20 20:32:24 +00:00
|
|
|
if (opType == MachineOperand::MO_VirtualRegister)
|
|
|
|
loadConstantToReg = true;
|
|
|
|
}
|
2002-05-19 15:25:51 +00:00
|
|
|
else if (isa<GlobalValue>(src))
|
|
|
|
loadConstantToReg = true;
|
|
|
|
|
2003-05-21 18:48:06 +00:00
|
|
|
if (loadConstantToReg) {
|
|
|
|
// `src' is constant and cannot fit in immed field for the ADD
|
2003-05-20 20:32:24 +00:00
|
|
|
// Insert instructions to "load" the constant into a register
|
|
|
|
target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
|
|
|
|
mvec, mcfi);
|
2003-05-21 18:48:06 +00:00
|
|
|
} else {
|
2003-05-31 07:32:01 +00:00
|
|
|
// Create a reg-to-reg copy instruction for the given type:
|
|
|
|
// -- For FP values, create a FMOVS or FMOVD instruction
|
|
|
|
// -- For non-FP values, create an add-with-0 instruction (opCode as above)
|
|
|
|
// Make `src' the second operand, in case it is a small constant!
|
2003-05-20 20:32:24 +00:00
|
|
|
//
|
2003-05-31 07:32:01 +00:00
|
|
|
MachineInstr* MI;
|
|
|
|
if (resultType->isFloatingPoint())
|
|
|
|
MI = (BuildMI(resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
|
|
|
|
.addReg(src).addRegDef(dest));
|
|
|
|
else {
|
|
|
|
const Type* Ty =isa<PointerType>(resultType)? Type::ULongTy :resultType;
|
|
|
|
MI = (BuildMI(opCode, 3)
|
|
|
|
.addSImm((int64_t) 0).addReg(src).addRegDef(dest));
|
|
|
|
}
|
2003-05-20 20:32:24 +00:00
|
|
|
mvec.push_back(MI);
|
|
|
|
}
|
2002-05-19 15:25:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2002-09-05 18:33:59 +00:00
|
|
|
// Helper function for sign-extension and zero-extension.
|
|
|
|
// For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
|
|
|
|
inline void
|
|
|
|
CreateBitExtensionInstructions(bool signExtend,
|
|
|
|
const TargetMachine& target,
|
|
|
|
Function* F,
|
|
|
|
Value* srcVal,
|
2002-09-27 14:29:45 +00:00
|
|
|
Value* destVal,
|
|
|
|
unsigned int numLowBits,
|
2003-05-20 20:32:24 +00:00
|
|
|
std::vector<MachineInstr*>& mvec,
|
2002-09-05 18:33:59 +00:00
|
|
|
MachineCodeForInstruction& mcfi)
|
|
|
|
{
|
|
|
|
MachineInstr* M;
|
|
|
|
|
2002-09-27 14:29:45 +00:00
|
|
|
assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
|
|
|
|
|
2003-05-21 18:48:06 +00:00
|
|
|
if (numLowBits < 32) {
|
|
|
|
// SLL is needed since operand size is < 32 bits.
|
2003-05-31 07:32:01 +00:00
|
|
|
TmpInstruction *tmpI = new TmpInstruction(mcfi, destVal->getType(),
|
2003-05-20 20:32:24 +00:00
|
|
|
srcVal, destVal, "make32");
|
2003-05-27 22:35:43 +00:00
|
|
|
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(srcVal)
|
2003-05-20 20:32:24 +00:00
|
|
|
.addZImm(32-numLowBits).addRegDef(tmpI));
|
|
|
|
srcVal = tmpI;
|
|
|
|
}
|
2002-09-05 18:33:59 +00:00
|
|
|
|
2003-06-06 09:52:23 +00:00
|
|
|
mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
|
2003-05-20 20:32:24 +00:00
|
|
|
.addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
|
2002-09-05 18:33:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2002-05-19 15:25:51 +00:00
|
|
|
// Create instruction sequence to produce a sign-extended register value
|
2002-09-05 18:33:59 +00:00
|
|
|
// from an arbitrary-sized integer value (sized in bits, not bytes).
|
2002-05-19 15:25:51 +00:00
|
|
|
// The generated instructions are returned in `mvec'.
|
|
|
|
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
|
2002-10-28 00:28:31 +00:00
|
|
|
// Any stack space required is allocated via MachineFunction.
|
2002-05-19 15:25:51 +00:00
|
|
|
//
|
|
|
|
void
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::CreateSignExtensionInstructions(
|
2002-05-19 15:25:51 +00:00
|
|
|
const TargetMachine& target,
|
|
|
|
Function* F,
|
2002-09-05 18:33:59 +00:00
|
|
|
Value* srcVal,
|
2002-09-27 14:29:45 +00:00
|
|
|
Value* destVal,
|
|
|
|
unsigned int numLowBits,
|
2003-05-20 20:32:24 +00:00
|
|
|
std::vector<MachineInstr*>& mvec,
|
2002-05-19 15:25:51 +00:00
|
|
|
MachineCodeForInstruction& mcfi) const
|
|
|
|
{
|
2002-09-05 18:33:59 +00:00
|
|
|
CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
|
2002-09-27 14:29:45 +00:00
|
|
|
destVal, numLowBits, mvec, mcfi);
|
2002-09-05 18:33:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Create instruction sequence to produce a zero-extended register value
|
|
|
|
// from an arbitrary-sized integer value (sized in bits, not bytes).
|
|
|
|
// For SPARC v9, we sign-extend the given operand using SLL; SRL.
|
|
|
|
// The generated instructions are returned in `mvec'.
|
|
|
|
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
|
2002-10-28 00:28:31 +00:00
|
|
|
// Any stack space required is allocated via MachineFunction.
|
2002-09-05 18:33:59 +00:00
|
|
|
//
|
|
|
|
void
|
2004-02-25 18:44:15 +00:00
|
|
|
SparcV9InstrInfo::CreateZeroExtensionInstructions(
|
2002-09-05 18:33:59 +00:00
|
|
|
const TargetMachine& target,
|
|
|
|
Function* F,
|
|
|
|
Value* srcVal,
|
2002-09-27 14:29:45 +00:00
|
|
|
Value* destVal,
|
|
|
|
unsigned int numLowBits,
|
2003-05-20 20:32:24 +00:00
|
|
|
std::vector<MachineInstr*>& mvec,
|
2002-09-05 18:33:59 +00:00
|
|
|
MachineCodeForInstruction& mcfi) const
|
|
|
|
{
|
|
|
|
CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
|
2002-09-27 14:29:45 +00:00
|
|
|
destVal, numLowBits, mvec, mcfi);
|
2001-11-08 04:57:53 +00:00
|
|
|
}
|
2003-11-11 22:41:34 +00:00
|
|
|
|
|
|
|
} // End llvm namespace
|