2003-01-13 20:01:16 +00:00
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//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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2005-04-21 22:36:52 +00:00
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//
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2003-10-20 19:43:21 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 22:36:52 +00:00
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//
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2003-10-20 19:43:21 +00:00
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//===----------------------------------------------------------------------===//
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2005-04-21 22:36:52 +00:00
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//
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2003-05-07 20:08:36 +00:00
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// This file implements the LiveVariable analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using are sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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2003-01-13 20:01:16 +00:00
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-08-04 23:54:43 +00:00
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#include "llvm/CodeGen/Passes.h"
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2010-01-04 23:02:10 +00:00
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#include "llvm/Support/Debug.h"
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2003-01-14 22:00:31 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2003-01-13 20:01:16 +00:00
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#include "llvm/Target/TargetMachine.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/ADT/DepthFirstIterator.h"
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2007-06-27 05:23:00 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2008-06-27 07:05:59 +00:00
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#include "llvm/ADT/SmallSet.h"
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2004-09-01 22:55:40 +00:00
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#include "llvm/ADT/STLExtras.h"
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2005-08-24 00:09:33 +00:00
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#include <algorithm>
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2004-01-30 22:08:53 +00:00
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using namespace llvm;
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2003-11-11 22:41:34 +00:00
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2007-05-03 01:11:54 +00:00
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char LiveVariables::ID = 0;
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2010-10-12 19:48:12 +00:00
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INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
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"Live Variable Analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
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INITIALIZE_PASS_END(LiveVariables, "livevars",
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2010-10-07 22:25:06 +00:00
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"Live Variable Analysis", false, false)
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2003-01-13 20:01:16 +00:00
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2008-08-04 23:54:43 +00:00
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void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequiredID(UnreachableMachineBlockElimID);
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AU.setPreservesAll();
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2009-07-31 18:16:33 +00:00
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MachineFunctionPass::getAnalysisUsage(AU);
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2008-08-04 23:54:43 +00:00
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}
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2009-11-10 22:01:05 +00:00
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MachineInstr *
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LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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if (Kills[i]->getParent() == MBB)
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return Kills[i];
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return NULL;
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}
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2006-01-04 05:40:30 +00:00
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void LiveVariables::VarInfo::dump() const {
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2010-01-04 23:02:10 +00:00
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dbgs() << " Alive in blocks: ";
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2009-05-26 18:27:15 +00:00
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for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
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E = AliveBlocks.end(); I != E; ++I)
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2010-01-04 23:02:10 +00:00
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dbgs() << *I << ", ";
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dbgs() << "\n Killed by:";
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2006-01-04 05:40:30 +00:00
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if (Kills.empty())
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2010-01-04 23:02:10 +00:00
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dbgs() << " No instructions.\n";
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2006-01-04 05:40:30 +00:00
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else {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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2010-01-04 23:02:10 +00:00
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dbgs() << "\n #" << i << ": " << *Kills[i];
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dbgs() << "\n";
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2006-01-04 05:40:30 +00:00
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}
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}
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2008-02-20 06:10:21 +00:00
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/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
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2003-05-12 14:24:00 +00:00
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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2008-02-10 18:45:23 +00:00
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assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
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2003-05-12 14:24:00 +00:00
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"getVarInfo: not a virtual register!");
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2011-01-08 23:10:57 +00:00
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VirtRegInfo.grow(RegIdx);
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2009-05-26 18:27:15 +00:00
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return VirtRegInfo[RegIdx];
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2003-05-12 14:24:00 +00:00
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}
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2008-01-15 22:58:11 +00:00
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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MachineBasicBlock *DefBlock,
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2007-05-08 19:00:00 +00:00
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MachineBasicBlock *MBB,
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std::vector<MachineBasicBlock*> &WorkList) {
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2004-07-01 04:29:47 +00:00
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unsigned BBNum = MBB->getNumber();
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2008-01-15 22:02:46 +00:00
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2003-01-13 20:01:16 +00:00
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// Check to see if this basic block is one of the killing blocks. If so,
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2008-02-20 06:10:21 +00:00
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// remove it.
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2003-01-13 20:01:16 +00:00
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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2004-07-19 07:04:55 +00:00
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if (VRInfo.Kills[i]->getParent() == MBB) {
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2003-01-13 20:01:16 +00:00
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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2008-01-15 22:02:46 +00:00
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2008-01-15 22:58:11 +00:00
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if (MBB == DefBlock) return; // Terminate recursion
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2003-01-13 20:01:16 +00:00
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2009-05-26 18:27:15 +00:00
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if (VRInfo.AliveBlocks.test(BBNum))
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2003-01-13 20:01:16 +00:00
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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2009-05-26 18:27:15 +00:00
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VRInfo.AliveBlocks.set(BBNum);
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2003-01-13 20:01:16 +00:00
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2007-05-08 19:00:00 +00:00
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for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
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E = MBB->pred_rend(); PI != E; ++PI)
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WorkList.push_back(*PI);
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2003-01-13 20:01:16 +00:00
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}
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2008-02-20 07:36:31 +00:00
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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2008-01-15 22:58:11 +00:00
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MachineBasicBlock *DefBlock,
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2007-05-08 19:00:00 +00:00
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MachineBasicBlock *MBB) {
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std::vector<MachineBasicBlock*> WorkList;
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2008-01-15 22:58:11 +00:00
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
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2008-02-20 07:36:31 +00:00
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2007-05-08 19:00:00 +00:00
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while (!WorkList.empty()) {
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MachineBasicBlock *Pred = WorkList.back();
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WorkList.pop_back();
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2008-01-15 22:58:11 +00:00
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
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2007-05-08 19:00:00 +00:00
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}
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}
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2008-01-15 22:02:46 +00:00
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void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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2004-06-24 21:31:16 +00:00
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MachineInstr *MI) {
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2008-04-02 18:04:08 +00:00
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assert(MRI->getVRegDef(reg) && "Register use before def!");
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2004-09-01 22:34:52 +00:00
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2007-11-08 01:20:48 +00:00
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unsigned BBNum = MBB->getNumber();
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2008-01-15 22:02:46 +00:00
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VarInfo& VRInfo = getVarInfo(reg);
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2007-04-17 20:22:11 +00:00
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VRInfo.NumUses++;
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2007-03-17 09:29:54 +00:00
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2008-02-20 06:10:21 +00:00
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// Check to see if this basic block is already a kill block.
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2004-07-19 07:04:55 +00:00
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
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2008-02-20 06:10:21 +00:00
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// Yes, this register is killed in this basic block already. Increase the
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2003-01-13 20:01:16 +00:00
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// live range by updating the kill instruction.
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2004-07-19 07:04:55 +00:00
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VRInfo.Kills.back() = MI;
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2003-01-13 20:01:16 +00:00
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return;
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}
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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2004-07-19 07:04:55 +00:00
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assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
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2003-01-13 20:01:16 +00:00
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#endif
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2008-06-23 23:41:14 +00:00
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// This situation can occur:
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//
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// ,------.
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// | |
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// | v
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// | t2 = phi ... t1 ...
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// | |
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// | v
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// | t1 = ...
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// | ... = ... t1 ...
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// | |
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// `------'
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//
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// where there is a use in a PHI node that's a predecessor to the defining
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// block. We don't want to mark all predecessors as having the value "alive"
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// in this case.
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if (MBB == MRI->getVRegDef(reg)->getParent()) return;
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2003-01-13 20:01:16 +00:00
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2008-02-20 06:10:21 +00:00
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// Add a new kill entry for this basic block. If this virtual register is
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// already marked as alive in this basic block, that means it is alive in at
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// least one of the successor blocks, it's not a kill.
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2009-05-26 18:27:15 +00:00
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if (!VRInfo.AliveBlocks.test(BBNum))
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2007-03-09 09:48:56 +00:00
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VRInfo.Kills.push_back(MI);
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2003-01-13 20:01:16 +00:00
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2008-02-20 07:36:31 +00:00
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// Update all dominating blocks to mark them as "known live".
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2004-05-01 21:24:24 +00:00
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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2008-04-02 18:04:08 +00:00
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MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
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2003-01-13 20:01:16 +00:00
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}
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2008-09-21 21:11:41 +00:00
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void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
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VarInfo &VRInfo = getVarInfo(Reg);
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2009-05-26 18:27:15 +00:00
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if (VRInfo.AliveBlocks.empty())
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2008-09-21 21:11:41 +00:00
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// If vr is not alive in any block, then defaults to dead.
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VRInfo.Kills.push_back(MI);
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}
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2008-04-16 09:46:40 +00:00
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/// FindLastPartialDef - Return the last partial def of the specified register.
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2009-09-22 08:34:46 +00:00
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/// Also returns the sub-registers that're defined by the instruction.
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2008-04-16 09:46:40 +00:00
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MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
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2009-09-22 08:34:46 +00:00
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SmallSet<unsigned,4> &PartDefRegs) {
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2008-04-16 09:46:40 +00:00
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unsigned LastDefReg = 0;
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unsigned LastDefDist = 0;
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MachineInstr *LastDef = NULL;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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MachineInstr *Def = PhysRegDef[SubReg];
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if (!Def)
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continue;
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unsigned Dist = DistanceMap[Def];
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if (Dist > LastDefDist) {
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LastDefReg = SubReg;
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LastDef = Def;
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LastDefDist = Dist;
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}
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}
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2009-09-22 08:34:46 +00:00
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if (!LastDef)
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return 0;
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PartDefRegs.insert(LastDefReg);
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for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = LastDef->getOperand(i);
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if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
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continue;
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unsigned DefReg = MO.getReg();
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if (TRI->isSubRegister(Reg, DefReg)) {
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PartDefRegs.insert(DefReg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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PartDefRegs.insert(SubReg);
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}
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}
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2008-04-16 09:46:40 +00:00
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return LastDef;
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}
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2008-02-20 09:15:16 +00:00
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/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
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/// implicit defs to a machine instruction if there was an earlier def of its
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/// super-register.
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2003-01-13 20:01:16 +00:00
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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2009-11-13 20:36:40 +00:00
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MachineInstr *LastDef = PhysRegDef[Reg];
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2008-04-16 09:46:40 +00:00
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// If there was a previous use or a "full" def all is well.
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2009-11-13 20:36:40 +00:00
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if (!LastDef && !PhysRegUse[Reg]) {
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2008-04-16 09:46:40 +00:00
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// Otherwise, the last sub-register def implicitly defines this register.
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// e.g.
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// AH =
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// AL = ... <imp-def EAX>, <imp-kill AH>
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// = AH
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// ...
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// = EAX
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// All of the sub-registers must have been defined before the use of Reg!
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2009-09-22 08:34:46 +00:00
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SmallSet<unsigned, 4> PartDefRegs;
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MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
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2008-04-16 09:46:40 +00:00
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// If LastPartialDef is NULL, it must be using a livein register.
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if (LastPartialDef) {
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LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
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true/*IsImp*/));
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PhysRegDef[Reg] = LastPartialDef;
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2008-08-14 23:41:38 +00:00
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SmallSet<unsigned, 8> Processed;
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2008-04-16 09:46:40 +00:00
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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if (Processed.count(SubReg))
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continue;
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2009-09-22 08:34:46 +00:00
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if (PartDefRegs.count(SubReg))
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2008-04-16 09:46:40 +00:00
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continue;
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// This part of Reg was defined before the last partial def. It's killed
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// here.
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LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
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false/*IsDef*/,
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true/*IsImp*/));
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PhysRegDef[SubReg] = LastPartialDef;
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for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
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Processed.insert(*SS);
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}
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}
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2007-04-25 07:30:23 +00:00
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}
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2009-11-13 20:36:40 +00:00
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else if (LastDef && !PhysRegUse[Reg] &&
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!LastDef->findRegisterDefOperand(Reg))
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|
|
// Last def defines the super register, add an implicit def of reg.
|
|
|
|
LastDef->addOperand(MachineOperand::CreateReg(Reg,
|
|
|
|
true/*IsDef*/, true/*IsImp*/));
|
2008-02-20 06:10:21 +00:00
|
|
|
|
2008-04-16 09:46:40 +00:00
|
|
|
// Remember this use.
|
|
|
|
PhysRegUse[Reg] = MI;
|
2008-03-05 00:59:57 +00:00
|
|
|
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
2008-02-20 07:36:31 +00:00
|
|
|
unsigned SubReg = *SubRegs; ++SubRegs)
|
2008-04-16 09:46:40 +00:00
|
|
|
PhysRegUse[SubReg] = MI;
|
2007-06-26 21:03:35 +00:00
|
|
|
}
|
|
|
|
|
2009-12-01 00:44:45 +00:00
|
|
|
/// FindLastRefOrPartRef - Return the last reference or partial reference of
|
|
|
|
/// the specified register.
|
|
|
|
MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
|
|
|
|
MachineInstr *LastDef = PhysRegDef[Reg];
|
|
|
|
MachineInstr *LastUse = PhysRegUse[Reg];
|
|
|
|
if (!LastDef && !LastUse)
|
2010-06-14 18:28:34 +00:00
|
|
|
return 0;
|
2009-12-01 00:44:45 +00:00
|
|
|
|
|
|
|
MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
|
|
|
|
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
|
|
|
|
unsigned LastPartDefDist = 0;
|
|
|
|
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
|
|
|
unsigned SubReg = *SubRegs; ++SubRegs) {
|
|
|
|
MachineInstr *Def = PhysRegDef[SubReg];
|
|
|
|
if (Def && Def != LastDef) {
|
|
|
|
// There was a def of this sub-register in between. This is a partial
|
|
|
|
// def, keep track of the last one.
|
|
|
|
unsigned Dist = DistanceMap[Def];
|
2010-01-07 17:29:08 +00:00
|
|
|
if (Dist > LastPartDefDist)
|
2009-12-01 00:44:45 +00:00
|
|
|
LastPartDefDist = Dist;
|
2010-01-07 17:29:08 +00:00
|
|
|
} else if (MachineInstr *Use = PhysRegUse[SubReg]) {
|
2009-12-01 00:44:45 +00:00
|
|
|
unsigned Dist = DistanceMap[Use];
|
|
|
|
if (Dist > LastRefOrPartRefDist) {
|
|
|
|
LastRefOrPartRefDist = Dist;
|
|
|
|
LastRefOrPartRef = Use;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return LastRefOrPartRef;
|
|
|
|
}
|
|
|
|
|
2009-01-20 21:25:12 +00:00
|
|
|
bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
|
2009-09-24 02:15:22 +00:00
|
|
|
MachineInstr *LastDef = PhysRegDef[Reg];
|
|
|
|
MachineInstr *LastUse = PhysRegUse[Reg];
|
|
|
|
if (!LastDef && !LastUse)
|
2008-04-16 09:46:40 +00:00
|
|
|
return false;
|
|
|
|
|
2009-09-24 02:15:22 +00:00
|
|
|
MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
|
2008-04-16 09:46:40 +00:00
|
|
|
unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
|
|
|
|
// The whole register is used.
|
|
|
|
// AL =
|
|
|
|
// AH =
|
|
|
|
//
|
|
|
|
// = AX
|
|
|
|
// = AL, AX<imp-use, kill>
|
|
|
|
// AX =
|
|
|
|
//
|
|
|
|
// Or whole register is defined, but not used at all.
|
|
|
|
// AX<dead> =
|
|
|
|
// ...
|
|
|
|
// AX =
|
|
|
|
//
|
|
|
|
// Or whole register is defined, but only partly used.
|
|
|
|
// AX<dead> = AL<imp-def>
|
|
|
|
// = AL<kill>
|
|
|
|
// AX =
|
2009-09-24 02:15:22 +00:00
|
|
|
MachineInstr *LastPartDef = 0;
|
|
|
|
unsigned LastPartDefDist = 0;
|
2008-08-14 23:41:38 +00:00
|
|
|
SmallSet<unsigned, 8> PartUses;
|
2008-04-16 09:46:40 +00:00
|
|
|
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
|
|
|
unsigned SubReg = *SubRegs; ++SubRegs) {
|
2009-09-24 02:15:22 +00:00
|
|
|
MachineInstr *Def = PhysRegDef[SubReg];
|
|
|
|
if (Def && Def != LastDef) {
|
|
|
|
// There was a def of this sub-register in between. This is a partial
|
|
|
|
// def, keep track of the last one.
|
|
|
|
unsigned Dist = DistanceMap[Def];
|
|
|
|
if (Dist > LastPartDefDist) {
|
|
|
|
LastPartDefDist = Dist;
|
|
|
|
LastPartDef = Def;
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
2008-04-16 09:46:40 +00:00
|
|
|
if (MachineInstr *Use = PhysRegUse[SubReg]) {
|
|
|
|
PartUses.insert(SubReg);
|
|
|
|
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
|
|
|
|
PartUses.insert(*SS);
|
|
|
|
unsigned Dist = DistanceMap[Use];
|
|
|
|
if (Dist > LastRefOrPartRefDist) {
|
|
|
|
LastRefOrPartRefDist = Dist;
|
|
|
|
LastRefOrPartRef = Use;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2009-01-20 21:25:12 +00:00
|
|
|
|
2010-03-05 21:49:17 +00:00
|
|
|
if (!PhysRegUse[Reg]) {
|
2009-09-24 02:15:22 +00:00
|
|
|
// Partial uses. Mark register def dead and add implicit def of
|
|
|
|
// sub-registers which are used.
|
|
|
|
// EAX<dead> = op AL<imp-def>
|
|
|
|
// That is, EAX def is dead but AL def extends pass it.
|
2008-04-16 09:46:40 +00:00
|
|
|
PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
|
|
|
|
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
|
|
|
unsigned SubReg = *SubRegs; ++SubRegs) {
|
2009-09-24 02:15:22 +00:00
|
|
|
if (!PartUses.count(SubReg))
|
|
|
|
continue;
|
|
|
|
bool NeedDef = true;
|
|
|
|
if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
|
|
|
|
MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
|
|
|
|
if (MO) {
|
|
|
|
NeedDef = false;
|
|
|
|
assert(!MO->isDead());
|
2009-07-06 21:34:05 +00:00
|
|
|
}
|
2008-04-16 09:46:40 +00:00
|
|
|
}
|
2009-09-24 02:15:22 +00:00
|
|
|
if (NeedDef)
|
|
|
|
PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
|
|
|
|
true/*IsDef*/, true/*IsImp*/));
|
2009-12-01 00:44:45 +00:00
|
|
|
MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
|
|
|
|
if (LastSubRef)
|
|
|
|
LastSubRef->addRegisterKilled(SubReg, TRI, true);
|
|
|
|
else {
|
|
|
|
LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
|
|
|
|
PhysRegUse[SubReg] = LastRefOrPartRef;
|
|
|
|
for (const unsigned *SSRegs = TRI->getSubRegisters(SubReg);
|
|
|
|
unsigned SSReg = *SSRegs; ++SSRegs)
|
|
|
|
PhysRegUse[SSReg] = LastRefOrPartRef;
|
|
|
|
}
|
2009-09-24 02:15:22 +00:00
|
|
|
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
|
|
|
|
PartUses.erase(*SS);
|
2008-04-16 09:46:40 +00:00
|
|
|
}
|
2010-03-05 21:49:17 +00:00
|
|
|
} else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
|
|
|
|
if (LastPartDef)
|
|
|
|
// The last partial def kills the register.
|
|
|
|
LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
|
|
|
|
true/*IsImp*/, true/*IsKill*/));
|
|
|
|
else {
|
|
|
|
MachineOperand *MO =
|
|
|
|
LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
|
|
|
|
bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
|
|
|
|
// If the last reference is the last def, then it's not used at all.
|
|
|
|
// That is, unless we are currently processing the last reference itself.
|
|
|
|
LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
|
|
|
|
if (NeedEC) {
|
|
|
|
// If we are adding a subreg def and the superreg def is marked early
|
|
|
|
// clobber, add an early clobber marker to the subreg def.
|
|
|
|
MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
|
|
|
|
if (MO)
|
|
|
|
MO->setIsEarlyClobber();
|
|
|
|
}
|
|
|
|
}
|
2009-09-24 02:15:22 +00:00
|
|
|
} else
|
2008-04-16 09:46:40 +00:00
|
|
|
LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-09-23 06:28:31 +00:00
|
|
|
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
|
2009-09-24 02:15:22 +00:00
|
|
|
SmallVector<unsigned, 4> &Defs) {
|
2008-04-16 09:46:40 +00:00
|
|
|
// What parts of the register are previously defined?
|
2008-06-27 07:05:59 +00:00
|
|
|
SmallSet<unsigned, 32> Live;
|
2008-04-16 09:46:40 +00:00
|
|
|
if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
|
|
|
|
Live.insert(Reg);
|
|
|
|
for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
|
|
|
|
Live.insert(*SS);
|
|
|
|
} else {
|
|
|
|
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
|
|
|
unsigned SubReg = *SubRegs; ++SubRegs) {
|
|
|
|
// If a register isn't itself defined, but all parts that make up of it
|
|
|
|
// are defined, then consider it also defined.
|
|
|
|
// e.g.
|
|
|
|
// AL =
|
|
|
|
// AH =
|
|
|
|
// = AX
|
2009-09-24 02:15:22 +00:00
|
|
|
if (Live.count(SubReg))
|
|
|
|
continue;
|
2008-04-16 09:46:40 +00:00
|
|
|
if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
|
|
|
|
Live.insert(SubReg);
|
|
|
|
for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
|
|
|
|
Live.insert(*SS);
|
2007-06-26 21:03:35 +00:00
|
|
|
}
|
2008-02-20 07:36:31 +00:00
|
|
|
}
|
2003-01-13 20:01:16 +00:00
|
|
|
}
|
2007-04-25 07:30:23 +00:00
|
|
|
|
2008-04-16 09:46:40 +00:00
|
|
|
// Start from the largest piece, find the last time any part of the register
|
|
|
|
// is referenced.
|
2009-09-24 02:15:22 +00:00
|
|
|
HandlePhysRegKill(Reg, MI);
|
|
|
|
// Only some of the sub-registers are used.
|
|
|
|
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
|
|
|
unsigned SubReg = *SubRegs; ++SubRegs) {
|
|
|
|
if (!Live.count(SubReg))
|
|
|
|
// Skip if this sub-register isn't defined.
|
|
|
|
continue;
|
|
|
|
HandlePhysRegKill(SubReg, MI);
|
2007-04-25 07:30:23 +00:00
|
|
|
}
|
|
|
|
|
2009-09-24 02:15:22 +00:00
|
|
|
if (MI)
|
|
|
|
Defs.push_back(Reg); // Remember this def.
|
2009-09-23 06:28:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
|
|
|
|
SmallVector<unsigned, 4> &Defs) {
|
|
|
|
while (!Defs.empty()) {
|
|
|
|
unsigned Reg = Defs.back();
|
|
|
|
Defs.pop_back();
|
2008-04-16 09:46:40 +00:00
|
|
|
PhysRegDef[Reg] = MI;
|
|
|
|
PhysRegUse[Reg] = NULL;
|
2008-03-05 00:59:57 +00:00
|
|
|
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
|
2007-06-26 21:03:35 +00:00
|
|
|
unsigned SubReg = *SubRegs; ++SubRegs) {
|
2008-04-16 09:46:40 +00:00
|
|
|
PhysRegDef[SubReg] = MI;
|
|
|
|
PhysRegUse[SubReg] = NULL;
|
2007-06-26 21:03:35 +00:00
|
|
|
}
|
2004-01-13 06:24:30 +00:00
|
|
|
}
|
2003-01-13 20:01:16 +00:00
|
|
|
}
|
|
|
|
|
2007-03-17 09:29:54 +00:00
|
|
|
bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
|
|
|
|
MF = &mf;
|
2008-04-02 18:04:08 +00:00
|
|
|
MRI = &mf.getRegInfo();
|
2008-03-05 00:59:57 +00:00
|
|
|
TRI = MF->getTarget().getRegisterInfo();
|
2004-02-09 01:35:21 +00:00
|
|
|
|
2008-03-05 00:59:57 +00:00
|
|
|
ReservedRegisters = TRI->getReservedRegs(mf);
|
2003-05-07 20:08:36 +00:00
|
|
|
|
2008-03-05 00:59:57 +00:00
|
|
|
unsigned NumRegs = TRI->getNumRegs();
|
2008-04-16 09:46:40 +00:00
|
|
|
PhysRegDef = new MachineInstr*[NumRegs];
|
|
|
|
PhysRegUse = new MachineInstr*[NumRegs];
|
2007-04-25 19:34:00 +00:00
|
|
|
PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
|
2008-04-16 09:46:40 +00:00
|
|
|
std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
|
|
|
|
std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
|
2010-02-23 22:43:58 +00:00
|
|
|
PHIJoins.clear();
|
2003-01-13 20:01:16 +00:00
|
|
|
|
2007-03-17 09:29:54 +00:00
|
|
|
analyzePHINodes(mf);
|
2006-10-03 07:20:20 +00:00
|
|
|
|
2003-01-13 20:01:16 +00:00
|
|
|
// Calculate live variable information in depth first order on the CFG of the
|
|
|
|
// function. This guarantees that we will see the definition of a virtual
|
|
|
|
// register before its uses due to dominance properties of SSA (except for PHI
|
|
|
|
// nodes, which are treated as a special case).
|
2007-03-17 09:29:54 +00:00
|
|
|
MachineBasicBlock *Entry = MF->begin();
|
2007-06-27 05:23:00 +00:00
|
|
|
SmallPtrSet<MachineBasicBlock*,16> Visited;
|
2008-02-20 09:15:16 +00:00
|
|
|
|
2007-06-27 05:23:00 +00:00
|
|
|
for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
|
|
|
|
DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
|
|
|
|
DFI != E; ++DFI) {
|
2004-05-01 21:24:24 +00:00
|
|
|
MachineBasicBlock *MBB = *DFI;
|
2003-01-13 20:01:16 +00:00
|
|
|
|
2007-02-19 21:49:54 +00:00
|
|
|
// Mark live-in registers as live-in.
|
2009-09-23 06:28:31 +00:00
|
|
|
SmallVector<unsigned, 4> Defs;
|
2010-04-13 16:57:55 +00:00
|
|
|
for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
|
2007-02-13 01:30:55 +00:00
|
|
|
EE = MBB->livein_end(); II != EE; ++II) {
|
2008-02-10 18:45:23 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
|
2007-02-13 01:30:55 +00:00
|
|
|
"Cannot have a live-in virtual register!");
|
2009-09-24 02:15:22 +00:00
|
|
|
HandlePhysRegDef(*II, 0, Defs);
|
2007-02-13 01:30:55 +00:00
|
|
|
}
|
|
|
|
|
2003-01-13 20:01:16 +00:00
|
|
|
// Loop over all of the instructions, processing them.
|
2008-04-02 18:04:08 +00:00
|
|
|
DistanceMap.clear();
|
|
|
|
unsigned Dist = 0;
|
2003-01-13 20:01:16 +00:00
|
|
|
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
|
2004-06-24 21:31:16 +00:00
|
|
|
I != E; ++I) {
|
2004-02-12 02:27:10 +00:00
|
|
|
MachineInstr *MI = I;
|
2010-02-09 19:54:29 +00:00
|
|
|
if (MI->isDebugValue())
|
2010-02-09 02:01:46 +00:00
|
|
|
continue;
|
2008-04-02 18:04:08 +00:00
|
|
|
DistanceMap.insert(std::make_pair(MI, Dist++));
|
2003-01-13 20:01:16 +00:00
|
|
|
|
|
|
|
// Process all of the operands of the instruction...
|
|
|
|
unsigned NumOperandsToProcess = MI->getNumOperands();
|
|
|
|
|
|
|
|
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
|
|
|
|
// of the uses. They will be handled in other basic blocks.
|
2010-02-09 19:54:29 +00:00
|
|
|
if (MI->isPHI())
|
2004-06-24 21:31:16 +00:00
|
|
|
NumOperandsToProcess = 1;
|
2003-01-13 20:01:16 +00:00
|
|
|
|
2010-03-26 02:12:24 +00:00
|
|
|
// Clear kill and dead markers. LV will recompute them.
|
2008-04-16 09:46:40 +00:00
|
|
|
SmallVector<unsigned, 4> UseRegs;
|
|
|
|
SmallVector<unsigned, 4> DefRegs;
|
2003-01-13 20:01:16 +00:00
|
|
|
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
|
2010-03-26 02:12:24 +00:00
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2009-01-20 21:25:12 +00:00
|
|
|
if (!MO.isReg() || MO.getReg() == 0)
|
|
|
|
continue;
|
|
|
|
unsigned MOReg = MO.getReg();
|
2010-03-26 02:12:24 +00:00
|
|
|
if (MO.isUse()) {
|
|
|
|
MO.setIsKill(false);
|
2009-01-20 21:25:12 +00:00
|
|
|
UseRegs.push_back(MOReg);
|
2010-03-26 02:12:24 +00:00
|
|
|
} else /*MO.isDef()*/ {
|
|
|
|
MO.setIsDead(false);
|
2009-01-20 21:25:12 +00:00
|
|
|
DefRegs.push_back(MOReg);
|
2010-03-26 02:12:24 +00:00
|
|
|
}
|
2003-01-13 20:01:16 +00:00
|
|
|
}
|
|
|
|
|
2008-04-16 09:46:40 +00:00
|
|
|
// Process all uses.
|
|
|
|
for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
|
|
|
|
unsigned MOReg = UseRegs[i];
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(MOReg))
|
|
|
|
HandleVirtRegUse(MOReg, MBB, MI);
|
2008-09-21 21:11:41 +00:00
|
|
|
else if (!ReservedRegisters[MOReg])
|
2008-04-16 09:46:40 +00:00
|
|
|
HandlePhysRegUse(MOReg, MI);
|
|
|
|
}
|
2008-02-20 06:10:21 +00:00
|
|
|
|
2008-04-16 09:46:40 +00:00
|
|
|
// Process all defs.
|
|
|
|
for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
|
|
|
|
unsigned MOReg = DefRegs[i];
|
2008-09-21 21:11:41 +00:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(MOReg))
|
|
|
|
HandleVirtRegDef(MOReg, MI);
|
2009-09-24 02:15:22 +00:00
|
|
|
else if (!ReservedRegisters[MOReg])
|
|
|
|
HandlePhysRegDef(MOReg, MI, Defs);
|
2003-01-13 20:01:16 +00:00
|
|
|
}
|
2009-09-23 06:28:31 +00:00
|
|
|
UpdatePhysRegDefs(MI, Defs);
|
2003-01-13 20:01:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// Handle any virtual assignments from PHI nodes which might be at the
|
|
|
|
// bottom of this basic block. We check all of our successor blocks to see
|
|
|
|
// if they have PHI nodes, and if so, we simulate an assignment at the end
|
|
|
|
// of the current block.
|
2007-04-25 19:34:00 +00:00
|
|
|
if (!PHIVarInfo[MBB->getNumber()].empty()) {
|
|
|
|
SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
|
2006-05-04 01:26:39 +00:00
|
|
|
|
2007-04-25 19:34:00 +00:00
|
|
|
for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
|
2008-02-20 07:36:31 +00:00
|
|
|
E = VarInfoVec.end(); I != E; ++I)
|
|
|
|
// Mark it alive only in the block we are representing.
|
2008-04-02 18:04:08 +00:00
|
|
|
MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
|
2008-01-15 22:58:11 +00:00
|
|
|
MBB);
|
2003-01-13 20:01:16 +00:00
|
|
|
}
|
2005-04-21 22:36:52 +00:00
|
|
|
|
2008-02-20 09:15:16 +00:00
|
|
|
// Finally, if the last instruction in the block is a return, make sure to
|
|
|
|
// mark it as using all of the live-out values in the function.
|
2010-06-05 00:30:45 +00:00
|
|
|
// Things marked both call and return are tail calls; do not do this for
|
|
|
|
// them. The tail callee need not take the same registers as input
|
|
|
|
// that it produces as output, and there are dependencies for its input
|
|
|
|
// registers elsewhere.
|
|
|
|
if (!MBB->empty() && MBB->back().getDesc().isReturn()
|
|
|
|
&& !MBB->back().getDesc().isCall()) {
|
2005-04-09 15:23:25 +00:00
|
|
|
MachineInstr *Ret = &MBB->back();
|
2008-02-20 07:36:31 +00:00
|
|
|
|
2007-12-31 04:13:23 +00:00
|
|
|
for (MachineRegisterInfo::liveout_iterator
|
|
|
|
I = MF->getRegInfo().liveout_begin(),
|
|
|
|
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
|
2008-02-10 18:45:23 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
|
2008-06-25 22:14:43 +00:00
|
|
|
"Cannot have a live-out virtual register!");
|
2005-04-09 15:23:25 +00:00
|
|
|
HandlePhysRegUse(*I, Ret);
|
2008-02-20 07:36:31 +00:00
|
|
|
|
2006-11-15 20:51:59 +00:00
|
|
|
// Add live-out registers as implicit uses.
|
2008-03-05 00:59:57 +00:00
|
|
|
if (!Ret->readsRegister(*I))
|
2007-12-30 00:41:17 +00:00
|
|
|
Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
|
2005-04-09 15:23:25 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-04-16 09:46:40 +00:00
|
|
|
// Loop over PhysRegDef / PhysRegUse, killing any registers that are
|
|
|
|
// available at the end of the basic block.
|
2007-04-25 19:34:00 +00:00
|
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
2009-09-24 02:15:22 +00:00
|
|
|
if (PhysRegDef[i] || PhysRegUse[i])
|
|
|
|
HandlePhysRegDef(i, 0, Defs);
|
2007-04-25 07:30:23 +00:00
|
|
|
|
2008-04-16 09:46:40 +00:00
|
|
|
std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
|
|
|
|
std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
|
2003-01-13 20:01:16 +00:00
|
|
|
}
|
|
|
|
|
2006-11-15 20:51:59 +00:00
|
|
|
// Convert and transfer the dead / killed information we have gathered into
|
|
|
|
// VirtRegInfo onto MI's.
|
2011-01-08 23:10:57 +00:00
|
|
|
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
|
|
|
|
const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
|
|
|
|
for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
|
|
|
|
if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
|
|
|
|
VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
|
2003-01-13 20:01:16 +00:00
|
|
|
else
|
2011-01-08 23:10:57 +00:00
|
|
|
VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
|
|
|
|
}
|
2004-07-01 04:24:29 +00:00
|
|
|
|
2004-07-09 16:44:37 +00:00
|
|
|
// Check to make sure there are no unreachable blocks in the MC CFG for the
|
|
|
|
// function. If so, it is due to a bug in the instruction selector or some
|
|
|
|
// other part of the code generator if this happens.
|
|
|
|
#ifndef NDEBUG
|
2007-03-17 09:29:54 +00:00
|
|
|
for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
|
2004-07-09 16:44:37 +00:00
|
|
|
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
|
|
|
|
#endif
|
|
|
|
|
2008-04-16 09:46:40 +00:00
|
|
|
delete[] PhysRegDef;
|
|
|
|
delete[] PhysRegUse;
|
2007-04-25 19:34:00 +00:00
|
|
|
delete[] PHIVarInfo;
|
|
|
|
|
2003-01-13 20:01:16 +00:00
|
|
|
return false;
|
|
|
|
}
|
2004-02-19 18:28:02 +00:00
|
|
|
|
2008-07-03 00:07:19 +00:00
|
|
|
/// replaceKillInstruction - Update register kill info by replacing a kill
|
|
|
|
/// instruction with a new one.
|
|
|
|
void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
|
|
|
|
MachineInstr *NewMI) {
|
|
|
|
VarInfo &VI = getVarInfo(Reg);
|
2008-07-03 00:28:27 +00:00
|
|
|
std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
|
2008-07-03 00:07:19 +00:00
|
|
|
}
|
|
|
|
|
2006-09-03 00:05:09 +00:00
|
|
|
/// removeVirtualRegistersKilled - Remove all killed info for the specified
|
|
|
|
/// instruction.
|
|
|
|
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
|
2006-11-15 20:51:59 +00:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
MachineOperand &MO = MI->getOperand(i);
|
2008-10-03 15:45:36 +00:00
|
|
|
if (MO.isReg() && MO.isKill()) {
|
2007-12-30 21:56:09 +00:00
|
|
|
MO.setIsKill(false);
|
2006-11-15 20:51:59 +00:00
|
|
|
unsigned Reg = MO.getReg();
|
2008-02-10 18:45:23 +00:00
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
2006-11-15 20:51:59 +00:00
|
|
|
bool removed = getVarInfo(Reg).removeKill(MI);
|
|
|
|
assert(removed && "kill not in register's VarInfo?");
|
2008-11-21 20:00:59 +00:00
|
|
|
removed = true;
|
2006-11-15 20:51:59 +00:00
|
|
|
}
|
2006-09-03 00:05:09 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-10-03 07:20:20 +00:00
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in here. In
|
2008-02-20 09:15:16 +00:00
|
|
|
/// particular, we want to map the variable information of a virtual register
|
|
|
|
/// which is used in a PHI node. We map that to the BB the vreg is coming from.
|
2006-10-03 07:20:20 +00:00
|
|
|
///
|
|
|
|
void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
|
|
|
|
for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
|
|
|
|
I != E; ++I)
|
|
|
|
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
|
2010-02-09 19:54:29 +00:00
|
|
|
BBI != BBE && BBI->isPHI(); ++BBI)
|
2006-10-03 07:20:20 +00:00
|
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
|
2008-02-20 06:10:21 +00:00
|
|
|
PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
|
|
|
|
.push_back(BBI->getOperand(i).getReg());
|
2006-10-03 07:20:20 +00:00
|
|
|
}
|
2009-11-10 22:01:05 +00:00
|
|
|
|
2009-11-21 02:05:21 +00:00
|
|
|
bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
|
|
|
|
unsigned Reg,
|
|
|
|
MachineRegisterInfo &MRI) {
|
|
|
|
unsigned Num = MBB.getNumber();
|
|
|
|
|
|
|
|
// Reg is live-through.
|
|
|
|
if (AliveBlocks.test(Num))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// Registers defined in MBB cannot be live in.
|
|
|
|
const MachineInstr *Def = MRI.getVRegDef(Reg);
|
|
|
|
if (Def && Def->getParent() == &MBB)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Reg was not defined in MBB, was it killed here?
|
|
|
|
return findKill(&MBB);
|
|
|
|
}
|
|
|
|
|
2009-12-01 17:13:31 +00:00
|
|
|
bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
|
|
|
|
LiveVariables::VarInfo &VI = getVarInfo(Reg);
|
|
|
|
|
|
|
|
// Loop over all of the successors of the basic block, checking to see if
|
|
|
|
// the value is either live in the block, or if it is killed in the block.
|
|
|
|
std::vector<MachineBasicBlock*> OpSuccBlocks;
|
|
|
|
for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
|
|
|
|
E = MBB.succ_end(); SI != E; ++SI) {
|
|
|
|
MachineBasicBlock *SuccMBB = *SI;
|
|
|
|
|
|
|
|
// Is it alive in this successor?
|
|
|
|
unsigned SuccIdx = SuccMBB->getNumber();
|
|
|
|
if (VI.AliveBlocks.test(SuccIdx))
|
|
|
|
return true;
|
|
|
|
OpSuccBlocks.push_back(SuccMBB);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Check to see if this value is live because there is a use in a successor
|
|
|
|
// that kills it.
|
|
|
|
switch (OpSuccBlocks.size()) {
|
|
|
|
case 1: {
|
|
|
|
MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
|
|
|
|
for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
|
|
|
|
if (VI.Kills[i]->getParent() == SuccMBB)
|
|
|
|
return true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case 2: {
|
|
|
|
MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
|
|
|
|
for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
|
|
|
|
if (VI.Kills[i]->getParent() == SuccMBB1 ||
|
|
|
|
VI.Kills[i]->getParent() == SuccMBB2)
|
|
|
|
return true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
|
|
|
|
for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
|
|
|
|
if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
|
|
|
|
VI.Kills[i]->getParent()))
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-11-11 19:31:31 +00:00
|
|
|
/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
|
|
|
|
/// variables that are live out of DomBB will be marked as passing live through
|
|
|
|
/// BB.
|
|
|
|
void LiveVariables::addNewBlock(MachineBasicBlock *BB,
|
2009-11-21 02:05:21 +00:00
|
|
|
MachineBasicBlock *DomBB,
|
|
|
|
MachineBasicBlock *SuccBB) {
|
2009-11-11 19:31:31 +00:00
|
|
|
const unsigned NumNew = BB->getNumber();
|
2009-11-21 02:05:21 +00:00
|
|
|
|
|
|
|
// All registers used by PHI nodes in SuccBB must be live through BB.
|
|
|
|
for (MachineBasicBlock::const_iterator BBI = SuccBB->begin(),
|
2010-02-09 19:54:29 +00:00
|
|
|
BBE = SuccBB->end(); BBI != BBE && BBI->isPHI(); ++BBI)
|
2009-11-21 02:05:21 +00:00
|
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
|
|
|
|
if (BBI->getOperand(i+1).getMBB() == BB)
|
|
|
|
getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
|
2009-11-10 22:01:05 +00:00
|
|
|
|
|
|
|
// Update info for all live variables
|
2011-01-08 23:10:57 +00:00
|
|
|
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
|
|
|
|
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
|
2009-11-11 19:31:31 +00:00
|
|
|
VarInfo &VI = getVarInfo(Reg);
|
2009-11-21 02:05:21 +00:00
|
|
|
if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI))
|
2009-11-11 19:31:31 +00:00
|
|
|
VI.AliveBlocks.set(NumNew);
|
2009-11-10 22:01:05 +00:00
|
|
|
}
|
|
|
|
}
|