2002-10-25 22:55:53 +00:00
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//===-- X86InstructionInfo.def - X86 Instruction Information ----*- C++ -*-===//
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//
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// This file describes all of the instructions that the X86 backend uses. It
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// relys on an external 'I' macro being defined that takes the arguments
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// specified below, and is used to make all of the information relevant to an
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// instruction be in one place.
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//
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2002-10-30 01:15:31 +00:00
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// Note that X86 Instructions always have the destination register listed as
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// operand 0, unless it does not produce a value (in which case the TSFlags will
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// include X86II::Void).
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//
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2002-10-25 22:55:53 +00:00
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//===----------------------------------------------------------------------===//
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// NOTE: No include guards desired
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#ifndef I
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#errror "Must define I macro before including X86/X86InstructionInfo.def!"
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#endif
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2002-12-03 05:42:53 +00:00
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// Macro to handle the implicit register uses lists...
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#ifndef IMPREGSLIST
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#define IMPREGSLIST(NAME, ...)
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#endif
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// Implicit register usage info: O_ is for one register, T_ is for two registers
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Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
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// NoIR means the instruction does not use implicit registers, in this form.
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2002-12-18 01:05:31 +00:00
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#define NoIR 0
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Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
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IMPREGSLIST(O_AL , X86::AL , 0)
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IMPREGSLIST(O_AH , X86::AH , 0)
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IMPREGSLIST(O_CL , X86::CL , 0)
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IMPREGSLIST(O_AX , X86::AX , 0)
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IMPREGSLIST(O_DX , X86::DX , 0)
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IMPREGSLIST(O_EAX, X86::EAX, 0)
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IMPREGSLIST(O_EDX, X86::EDX, 0)
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IMPREGSLIST(O_EBP, X86::EBP, 0)
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IMPREGSLIST(T_AXDX , X86::AX , X86::DX , 0)
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IMPREGSLIST(T_EAXEDX, X86::EAX, X86::EDX, 0)
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2002-12-16 15:54:42 +00:00
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IMPREGSLIST(C_CLOBBER, X86::EAX, X86::ECX, X86::EDX, 0) // Callee clobber regs
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2002-12-03 05:42:53 +00:00
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#undef IMPREGSLIST
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2002-10-25 22:55:53 +00:00
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// Arguments to be passed into the I macro
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// #1: Enum name - This ends up being the opcode symbol in the X86 namespace
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// #2: Opcode name, as used by the gnu assembler
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2002-11-18 05:37:11 +00:00
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// #3: The base opcode for the instruction
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// #4: Instruction Flags - This should be a field or'd together that contains
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2002-10-29 20:48:56 +00:00
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// constants from the MachineInstrInfo.h file.
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2002-11-18 05:37:11 +00:00
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// #5: Target Specific Flags - Another bitfield containing X86 specific flags
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2002-10-30 01:09:34 +00:00
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// that we are interested in for each instruction. These should be flags
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// defined in X86InstrInfo.h in the X86II namespace.
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2002-12-03 05:42:53 +00:00
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// #6: Name of the implicit register uses list
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// #7: Name of the implicit register definitions list
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2002-10-25 22:55:53 +00:00
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//
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2002-11-18 01:34:36 +00:00
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// The first instruction must always be the PHI instruction:
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2002-12-25 05:11:46 +00:00
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I(PHI , "phi", 0, 0, X86II::Pseudo , NoIR, NoIR)
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2002-10-25 22:55:53 +00:00
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2002-11-18 01:34:36 +00:00
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// The second instruction must always be the noop instruction:
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2002-12-28 20:29:14 +00:00
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I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void, NoIR, NoIR) // nop
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// This "instruction" is really an annotation which indicates that a specified
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// amount of stack space is needed for an outgoing function call. This
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// instruction is found before any of the stores to the argument slots, which
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// use direct ESP references. If the frame pointer is eliminated, this
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// instruction turns into a noop, but if the frame pointer is retained, this
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// turns into a 'sub ESP, <amount>'.
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//
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I(ADJCALLSTACKDOWN, "adjcallstackdown", 0, 0, X86II::Pseudo, NoIR, NoIR)
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// This instruction is used to mark readjustment of the stack after a function
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// call. If the frame pointer is retained, this becomes a 'add ESP, <amount>'
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// instruction after the call.
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I(ADJCALLSTACKUP , "adjcallstackup" , 0, 0, X86II::Pseudo, NoIR, NoIR)
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2002-10-25 22:55:53 +00:00
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2002-11-02 19:27:56 +00:00
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// Flow control instructions
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2002-12-28 20:29:14 +00:00
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I(RET , "ret", 0xC3, M_RET_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // ret
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I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::RawFrm | X86II::Void, NoIR, NoIR) // jmp foo
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I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // jne foo
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I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void, NoIR, NoIR) // je foo
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I(CALLpcrel32 , "call", 0xE8, M_CALL_FLAG, X86II::Void | X86II::RawFrm, NoIR, C_CLOBBER) // call pc+42
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I(CALLr32 , "call", 0xFF, M_CALL_FLAG, X86II::Void | X86II::MRMS2r | X86II::Arg32,
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NoIR, C_CLOBBER) // call [r32]
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I(CALLm32 , "call", 0xFF, M_CALL_FLAG, X86II::Void | X86II::MRMS2m | X86II::Arg32,
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NoIR, C_CLOBBER) // call [m32]
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2002-10-25 22:55:53 +00:00
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2002-11-17 20:33:12 +00:00
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// Misc instructions
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2002-12-28 20:29:14 +00:00
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I(LEAVE , "leave", 0xC9, 0, X86II::RawFrm , O_EBP, O_EBP) // leave
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I(BSWAPr32 , "bswap", 0xC8, M_2_ADDR_FLAG, X86II::AddRegFrm | X86II::Arg32 | X86II::TB , NoIR, NoIR) // R32 = bswap R32
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I(XCHGrr8 , "xchg" , 0x86, 0, X86II::MRMDestReg | X86II::Arg8 , NoIR, NoIR) // xchg(R8, R8)
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2002-12-25 05:11:46 +00:00
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I(XCHGrr16 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // xchg(R16, R16)
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2002-12-28 20:29:14 +00:00
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I(XCHGrr32 , "xchg" , 0x87, 0, X86II::MRMDestReg | X86II::Arg32 , NoIR, NoIR) // xchg(R32, R32)
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I(LEAr16 , "lea" , 0x8D, 0, X86II::MRMSrcMem | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = lea [mem]
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I(LEAr32 , "lea" , 0x8D, 0, X86II::MRMSrcMem | X86II::Arg32 , NoIR, NoIR) // R32 = lea [mem]
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2002-11-17 20:33:12 +00:00
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2002-10-27 21:16:44 +00:00
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// Move instructions
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2002-12-28 20:29:14 +00:00
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I(MOVrr8 , "mov", 0x88, 0, X86II::MRMDestReg, NoIR, NoIR) // R8 = R8
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I(MOVrr16 , "mov", 0x89, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 = R16
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I(MOVrr32 , "mov", 0x89, 0, X86II::MRMDestReg, NoIR, NoIR) // R32 = R32
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I(MOVir8 , "mov", 0xB0, 0, X86II::AddRegFrm | X86II::Arg8, NoIR, NoIR) // R8 = imm8
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I(MOVir16 , "mov", 0xB8, 0, X86II::AddRegFrm | X86II::Arg16 | X86II::OpSize, NoIR, NoIR) // R16 = imm16
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I(MOVir32 , "mov", 0xB8, 0, X86II::AddRegFrm | X86II::Arg32, NoIR, NoIR) // R32 = imm32
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I(MOVmr8 , "mov", 0x8A, 0, X86II::MRMSrcMem | X86II::Arg8, NoIR, NoIR) // R8 = [mem]
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I(MOVmr16 , "mov", 0x8B, 0, X86II::MRMSrcMem | X86II::OpSize |
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X86II::Arg16, NoIR, NoIR) // R16 = [mem]
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I(MOVmr32 , "mov", 0x8B, 0, X86II::MRMSrcMem | X86II::Arg32, NoIR, NoIR)// R32 = [mem]
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I(MOVrm8 , "mov", 0x88, 0, X86II::MRMDestMem | X86II::Void |
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X86II::Arg8, NoIR, NoIR) // [mem] = R8
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I(MOVrm16 , "mov", 0x89, 0, X86II::MRMDestMem | X86II::Void |
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X86II::OpSize | X86II::Arg16, NoIR, NoIR) // [mem] = R16
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I(MOVrm32 , "mov", 0x89, 0, X86II::MRMDestMem | X86II::Void |
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X86II::Arg32, NoIR, NoIR) // [mem] = R32
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//I(PUSHr32 , "pushl", 0x50, 0, X86II::AddRegFrm | X86II::Void, NoIR, NoIR)
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//I(POPr32 , "popl", 0x58, 0, X86II::AddRegFrm, NoIR, NoIR)
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2002-11-29 12:01:58 +00:00
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2002-10-27 21:16:44 +00:00
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// Arithmetic instructions
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2002-12-28 20:29:14 +00:00
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I(ADDrr8 , "add", 0x00, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 += R8
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I(ADDrr16 , "add", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 += R16
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I(ADDrr32 , "add", 0x01, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 += R32
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I(ADDri32 , "add", 0x81, M_2_ADDR_FLAG, X86II::MRMS0r | X86II::Arg32, NoIR, NoIR) // R32 += imm32
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I(SUBrr8 , "sub", 0x28, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 -= R8
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I(SUBrr16 , "sub", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 -= R16
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I(SUBrr32 , "sub", 0x29, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 -= R32
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I(SUBri32 , "sub", 0x81, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg32, NoIR, NoIR) // R32 -= imm32
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I(MULrr8 , "mul", 0xF6, 0, X86II::MRMS4r | X86II::Void, O_AL, O_AX) // AX = AL*R8
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I(MULrr16 , "mul", 0xF7, 0, X86II::MRMS4r | X86II::Void | // DX:AX= AX*R16
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2002-12-03 05:42:53 +00:00
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X86II::OpSize, O_AX, T_AXDX)
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2002-12-28 20:29:14 +00:00
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I(MULrr32 , "mul", 0xF7, 0, X86II::MRMS4r | X86II::Void, O_EAX, T_EAXEDX) // ED:EA= EA*R32
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2002-11-02 20:28:58 +00:00
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2002-11-02 20:54:46 +00:00
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// unsigned division/remainder
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2002-12-28 20:29:14 +00:00
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I(DIVrr8 , "div", 0xF6, 0, X86II::MRMS6r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
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I(DIVrr16 , "div", 0xF7, 0, X86II::MRMS6r | X86II::Void | // ED:EA/r16=AX&DX
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2002-12-03 05:42:53 +00:00
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X86II::OpSize, T_AXDX, T_AXDX)
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2002-12-28 20:29:14 +00:00
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I(DIVrr32 , "div", 0xF7, 0, X86II::MRMS6r | X86II::Void, T_EAXEDX,
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Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
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T_EAXEDX) // ED:EA/r32=EA&ED
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2002-11-02 20:54:46 +00:00
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// signed division/remainder
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2002-12-28 20:29:14 +00:00
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I(IDIVrr8 , "idiv", 0xF6, 0, X86II::MRMS7r | X86II::Void, O_AX, O_AX) // AX/r8= AL&AH
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I(IDIVrr16 , "idiv", 0xF7, 0, X86II::MRMS7r | X86II::Void | // DA/r16=AX&DX
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2002-12-03 05:42:53 +00:00
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X86II::OpSize, T_AXDX, T_AXDX)
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2002-12-28 20:29:14 +00:00
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I(IDIVrr32 , "idiv", 0xF7, 0, X86II::MRMS7r | X86II::Void, T_EAXEDX,
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Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
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T_EAXEDX) // DA/r32=EAX&DX
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2002-11-02 20:54:46 +00:00
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2002-11-02 20:04:26 +00:00
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// Logical operators
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2002-12-28 20:29:14 +00:00
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I(ANDrr8 , "and", 0x20, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 &= R8
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I(ANDrr16 , "and", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 &= R16
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I(ANDrr32 , "and", 0x21, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 &= R32
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I(ANDri32 , "and", 0x81, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg32, NoIR, NoIR) // R32 &= imm32
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I(ORrr8 , "or", 0x08, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 |= R8
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I(ORrr16 , "or", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 |= R16
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I(ORrr32 , "or", 0x09, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 |= R32
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I(XORrr8 , "xor", 0x30, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R8 ^= R8
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I(XORrr16 , "xor", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // R16 ^= R16
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I(XORrr32 , "xor", 0x31, M_2_ADDR_FLAG, X86II::MRMDestReg, NoIR, NoIR) // R32 ^= R32
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2002-10-25 22:55:53 +00:00
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2002-10-31 23:03:59 +00:00
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// Shift instructions
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2002-12-12 23:19:11 +00:00
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I(SHLrr8 , "shlb", 0xD2, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR) // R8 <<= cl
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I(SHLrr16 , "shlw", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::OpSize, O_CL, NoIR) // R16 <<= cl
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I(SHLrr32 , "shll", 0xD3, M_2_ADDR_FLAG, X86II::MRMS4r, O_CL, NoIR) // R32 <<= cl
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2002-12-13 03:51:55 +00:00
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I(SHLir8 , "shlb", 0xC0, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R8 <<= imm8
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I(SHLir16 , "shlw", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 <<= imm8
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I(SHLir32 , "shll", 0xC1, M_2_ADDR_FLAG, X86II::MRMS4r | X86II::Arg8, NoIR, NoIR) // R32 <<= imm8
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2002-12-12 23:19:11 +00:00
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I(SHRrr8 , "shrb", 0xD2, M_2_ADDR_FLAG, X86II::MRMS5r, O_CL, NoIR) // R8 >>>= cl
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I(SHRrr16 , "shrw", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::OpSize, O_CL, NoIR) // R16 >>>= cl
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I(SHRrr32 , "shrl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS5r, O_CL, NoIR) // R32 >>>= cl
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2002-12-13 03:51:55 +00:00
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I(SHRir8 , "shrb", 0xC0, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R8 >>>= imm8
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I(SHRir16 , "shrw", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>>= imm8
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I(SHRir32 , "shrl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS5r | X86II::Arg8, NoIR, NoIR) // R32 >>>= imm8
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2002-12-12 23:19:11 +00:00
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I(SARrr8 , "sarb", 0xD2, M_2_ADDR_FLAG, X86II::MRMS7r, O_CL, NoIR) // R8 >>= cl
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I(SARrr16 , "sarw", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::OpSize, O_CL, NoIR) // R16 >>= cl
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I(SARrr32 , "sarl", 0xD3, M_2_ADDR_FLAG, X86II::MRMS7r, O_CL, NoIR) // R32 >>= cl
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2002-12-13 03:51:55 +00:00
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I(SARir8 , "sarb", 0xC0, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R8 >>= imm8
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I(SARir16 , "sarw", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8 | X86II::OpSize, NoIR, NoIR) // R16 >>= imm8
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I(SARir32 , "sarl", 0xC1, M_2_ADDR_FLAG, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // R32 >>= imm8
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2002-10-25 22:55:53 +00:00
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2002-11-07 17:59:21 +00:00
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// Condition code ops, incl. set if equal/not equal/...
|
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
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I(SAHF , "sahf", 0x9E, 0, X86II::RawFrm, O_AH, NoIR) // flags = AH
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I(SETBr , "setb", 0x92, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = < unsign
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I(SETAEr , "setae", 0x93, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = >=unsign
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I(SETEr , "sete", 0x94, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = ==
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I(SETNEr , "setne", 0x95, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = !=
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I(SETBEr , "setbe", 0x96, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = <=unsign
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I(SETAr , "seta", 0x97, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = > unsign
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I(SETLr , "setl", 0x9C, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = < signed
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I(SETGEr , "setge", 0x9D, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = >=signed
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I(SETLEr , "setle", 0x9E, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = <=signed
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I(SETGr , "setg", 0x9F, 0, X86II::TB | X86II::MRMS0r, NoIR, NoIR) // R8 = > signed
|
2002-11-07 17:59:21 +00:00
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// Integer comparisons
|
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
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I(CMPrr8 , "cmpb", 0x38, 0, X86II::MRMDestReg, NoIR, NoIR) // compare R8,R8
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I(CMPrr16 , "cmpw", 0x39, 0, X86II::MRMDestReg | X86II::OpSize, NoIR, NoIR) // compare R16,R16
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I(CMPrr32 , "cmpl", 0x39, 0, X86II::MRMDestReg, NoIR, NoIR) // compare R32,R32
|
2002-12-28 20:29:14 +00:00
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I(CMPri8 , "cmp", 0x80, 0, X86II::MRMS7r | X86II::Arg8, NoIR, NoIR) // compare R8, imm8
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2002-11-07 17:59:21 +00:00
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2002-11-14 22:32:30 +00:00
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// Sign extenders (first 3 are good for DIV/IDIV; the others are more general)
|
2002-12-20 04:13:11 +00:00
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I(CBW , "cbw", 0x98, 0, X86II::RawFrm | X86II::OpSize, O_AL, O_AH) // AX = signext(AL)
|
Target/X86/Printer.cpp: Add sizePtr function, and use it instead of
" <SIZE> PTR " string when emitting assembly.
Target/X86/X86InstrInfo.def: Tidy up a bit:
Squashed everything down to 118 chars wide, wrapping lines so that
comment is at the same point on each line. Rename "NoImpRegs" as
"NoIR". (most instructions have NoImpRegs twice on a line, so this
saves 10 columns).
Also, annotate various instructions with flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
Target/X86/X86InstrInfo.h: Define flags for size of memory operand.
(MemArg16, MemArg32, MemArg64, etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4932 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-05 08:30:40 +00:00
|
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I(CWD , "cwd", 0x99, 0, X86II::RawFrm, O_AX, O_DX) // DX:AX = signext(AX)
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I(CDQ , "cdq", 0x99, 0, X86II::RawFrm, O_EAX, O_EDX) // EDX:EAX = signext(EAX)
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I(MOVSXr16r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB | // R16 = signext(R8)
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X86II::OpSize, NoIR, NoIR)
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I(MOVSXr32r8 , "movsx", 0xBE, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = signext(R8)
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I(MOVSXr32r16 , "movsx", 0xBF, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = signext(R16)
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I(MOVZXr16r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB | // R16 = zeroext(R8)
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X86II::OpSize, NoIR, NoIR)
|
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I(MOVZXr32r8 , "movzx", 0xB6, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R8)
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I(MOVZXr32r16 , "movzx", 0xB7, 0, X86II::MRMSrcReg | X86II::TB, NoIR, NoIR) // R32 = zeroext(R16)
|
2002-11-02 20:54:46 +00:00
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|
2002-12-25 05:11:46 +00:00
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|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Floating point support
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
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|
|
// FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
|
|
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|
|
// FIXME: Remove Pseudo encodings from some insts
|
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|
|
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|
|
// Floating point loads & stores... PREFIX ARGTYPE ENCODING REF MOD
|
|
|
|
|
I(FLDr32 , "flds" , 0xD9, 0, X86II::ArgF32 | X86II::Pseudo, NoIR, NoIR) // load float MRMS0m
|
|
|
|
|
I(FLDr64 , "fldl" , 0xDD, 0, X86II::ArgF64 | X86II::Pseudo, NoIR, NoIR) // load double MRMS0m
|
|
|
|
|
I(FLDr80 , "fldx" , 0xDB, 0, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // store extended MRMS5m
|
|
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|
|
I(FSTr32 , "fsts" , 0xD9, 0, X86II::ArgF32 | X86II::Pseudo, NoIR, NoIR) // store float MRMS2m
|
|
|
|
|
I(FSTr64 , "fstl" , 0xDD, 0, X86II::ArgF64 | X86II::Pseudo, NoIR, NoIR) // store double MRMS2m
|
|
|
|
|
I(FSTPr80 , "fstpx", 0xDB, 0, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // store extended MRMS7m
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Floating point constant loads...
|
|
|
|
|
I(FLD0 , "fld0" , 0xEE, 0, X86II::D9 | X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // load +0.0 RawFrm
|
|
|
|
|
I(FLD1 , "fld1" , 0xE8, 0, X86II::D9 | X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // load +1.0 RawFrm
|
|
|
|
|
|
|
|
|
|
// Floating point pseudo instructions...
|
|
|
|
|
I(FpMOV , "FMOV" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fmov f2
|
|
|
|
|
I(FpADD , "FADD" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fadd f2, f3
|
|
|
|
|
I(FpSUB , "FSUB" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fsub f2, f3
|
|
|
|
|
I(FpMUL , "FMUL" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fmul f2, f3
|
|
|
|
|
I(FpDIV , "FDIV" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = fdiv f2, f3
|
|
|
|
|
I(FpREM , "FREM" , 0, M_PSEUDO_FLAG, X86II::ArgF80 | X86II::Pseudo, NoIR, NoIR) // f1 = frem f2, f3
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Floating point compares
|
|
|
|
|
//I(FUCOMPP , "fucompp", 0xDA, 0, X86II::Void, NoIR, NoIR) // compare+pop2x
|
|
|
|
|
|
|
|
|
|
// Floating point flag ops
|
|
|
|
|
//I(FNSTSWr8 , "fnstsw", 0xDF, 0, X86II::Void, NoIR, O_AX) // AX = fp flags
|
|
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|
|
|
|
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|
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|
|
|
|
2002-10-30 01:09:34 +00:00
|
|
|
// At this point, I is dead, so undefine the macro
|
2002-10-25 22:55:53 +00:00
|
|
|
#undef I
|
2002-12-18 01:05:31 +00:00
|
|
|
#undef NoIR
|
|
|
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|
