2008-06-17 14:27:01 +00:00
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//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
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2007-12-08 22:37:41 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-12-08 22:37:41 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2008-06-17 14:27:01 +00:00
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// This file performs vector type splitting and scalarization for LegalizeTypes.
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// Scalarization is the act of changing a computation in an illegal one-element
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// vector type to be a computation in its scalar element type. For example,
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// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
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// as a base case when scalarizing vector arithmetic like <4 x f32>, which
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// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
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// types.
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// Splitting is the act of changing a computation in an invalid vector type to
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2007-12-08 22:37:41 +00:00
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// be a computation in multiple vectors of a smaller type. For example,
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// implementing <128 x f32> operations in terms of two <64 x f32> operations.
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//
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//===----------------------------------------------------------------------===//
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#include "LegalizeTypes.h"
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2008-12-09 21:33:20 +00:00
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#include "llvm/Target/TargetData.h"
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2007-12-08 22:37:41 +00:00
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using namespace llvm;
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2008-06-17 14:27:01 +00:00
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//===----------------------------------------------------------------------===//
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// Result Vector Scalarization: <1 x ty> -> ty.
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//===----------------------------------------------------------------------===//
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2008-07-10 15:25:04 +00:00
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void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
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2008-06-17 14:27:01 +00:00
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DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
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cerr << "\n");
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2008-07-27 21:46:04 +00:00
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SDValue R = SDValue();
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2008-06-17 14:27:01 +00:00
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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2008-07-10 15:25:04 +00:00
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cerr << "ScalarizeVectorResult #" << ResNo << ": ";
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2008-06-17 14:27:01 +00:00
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to scalarize the result of this operator!");
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abort();
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2008-11-18 16:40:48 +00:00
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case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
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case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
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case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
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2008-10-20 16:31:21 +00:00
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case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
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2008-11-18 16:40:48 +00:00
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case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
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2008-07-16 11:41:33 +00:00
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case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
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case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
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2008-11-18 16:40:48 +00:00
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case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
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case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
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case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
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case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
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case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
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case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
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2008-06-20 18:40:50 +00:00
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2008-07-27 12:28:43 +00:00
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::CTTZ:
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case ISD::FABS:
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case ISD::FCOS:
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case ISD::FNEG:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::FSIN:
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case ISD::FSQRT:
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2008-08-21 17:55:02 +00:00
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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2008-07-27 12:28:43 +00:00
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case ISD::SINT_TO_FP:
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2008-10-20 16:31:21 +00:00
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case ISD::TRUNCATE:
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2008-07-27 12:28:43 +00:00
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case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
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2008-06-17 14:27:01 +00:00
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case ISD::ADD:
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2008-07-27 12:28:43 +00:00
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case ISD::AND:
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2008-06-17 14:27:01 +00:00
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case ISD::FADD:
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2008-07-27 12:28:43 +00:00
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case ISD::FDIV:
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case ISD::FMUL:
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case ISD::FPOW:
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case ISD::FREM:
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2008-06-17 14:27:01 +00:00
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case ISD::FSUB:
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case ISD::MUL:
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2008-07-27 12:28:43 +00:00
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case ISD::OR:
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2008-06-17 14:27:01 +00:00
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case ISD::SDIV:
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case ISD::SREM:
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2008-07-27 12:28:43 +00:00
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case ISD::SUB:
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case ISD::UDIV:
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2008-06-17 14:27:01 +00:00
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case ISD::UREM:
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2008-06-20 18:40:50 +00:00
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case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
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2008-06-17 14:27:01 +00:00
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}
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// If R is null, the sub-method took care of registering the result.
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2008-08-28 21:40:38 +00:00
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if (R.getNode())
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2008-07-27 21:46:04 +00:00
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SetScalarizedVector(SDValue(N, ResNo), R);
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2008-06-17 14:27:01 +00:00
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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2008-06-17 14:27:01 +00:00
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return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
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2008-07-16 11:41:33 +00:00
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MVT NewVT = N->getValueType(0).getVectorElementType();
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return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
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2008-06-17 14:27:01 +00:00
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}
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2008-11-10 20:54:11 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
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MVT NewVT = N->getValueType(0).getVectorElementType();
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SDValue Op0 = GetScalarizedVector(N->getOperand(0));
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return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
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DAG.getValueType(Op0.getValueType()),
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N->getOperand(3),
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N->getOperand(4),
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cast<CvtRndSatSDNode>(N)->getCvtCode());
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}
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2008-10-20 16:31:21 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
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N->getValueType(0).getVectorElementType(),
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N->getOperand(0), N->getOperand(1));
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
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SDValue Op = GetScalarizedVector(N->getOperand(0));
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2008-06-17 14:27:01 +00:00
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return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
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2008-06-17 14:27:01 +00:00
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// The value to insert may have a wider type than the vector element type,
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// so be sure to truncate it to the element type if necessary.
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2008-07-27 21:46:04 +00:00
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SDValue Op = N->getOperand(1);
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2008-06-17 14:27:01 +00:00
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MVT EltVT = N->getValueType(0).getVectorElementType();
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2008-07-14 17:22:31 +00:00
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if (Op.getValueType() != EltVT)
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// FIXME: Can this happen for floating point types?
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2008-06-17 14:27:01 +00:00
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Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
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return Op;
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
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2008-08-14 20:04:46 +00:00
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assert(N->isUnindexed() && "Indexed vector load?");
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SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
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N->getValueType(0).getVectorElementType(),
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N->getChain(), N->getBasePtr(),
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DAG.getNode(ISD::UNDEF,
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N->getBasePtr().getValueType()),
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N->getSrcValue(), N->getSrcValueOffset(),
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N->getMemoryVT().getVectorElementType(),
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N->isVolatile(), N->getAlignment());
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2008-07-16 11:41:33 +00:00
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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2008-07-27 21:46:04 +00:00
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ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
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2008-07-16 11:41:33 +00:00
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return Result;
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2008-06-17 14:27:01 +00:00
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
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2008-07-27 12:28:43 +00:00
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// Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
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2008-10-20 16:31:21 +00:00
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MVT DestVT = N->getValueType(0).getVectorElementType();
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2008-07-27 21:46:04 +00:00
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SDValue Op = GetScalarizedVector(N->getOperand(0));
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2008-07-27 12:28:43 +00:00
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return DAG.getNode(N->getOpcode(), DestVT, Op);
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2008-07-16 11:41:33 +00:00
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}
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2008-11-18 16:40:48 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
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return N->getOperand(0);
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2008-06-17 14:27:01 +00:00
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(1));
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2008-06-17 14:27:01 +00:00
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return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
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GetScalarizedVector(N->getOperand(2)));
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}
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2008-11-04 17:31:08 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(2));
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return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(),
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N->getOperand(0), N->getOperand(1),
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LHS, GetScalarizedVector(N->getOperand(3)),
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N->getOperand(4));
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}
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2008-11-18 16:40:48 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
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return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
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2008-07-16 11:41:33 +00:00
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// Figure out if the scalar is the LHS or RHS and return it.
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2008-10-19 15:00:25 +00:00
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SDValue Arg = N->getOperand(2).getOperand(0);
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if (Arg.getOpcode() == ISD::UNDEF)
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return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
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unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
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2008-07-16 11:41:33 +00:00
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return GetScalarizedVector(N->getOperand(Op));
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}
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2008-07-27 21:46:04 +00:00
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SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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2008-11-08 18:26:48 +00:00
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MVT NVT = N->getValueType(0).getVectorElementType();
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MVT SVT = TLI.getSetCCResultType(LHS);
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// Turn it into a scalar SETCC.
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SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
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// VSETCC always returns a sign-extended value, while SETCC may not. The
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// SETCC result type may not match the vector element type. Correct these.
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2008-11-10 17:29:56 +00:00
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if (NVT.bitsLE(SVT)) {
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2008-11-08 18:26:48 +00:00
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// The SETCC result type is bigger than the vector element type.
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// Ensure the SETCC result is sign-extended.
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2008-11-23 15:47:28 +00:00
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if (TLI.getBooleanContents() !=
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TargetLowering::ZeroOrNegativeOneBooleanContent)
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2008-11-08 18:26:48 +00:00
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Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
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DAG.getValueType(MVT::i1));
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// Truncate to the final type.
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return DAG.getNode(ISD::TRUNCATE, NVT, Res);
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} else {
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// The SETCC result type is smaller than the vector element type.
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// If the SetCC result is not sign-extended, chop it down to MVT::i1.
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2008-11-23 15:47:28 +00:00
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if (TLI.getBooleanContents() !=
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TargetLowering::ZeroOrNegativeOneBooleanContent)
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2008-11-08 18:26:48 +00:00
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Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
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// Sign extend to the final type.
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return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
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}
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2008-07-22 23:54:03 +00:00
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}
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2008-06-17 14:27:01 +00:00
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//===----------------------------------------------------------------------===//
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// Operand Vector Scalarization <1 x ty> -> ty.
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//===----------------------------------------------------------------------===//
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2008-07-10 15:25:04 +00:00
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bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
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2008-06-17 14:27:01 +00:00
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DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
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cerr << "\n");
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2008-07-27 21:46:04 +00:00
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SDValue Res = SDValue();
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2008-06-17 14:27:01 +00:00
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2008-08-28 21:40:38 +00:00
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if (Res.getNode() == 0) {
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2008-06-17 14:27:01 +00:00
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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2008-07-10 15:25:04 +00:00
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cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
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2008-06-17 14:27:01 +00:00
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to scalarize this operator's operand!");
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abort();
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case ISD::BIT_CONVERT:
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2008-06-20 18:40:50 +00:00
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Res = ScalarizeVecOp_BIT_CONVERT(N); break;
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2008-06-17 14:27:01 +00:00
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2008-10-20 16:31:21 +00:00
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case ISD::CONCAT_VECTORS:
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Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
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2008-06-17 14:27:01 +00:00
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case ISD::EXTRACT_VECTOR_ELT:
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2008-06-20 18:40:50 +00:00
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Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
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2008-06-17 14:27:01 +00:00
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|
|
|
|
|
case ISD::STORE:
|
2008-06-20 18:40:50 +00:00
|
|
|
Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
|
2008-06-17 14:27:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If the result is null, the sub-method took care of registering results etc.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (!Res.getNode()) return false;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-12-09 21:33:20 +00:00
|
|
|
// If the result is N, the sub-method updated N in place. Tell the legalizer
|
|
|
|
// core about this.
|
|
|
|
if (Res.getNode() == N)
|
2008-06-17 14:27:01 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
|
|
|
|
"Invalid operand expansion");
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
ReplaceValueWith(SDValue(N, 0), Res);
|
2008-06-17 14:27:01 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
|
2008-06-17 14:27:01 +00:00
|
|
|
/// to be scalarized, it must be <1 x ty>. Convert the element instead.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
|
|
|
|
SDValue Elt = GetScalarizedVector(N->getOperand(0));
|
2008-06-17 14:27:01 +00:00
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
|
|
|
|
}
|
|
|
|
|
2008-10-20 16:31:21 +00:00
|
|
|
/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
|
|
|
|
/// use a BUILD_VECTOR instead.
|
|
|
|
SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
|
|
|
|
SmallVector<SDValue, 8> Ops(N->getNumOperands());
|
|
|
|
for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
|
|
|
|
Ops[i] = GetScalarizedVector(N->getOperand(i));
|
|
|
|
return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
|
|
|
|
&Ops[0], Ops.size());
|
|
|
|
}
|
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
|
|
|
|
/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
|
2008-06-17 14:27:01 +00:00
|
|
|
/// index.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
|
2008-06-17 14:27:01 +00:00
|
|
|
return GetScalarizedVector(N->getOperand(0));
|
|
|
|
}
|
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
|
2008-06-17 14:27:01 +00:00
|
|
|
/// scalarized, it must be <1 x ty>. Just store the element.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
|
2008-08-14 20:04:46 +00:00
|
|
|
assert(N->isUnindexed() && "Indexed store of one-element vector?");
|
2008-06-17 14:27:01 +00:00
|
|
|
assert(OpNo == 1 && "Do not know how to scalarize this operand!");
|
2008-08-14 20:04:46 +00:00
|
|
|
|
|
|
|
if (N->isTruncatingStore())
|
|
|
|
return DAG.getTruncStore(N->getChain(),
|
|
|
|
GetScalarizedVector(N->getOperand(1)),
|
|
|
|
N->getBasePtr(),
|
|
|
|
N->getSrcValue(), N->getSrcValueOffset(),
|
|
|
|
N->getMemoryVT().getVectorElementType(),
|
|
|
|
N->isVolatile(), N->getAlignment());
|
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
|
|
|
|
N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
|
|
|
|
N->isVolatile(), N->getAlignment());
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Result Vector Splitting
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2008-07-10 15:25:04 +00:00
|
|
|
/// SplitVectorResult - This method is called when the specified result of the
|
2007-12-08 22:37:41 +00:00
|
|
|
/// specified node is found to need vector splitting. At this point, the node
|
|
|
|
/// may also have invalid operands or may have other results that need
|
|
|
|
/// legalization, we just know that (at least) one result needs vector
|
|
|
|
/// splitting.
|
2008-07-10 15:25:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
|
2008-03-11 06:41:14 +00:00
|
|
|
DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Lo, Hi;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default:
|
|
|
|
#ifndef NDEBUG
|
2008-07-10 15:25:04 +00:00
|
|
|
cerr << "SplitVectorResult #" << ResNo << ": ";
|
2007-12-08 22:37:41 +00:00
|
|
|
N->dump(&DAG); cerr << "\n";
|
|
|
|
#endif
|
|
|
|
assert(0 && "Do not know how to split the result of this operator!");
|
|
|
|
abort();
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
|
|
|
|
case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
|
|
|
|
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
|
|
|
|
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
|
|
|
|
|
2008-11-10 04:46:22 +00:00
|
|
|
case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
|
|
|
|
case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
|
|
|
|
case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
|
2008-11-10 20:54:11 +00:00
|
|
|
case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
|
2008-11-10 04:46:22 +00:00
|
|
|
case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
|
|
|
|
case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
|
2008-07-16 11:41:33 +00:00
|
|
|
case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
|
2008-11-18 16:40:48 +00:00
|
|
|
case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
|
2008-07-16 11:41:33 +00:00
|
|
|
case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
|
2008-11-12 08:37:57 +00:00
|
|
|
case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
|
|
|
|
case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
|
2008-07-16 11:41:33 +00:00
|
|
|
|
2007-12-08 23:58:27 +00:00
|
|
|
case ISD::CTTZ:
|
|
|
|
case ISD::CTLZ:
|
|
|
|
case ISD::CTPOP:
|
|
|
|
case ISD::FNEG:
|
|
|
|
case ISD::FABS:
|
|
|
|
case ISD::FSQRT:
|
|
|
|
case ISD::FSIN:
|
|
|
|
case ISD::FCOS:
|
2008-08-21 17:55:02 +00:00
|
|
|
case ISD::FTRUNC:
|
|
|
|
case ISD::FFLOOR:
|
|
|
|
case ISD::FCEIL:
|
|
|
|
case ISD::FRINT:
|
|
|
|
case ISD::FNEARBYINT:
|
2007-12-08 23:58:27 +00:00
|
|
|
case ISD::FP_TO_SINT:
|
|
|
|
case ISD::FP_TO_UINT:
|
|
|
|
case ISD::SINT_TO_FP:
|
2008-10-20 16:31:21 +00:00
|
|
|
case ISD::TRUNCATE:
|
2008-07-27 12:28:43 +00:00
|
|
|
case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
|
2008-07-16 11:41:33 +00:00
|
|
|
|
2007-12-08 23:08:49 +00:00
|
|
|
case ISD::ADD:
|
|
|
|
case ISD::SUB:
|
|
|
|
case ISD::MUL:
|
|
|
|
case ISD::FADD:
|
|
|
|
case ISD::FSUB:
|
|
|
|
case ISD::FMUL:
|
|
|
|
case ISD::SDIV:
|
|
|
|
case ISD::UDIV:
|
|
|
|
case ISD::FDIV:
|
|
|
|
case ISD::FPOW:
|
|
|
|
case ISD::AND:
|
|
|
|
case ISD::OR:
|
|
|
|
case ISD::XOR:
|
|
|
|
case ISD::UREM:
|
|
|
|
case ISD::SREM:
|
2008-07-27 12:28:43 +00:00
|
|
|
case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
|
2007-12-08 22:37:41 +00:00
|
|
|
}
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
// If Lo/Hi is null, the sub-method took care of registering results etc.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (Lo.getNode())
|
2008-07-27 21:46:04 +00:00
|
|
|
SetSplitVector(SDValue(N, ResNo), Lo, Hi);
|
2007-12-08 22:37:41 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
|
|
|
SDValue LHSLo, LHSHi;
|
2008-07-16 11:41:33 +00:00
|
|
|
GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue RHSLo, RHSHi;
|
2008-07-16 11:41:33 +00:00
|
|
|
GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
|
|
|
|
|
|
|
|
Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
|
|
|
|
Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-07-16 11:41:33 +00:00
|
|
|
// We know the result is a vector. The input may be either a vector or a
|
|
|
|
// scalar value.
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT LoVT, HiVT;
|
2008-07-16 11:41:33 +00:00
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue InOp = N->getOperand(0);
|
2008-07-16 11:41:33 +00:00
|
|
|
MVT InVT = InOp.getValueType();
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-07-16 11:41:33 +00:00
|
|
|
// Handle some special cases efficiently.
|
|
|
|
switch (getTypeAction(InVT)) {
|
|
|
|
default:
|
|
|
|
assert(false && "Unknown type action!");
|
|
|
|
case Legal:
|
|
|
|
case PromoteInteger:
|
|
|
|
case SoftenFloat:
|
|
|
|
case ScalarizeVector:
|
|
|
|
break;
|
|
|
|
case ExpandInteger:
|
|
|
|
case ExpandFloat:
|
|
|
|
// A scalar to vector conversion, where the scalar needs expansion.
|
|
|
|
// If the vector is being split in two then we can just convert the
|
|
|
|
// expanded pieces.
|
|
|
|
if (LoVT == HiVT) {
|
|
|
|
GetExpandedOp(InOp, Lo, Hi);
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SplitVector:
|
|
|
|
// If the input is a vector that needs to be split, convert each split
|
|
|
|
// piece of the input now.
|
|
|
|
GetSplitVector(InOp, Lo, Hi);
|
|
|
|
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
|
|
|
return;
|
|
|
|
}
|
2008-07-14 17:27:46 +00:00
|
|
|
|
2008-07-16 11:41:33 +00:00
|
|
|
// In the general case, convert the input to an integer and split it by hand.
|
|
|
|
MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
|
|
|
|
MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(LoIntVT, HiIntVT);
|
2008-07-14 17:27:46 +00:00
|
|
|
|
2008-07-16 11:41:33 +00:00
|
|
|
SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
|
|
|
|
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-07-16 11:41:33 +00:00
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
unsigned LoNumElts = LoVT.getVectorNumElements();
|
2008-07-27 21:46:04 +00:00
|
|
|
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
|
2008-07-16 11:41:33 +00:00
|
|
|
Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
|
2008-07-16 11:41:33 +00:00
|
|
|
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-07-16 11:41:33 +00:00
|
|
|
assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
|
|
|
|
unsigned NumSubvectors = N->getNumOperands() / 2;
|
|
|
|
if (NumSubvectors == 1) {
|
|
|
|
Lo = N->getOperand(0);
|
|
|
|
Hi = N->getOperand(1);
|
|
|
|
return;
|
2008-07-14 17:27:46 +00:00
|
|
|
}
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-07-16 11:41:33 +00:00
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
|
2008-07-16 11:41:33 +00:00
|
|
|
Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
|
2008-07-16 11:41:33 +00:00
|
|
|
Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
|
|
|
|
}
|
|
|
|
|
2008-11-10 20:54:11 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
SDValue VLo, VHi;
|
|
|
|
GetSplitVector(N->getOperand(0), VLo, VHi);
|
|
|
|
SDValue DTyOpLo = DAG.getValueType(LoVT);
|
|
|
|
SDValue DTyOpHi = DAG.getValueType(HiVT);
|
|
|
|
SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
|
|
|
|
SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
|
|
|
|
|
|
|
|
SDValue RndOp = N->getOperand(3);
|
|
|
|
SDValue SatOp = N->getOperand(4);
|
|
|
|
ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
|
|
|
|
|
|
|
|
Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
|
|
|
|
Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
|
|
|
|
}
|
|
|
|
|
2008-11-10 04:46:22 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-11-12 08:37:57 +00:00
|
|
|
SDValue Vec = N->getOperand(0);
|
|
|
|
SDValue Idx = N->getOperand(1);
|
|
|
|
MVT IdxVT = Idx.getValueType();
|
|
|
|
|
2008-11-10 04:46:22 +00:00
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
2008-11-12 08:37:57 +00:00
|
|
|
// The indices are not guaranteed to be a multiple of the new vector
|
|
|
|
// size unless the original vector type was split in two.
|
|
|
|
assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
|
2008-11-10 04:46:22 +00:00
|
|
|
|
|
|
|
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
|
2008-11-12 08:37:57 +00:00
|
|
|
Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
|
|
|
|
DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
|
|
|
|
Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
|
2008-11-10 04:46:22 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-07-16 11:41:33 +00:00
|
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
|
|
Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
|
|
|
|
Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
|
2007-12-08 23:08:49 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
|
|
|
SDValue Vec = N->getOperand(0);
|
|
|
|
SDValue Elt = N->getOperand(1);
|
|
|
|
SDValue Idx = N->getOperand(2);
|
2008-06-17 14:27:01 +00:00
|
|
|
GetSplitVector(Vec, Lo, Hi);
|
2008-06-15 20:00:14 +00:00
|
|
|
|
|
|
|
if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
|
2008-09-12 16:56:44 +00:00
|
|
|
unsigned IdxVal = CIdx->getZExtValue();
|
2008-06-15 20:00:14 +00:00
|
|
|
unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
|
|
|
|
if (IdxVal < LoNumElts)
|
|
|
|
Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
|
|
|
|
else
|
|
|
|
Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
|
|
|
|
DAG.getIntPtrConstant(IdxVal - LoNumElts));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Spill the vector to the stack.
|
|
|
|
MVT VecVT = Vec.getValueType();
|
2008-07-14 17:32:02 +00:00
|
|
|
MVT EltVT = VecVT.getVectorElementType();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
|
|
|
|
SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
|
2008-06-15 20:00:14 +00:00
|
|
|
|
2008-07-14 17:32:02 +00:00
|
|
|
// Store the new element. This may be larger than the vector element type,
|
|
|
|
// so use a truncating store.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
|
2008-12-09 21:33:20 +00:00
|
|
|
unsigned Alignment =
|
|
|
|
TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
|
2008-07-14 17:32:02 +00:00
|
|
|
Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
|
2008-06-15 20:00:14 +00:00
|
|
|
|
2008-12-09 21:33:20 +00:00
|
|
|
// Load the Lo part from the stack slot.
|
|
|
|
Lo = DAG.getLoad(Lo.getValueType(), Store, StackPtr, NULL, 0);
|
|
|
|
|
|
|
|
// Increment the pointer to the other part.
|
|
|
|
unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
|
|
|
|
StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
|
|
|
|
DAG.getIntPtrConstant(IncrementSize));
|
2008-06-15 20:00:14 +00:00
|
|
|
|
2008-12-09 21:33:20 +00:00
|
|
|
// Load the Hi part from the stack slot.
|
|
|
|
Hi = DAG.getLoad(Hi.getValueType(), Store, StackPtr, NULL, 0, false,
|
|
|
|
MinAlign(Alignment, IncrementSize));
|
2007-12-08 23:58:27 +00:00
|
|
|
}
|
|
|
|
|
2008-11-18 16:40:48 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, LoVT, N->getOperand(0));
|
|
|
|
Hi = DAG.getNode(ISD::UNDEF, HiVT);
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-07-16 11:41:33 +00:00
|
|
|
assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
|
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
|
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ch = LD->getChain();
|
|
|
|
SDValue Ptr = LD->getBasePtr();
|
2008-08-14 20:04:46 +00:00
|
|
|
SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
|
2008-07-16 11:41:33 +00:00
|
|
|
const Value *SV = LD->getSrcValue();
|
|
|
|
int SVOffset = LD->getSrcValueOffset();
|
2008-08-14 20:04:46 +00:00
|
|
|
MVT MemoryVT = LD->getMemoryVT();
|
2008-07-16 11:41:33 +00:00
|
|
|
unsigned Alignment = LD->getAlignment();
|
|
|
|
bool isVolatile = LD->isVolatile();
|
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
MVT LoMemVT, HiMemVT;
|
|
|
|
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
|
2008-07-16 11:41:33 +00:00
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
|
|
|
|
SV, SVOffset, LoMemVT, isVolatile, Alignment);
|
2008-07-16 11:41:33 +00:00
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
|
|
|
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
|
|
|
DAG.getIntPtrConstant(IncrementSize));
|
|
|
|
SVOffset += IncrementSize;
|
|
|
|
Alignment = MinAlign(Alignment, IncrementSize);
|
|
|
|
Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
|
|
|
|
SV, SVOffset, HiMemVT, isVolatile, Alignment);
|
|
|
|
|
|
|
|
// Build a factor node to remember that this load is independent of the
|
|
|
|
// other one.
|
|
|
|
Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
|
|
|
|
Hi.getValue(1));
|
2008-07-16 11:41:33 +00:00
|
|
|
|
|
|
|
// Legalized the chain result - switch anything that used the old chain to
|
|
|
|
// use the new one.
|
2008-07-27 21:46:04 +00:00
|
|
|
ReplaceValueWith(SDValue(LD, 1), Ch);
|
2008-07-16 11:41:33 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-07-27 12:28:43 +00:00
|
|
|
// Get the dest types - they may not match the input types, e.g. int_to_fp.
|
2008-07-16 11:41:33 +00:00
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
|
2008-09-05 08:13:35 +00:00
|
|
|
// Split the input.
|
|
|
|
MVT InVT = N->getOperand(0).getValueType();
|
|
|
|
switch (getTypeAction(InVT)) {
|
|
|
|
default: assert(0 && "Unexpected type action!");
|
|
|
|
case Legal: {
|
|
|
|
assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
|
|
|
|
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
|
|
|
|
LoVT.getVectorNumElements());
|
|
|
|
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
|
|
|
|
DAG.getIntPtrConstant(0));
|
|
|
|
Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
|
|
|
|
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case SplitVector:
|
|
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-07-16 11:41:33 +00:00
|
|
|
Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
|
|
|
|
Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-11-15 09:25:38 +00:00
|
|
|
// The low and high parts of the original input give four input vectors.
|
|
|
|
SDValue Inputs[4];
|
|
|
|
GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
|
|
|
|
GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
|
|
|
|
MVT NewVT = Inputs[0].getValueType();
|
|
|
|
unsigned NewElts = NewVT.getVectorNumElements();
|
|
|
|
assert(NewVT == Inputs[1].getValueType() &&
|
|
|
|
"Non power-of-two vectors not supported!");
|
|
|
|
|
|
|
|
// If Lo or Hi uses elements from at most two of the four input vectors, then
|
|
|
|
// express it as a vector shuffle of those two inputs. Otherwise extract the
|
|
|
|
// input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Mask = N->getOperand(2);
|
2008-11-15 09:25:38 +00:00
|
|
|
MVT IdxVT = Mask.getValueType().getVectorElementType();
|
2008-07-27 21:46:04 +00:00
|
|
|
SmallVector<SDValue, 16> Ops;
|
2008-11-15 09:25:38 +00:00
|
|
|
Ops.reserve(NewElts);
|
|
|
|
for (unsigned High = 0; High < 2; ++High) {
|
|
|
|
SDValue &Output = High ? Hi : Lo;
|
|
|
|
|
|
|
|
// Build a shuffle mask for the output, discovering on the fly which
|
|
|
|
// input vectors to use as shuffle operands (recorded in InputUsed).
|
|
|
|
// If building a suitable shuffle vector proves too hard, then bail
|
|
|
|
// out with useBuildVector set.
|
|
|
|
unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
|
|
|
|
unsigned FirstMaskIdx = High * NewElts;
|
|
|
|
bool useBuildVector = false;
|
|
|
|
for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
|
|
|
|
SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
|
|
|
|
|
|
|
|
// The mask element. This indexes into the input.
|
|
|
|
unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
|
|
|
|
-1U : cast<ConstantSDNode>(Arg)->getZExtValue();
|
|
|
|
|
|
|
|
// The input vector this mask element indexes into.
|
|
|
|
unsigned Input = Idx / NewElts;
|
|
|
|
|
|
|
|
if (Input >= array_lengthof(Inputs)) {
|
|
|
|
// The mask element does not index into any input vector.
|
|
|
|
Ops.push_back(DAG.getNode(ISD::UNDEF, IdxVT));
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Turn the index into an offset from the start of the input vector.
|
|
|
|
Idx -= Input * NewElts;
|
|
|
|
|
|
|
|
// Find or create a shuffle vector operand to hold this input.
|
|
|
|
unsigned OpNo;
|
|
|
|
for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
|
|
|
|
if (InputUsed[OpNo] == Input) {
|
|
|
|
// This input vector is already an operand.
|
|
|
|
break;
|
|
|
|
} else if (InputUsed[OpNo] == -1U) {
|
|
|
|
// Create a new operand for this input vector.
|
|
|
|
InputUsed[OpNo] = Input;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (OpNo >= array_lengthof(InputUsed)) {
|
|
|
|
// More than two input vectors used! Give up on trying to create a
|
|
|
|
// shuffle vector. Insert all elements into a BUILD_VECTOR instead.
|
|
|
|
useBuildVector = true;
|
|
|
|
break;
|
2008-10-19 15:00:25 +00:00
|
|
|
}
|
2008-11-15 09:25:38 +00:00
|
|
|
|
|
|
|
// Add the mask index for the new shuffle vector.
|
|
|
|
Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
|
2007-12-08 23:58:27 +00:00
|
|
|
}
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-11-15 09:25:38 +00:00
|
|
|
if (useBuildVector) {
|
|
|
|
MVT EltVT = NewVT.getVectorElementType();
|
|
|
|
Ops.clear();
|
|
|
|
|
|
|
|
// Extract the input elements by hand.
|
|
|
|
for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
|
|
|
|
SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
|
|
|
|
|
|
|
|
// The mask element. This indexes into the input.
|
|
|
|
unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
|
|
|
|
-1U : cast<ConstantSDNode>(Arg)->getZExtValue();
|
|
|
|
|
|
|
|
// The input vector this mask element indexes into.
|
|
|
|
unsigned Input = Idx / NewElts;
|
|
|
|
|
|
|
|
if (Input >= array_lengthof(Inputs)) {
|
|
|
|
// The mask element is "undef" or indexes off the end of the input.
|
|
|
|
Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Turn the index into an offset from the start of the input vector.
|
|
|
|
Idx -= Input * NewElts;
|
|
|
|
|
|
|
|
// Extract the vector element by hand.
|
|
|
|
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT,
|
|
|
|
Inputs[Input], DAG.getIntPtrConstant(Idx)));
|
2008-11-10 04:46:22 +00:00
|
|
|
}
|
2008-11-15 09:25:38 +00:00
|
|
|
|
|
|
|
// Construct the Lo/Hi output using a BUILD_VECTOR.
|
|
|
|
Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &Ops[0], Ops.size());
|
|
|
|
} else if (InputUsed[0] == -1U) {
|
|
|
|
// No input vectors were used! The result is undefined.
|
|
|
|
Output = DAG.getNode(ISD::UNDEF, NewVT);
|
|
|
|
} else {
|
|
|
|
// At least one input vector was used. Create a new shuffle vector.
|
|
|
|
SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR,
|
|
|
|
MVT::getVectorVT(IdxVT, Ops.size()),
|
|
|
|
&Ops[0], Ops.size());
|
|
|
|
SDValue Op0 = Inputs[InputUsed[0]];
|
|
|
|
// If only one input was used, use an undefined vector for the other.
|
|
|
|
SDValue Op1 = InputUsed[1] == -1U ?
|
|
|
|
DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]];
|
|
|
|
Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask);
|
2007-12-08 23:58:27 +00:00
|
|
|
}
|
2008-11-15 09:25:38 +00:00
|
|
|
|
|
|
|
Ops.clear();
|
2007-12-08 23:58:27 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
|
|
|
|
SDValue &Hi) {
|
2008-07-22 23:54:03 +00:00
|
|
|
MVT LoVT, HiVT;
|
|
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue LL, LH, RL, RH;
|
2008-07-22 23:54:03 +00:00
|
|
|
GetSplitVector(N->getOperand(0), LL, LH);
|
|
|
|
GetSplitVector(N->getOperand(1), RL, RH);
|
|
|
|
|
|
|
|
Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
|
|
|
|
Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
|
|
|
|
}
|
|
|
|
|
2007-12-08 23:58:27 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Operand Vector Splitting
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2008-07-10 15:25:04 +00:00
|
|
|
/// SplitVectorOperand - This method is called when the specified operand of the
|
2007-12-08 22:37:41 +00:00
|
|
|
/// specified node is found to need vector splitting. At this point, all of the
|
|
|
|
/// result types of the node are known to be legal, but other operands of the
|
|
|
|
/// node may need legalization as well as the specified one.
|
2008-07-10 15:25:04 +00:00
|
|
|
bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
|
2007-12-08 22:37:41 +00:00
|
|
|
DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Res = SDValue();
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
if (Res.getNode() == 0) {
|
2007-12-08 22:37:41 +00:00
|
|
|
switch (N->getOpcode()) {
|
|
|
|
default:
|
|
|
|
#ifndef NDEBUG
|
2008-07-10 15:25:04 +00:00
|
|
|
cerr << "SplitVectorOperand Op #" << OpNo << ": ";
|
2007-12-08 22:37:41 +00:00
|
|
|
N->dump(&DAG); cerr << "\n";
|
|
|
|
#endif
|
|
|
|
assert(0 && "Do not know how to split this operator's operand!");
|
|
|
|
abort();
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2008-07-16 11:41:33 +00:00
|
|
|
case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
|
|
|
|
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
|
|
|
|
case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
|
|
|
|
case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
|
|
|
|
OpNo); break;
|
|
|
|
case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
|
2008-10-20 16:31:21 +00:00
|
|
|
|
|
|
|
case ISD::CTTZ:
|
|
|
|
case ISD::CTLZ:
|
|
|
|
case ISD::CTPOP:
|
|
|
|
case ISD::FP_TO_SINT:
|
|
|
|
case ISD::FP_TO_UINT:
|
|
|
|
case ISD::SINT_TO_FP:
|
|
|
|
case ISD::TRUNCATE:
|
|
|
|
case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
|
2007-12-08 22:37:41 +00:00
|
|
|
}
|
|
|
|
}
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
// If the result is null, the sub-method took care of registering results etc.
|
2008-08-28 21:40:38 +00:00
|
|
|
if (!Res.getNode()) return false;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-12-09 21:33:20 +00:00
|
|
|
// If the result is N, the sub-method updated N in place. Tell the legalizer
|
|
|
|
// core about this.
|
|
|
|
if (Res.getNode() == N)
|
2007-12-08 22:37:41 +00:00
|
|
|
return true;
|
2008-02-26 11:21:42 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
|
|
|
|
"Invalid operand expansion");
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
ReplaceValueWith(SDValue(N, 0), Res);
|
2007-12-08 22:37:41 +00:00
|
|
|
return false;
|
|
|
|
}
|
Implement splitting support for store, allowing us to compile:
%f8 = type <8 x float>
define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
%p = load %f8* %P ; <%f8> [#uses=1]
%q = load %f8* %Q ; <%f8> [#uses=1]
%R = add %f8 %p, %q ; <%f8> [#uses=1]
store %f8 %R, %f8* %S
ret void
}
into:
_test_f8:
movaps 16(%rdi), %xmm0
addps 16(%rsi), %xmm0
movaps (%rdi), %xmm1
addps (%rsi), %xmm1
movaps %xmm0, 16(%rdx)
movaps %xmm1, (%rdx)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44725 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-08 23:24:26 +00:00
|
|
|
|
2008-10-20 16:31:21 +00:00
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
|
|
|
|
// The result has a legal vector type, but the input needs splitting.
|
|
|
|
MVT ResVT = N->getValueType(0);
|
|
|
|
SDValue Lo, Hi;
|
|
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
|
|
assert(Lo.getValueType() == Hi.getValueType() &&
|
|
|
|
"Returns legal non-power-of-two vector type?");
|
|
|
|
MVT InVT = Lo.getValueType();
|
|
|
|
|
|
|
|
MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
|
|
|
|
InVT.getVectorNumElements());
|
|
|
|
|
|
|
|
Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
|
|
|
|
Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
|
|
|
|
// end up being split all the way down to individual components. Convert the
|
|
|
|
// split pieces into integers and reassemble.
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Lo, Hi;
|
2008-06-17 14:27:01 +00:00
|
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
Lo = BitConvertToInteger(Lo);
|
|
|
|
Hi = BitConvertToInteger(Hi);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
|
|
|
if (TLI.isBigEndian())
|
|
|
|
std::swap(Lo, Hi);
|
|
|
|
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
|
2008-03-11 06:41:14 +00:00
|
|
|
JoinIntegers(Lo, Hi));
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
|
2008-07-16 11:41:33 +00:00
|
|
|
// We know that the extracted result type is legal. For now, assume the index
|
|
|
|
// is a constant.
|
|
|
|
MVT SubVT = N->getValueType(0);
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Idx = N->getOperand(1);
|
|
|
|
SDValue Lo, Hi;
|
2008-07-16 11:41:33 +00:00
|
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
|
|
|
|
|
|
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
|
2008-09-12 16:56:44 +00:00
|
|
|
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
|
2008-07-16 11:41:33 +00:00
|
|
|
|
|
|
|
if (IdxVal < LoElts) {
|
|
|
|
assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
|
|
|
|
"Extracted subvector crosses vector split!");
|
|
|
|
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
|
|
|
|
} else {
|
|
|
|
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
|
|
|
|
DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
|
|
|
|
SDValue Vec = N->getOperand(0);
|
|
|
|
SDValue Idx = N->getOperand(1);
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VecVT = Vec.getValueType();
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
|
|
|
if (isa<ConstantSDNode>(Idx)) {
|
2008-09-12 16:56:44 +00:00
|
|
|
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
|
2008-06-06 12:08:01 +00:00
|
|
|
assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Lo, Hi;
|
2008-06-17 14:27:01 +00:00
|
|
|
GetSplitVector(Vec, Lo, Hi);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2008-06-06 12:08:01 +00:00
|
|
|
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
|
|
|
if (IdxVal < LoElts)
|
2008-07-27 21:46:04 +00:00
|
|
|
return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
else
|
2008-07-27 21:46:04 +00:00
|
|
|
return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
DAG.getConstant(IdxVal - LoElts,
|
|
|
|
Idx.getValueType()));
|
|
|
|
}
|
|
|
|
|
2008-06-15 20:00:14 +00:00
|
|
|
// Store the vector to the stack.
|
|
|
|
MVT EltVT = VecVT.getVectorElementType();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
|
|
|
|
SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2008-06-15 20:00:14 +00:00
|
|
|
// Load back the required element.
|
|
|
|
StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
|
2008-08-14 20:04:46 +00:00
|
|
|
assert(N->isUnindexed() && "Indexed store of vector?");
|
2008-07-16 11:41:33 +00:00
|
|
|
assert(OpNo == 1 && "Can only split the stored value");
|
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
bool isTruncating = N->isTruncatingStore();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ch = N->getChain();
|
|
|
|
SDValue Ptr = N->getBasePtr();
|
2008-07-16 11:41:33 +00:00
|
|
|
int SVOffset = N->getSrcValueOffset();
|
2008-08-14 20:04:46 +00:00
|
|
|
MVT MemoryVT = N->getMemoryVT();
|
2008-07-16 11:41:33 +00:00
|
|
|
unsigned Alignment = N->getAlignment();
|
|
|
|
bool isVol = N->isVolatile();
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Lo, Hi;
|
2008-07-16 11:41:33 +00:00
|
|
|
GetSplitVector(N->getOperand(1), Lo, Hi);
|
2008-02-20 17:38:09 +00:00
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
MVT LoMemVT, HiMemVT;
|
|
|
|
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
|
2008-02-20 17:38:09 +00:00
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
|
|
|
|
|
|
|
|
if (isTruncating)
|
|
|
|
Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
|
|
|
|
LoMemVT, isVol, Alignment);
|
|
|
|
else
|
|
|
|
Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
|
|
|
|
isVol, Alignment);
|
2008-07-16 11:41:33 +00:00
|
|
|
|
|
|
|
// Increment the pointer to the other half.
|
|
|
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
|
|
|
DAG.getIntPtrConstant(IncrementSize));
|
|
|
|
|
2008-08-14 20:04:46 +00:00
|
|
|
if (isTruncating)
|
|
|
|
Hi = DAG.getTruncStore(Ch, Hi, Ptr,
|
|
|
|
N->getSrcValue(), SVOffset+IncrementSize,
|
|
|
|
HiMemVT,
|
|
|
|
isVol, MinAlign(Alignment, IncrementSize));
|
|
|
|
else
|
|
|
|
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
|
|
|
isVol, MinAlign(Alignment, IncrementSize));
|
|
|
|
|
2008-07-16 11:41:33 +00:00
|
|
|
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
|
2008-02-20 17:38:09 +00:00
|
|
|
}
|
2008-02-27 13:03:44 +00:00
|
|
|
|
2008-10-19 15:00:25 +00:00
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
|
2008-02-27 13:03:44 +00:00
|
|
|
assert(OpNo == 2 && "Shuffle source type differs from result type?");
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Mask = N->getOperand(2);
|
2008-06-06 12:08:01 +00:00
|
|
|
unsigned MaskLength = Mask.getValueType().getVectorNumElements();
|
2008-02-27 13:03:44 +00:00
|
|
|
unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
|
|
|
|
unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
|
|
|
|
|
|
|
|
// Look for a legal vector type to place the mask values in.
|
|
|
|
// Note that there may not be *any* legal vector-of-integer
|
|
|
|
// type for which the element type is legal!
|
|
|
|
for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
|
|
|
|
EltVT <= MVT::LAST_INTEGER_VALUETYPE;
|
|
|
|
// Integer values types are consecutively numbered. Exploit this.
|
|
|
|
EltVT = MVT::SimpleValueType(EltVT + 1)) {
|
|
|
|
|
|
|
|
// Is the element type big enough to hold the values?
|
2008-06-06 12:08:01 +00:00
|
|
|
if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
|
2008-02-27 13:03:44 +00:00
|
|
|
// Nope.
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Is the vector type legal?
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
|
2008-02-27 13:03:44 +00:00
|
|
|
if (!isTypeLegal(VecVT))
|
|
|
|
// Nope.
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// If the element type is not legal, find a larger legal type to use for
|
|
|
|
// the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
|
2008-02-27 17:39:13 +00:00
|
|
|
// FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
|
|
|
|
// node where the shuffle mask is a list of integer operands, #2 .. #2+n.
|
2008-02-27 13:03:44 +00:00
|
|
|
for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
|
|
|
|
// Integer values types are consecutively numbered. Exploit this.
|
|
|
|
OpVT = MVT::SimpleValueType(OpVT + 1)) {
|
|
|
|
if (!isTypeLegal(OpVT))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Success! Rebuild the vector using the legal types.
|
2008-07-27 21:46:04 +00:00
|
|
|
SmallVector<SDValue, 16> Ops(MaskLength);
|
2008-02-27 13:03:44 +00:00
|
|
|
for (unsigned i = 0; i < MaskLength; ++i) {
|
2008-10-19 15:00:25 +00:00
|
|
|
SDValue Arg = Mask.getOperand(i);
|
|
|
|
if (Arg.getOpcode() == ISD::UNDEF) {
|
|
|
|
Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
|
|
|
|
} else {
|
|
|
|
uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
|
|
|
|
Ops[i] = DAG.getConstant(Idx, OpVT);
|
|
|
|
}
|
2008-02-27 13:03:44 +00:00
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
return DAG.UpdateNodeOperands(SDValue(N,0),
|
2008-02-27 13:03:44 +00:00
|
|
|
N->getOperand(0), N->getOperand(1),
|
|
|
|
DAG.getNode(ISD::BUILD_VECTOR,
|
|
|
|
VecVT, &Ops[0], Ops.size()));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Continuing is pointless - failure is certain.
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
assert(false && "Failed to find an appropriate mask type!");
|
2008-07-27 21:46:04 +00:00
|
|
|
return SDValue(N, 0);
|
2008-02-27 13:03:44 +00:00
|
|
|
}
|