2007-12-08 20:16:06 +00:00
|
|
|
//===-- LegalizeTypes.h - Definition of the DAG Type Legalizer class ------===//
|
|
|
|
|
//
|
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
|
//
|
2007-12-29 20:36:04 +00:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-12-08 20:16:06 +00:00
|
|
|
//
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
//
|
|
|
|
|
// This file defines the DAGTypeLegalizer class. This is a private interface
|
|
|
|
|
// shared between the code that implements the SelectionDAG::LegalizeTypes
|
|
|
|
|
// method.
|
|
|
|
|
//
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
#ifndef SELECTIONDAG_LEGALIZETYPES_H
|
|
|
|
|
#define SELECTIONDAG_LEGALIZETYPES_H
|
|
|
|
|
|
|
|
|
|
#define DEBUG_TYPE "legalize-types"
|
|
|
|
|
#include "llvm/CodeGen/SelectionDAG.h"
|
|
|
|
|
#include "llvm/Target/TargetLowering.h"
|
|
|
|
|
#include "llvm/ADT/DenseMap.h"
|
|
|
|
|
#include "llvm/Support/Compiler.h"
|
|
|
|
|
#include "llvm/Support/Debug.h"
|
|
|
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
2008-07-10 15:25:04 +00:00
|
|
|
/// DAGTypeLegalizer - This takes an arbitrary SelectionDAG as input and hacks
|
|
|
|
|
/// on it until only value types the target machine can handle are left. This
|
|
|
|
|
/// involves promoting small sizes to large sizes or splitting up large values
|
|
|
|
|
/// into small values.
|
2007-12-08 20:16:06 +00:00
|
|
|
///
|
|
|
|
|
class VISIBILITY_HIDDEN DAGTypeLegalizer {
|
|
|
|
|
TargetLowering &TLI;
|
|
|
|
|
SelectionDAG &DAG;
|
2008-02-03 07:13:32 +00:00
|
|
|
public:
|
2007-12-08 20:16:06 +00:00
|
|
|
// NodeIDFlags - This pass uses the NodeID on the SDNodes to hold information
|
|
|
|
|
// about the state of the node. The enum has all the values.
|
|
|
|
|
enum NodeIDFlags {
|
|
|
|
|
/// ReadyToProcess - All operands have been processed, so this node is ready
|
|
|
|
|
/// to be handled.
|
|
|
|
|
ReadyToProcess = 0,
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
/// NewNode - This is a new node that was created in the process of
|
|
|
|
|
/// legalizing some other node.
|
|
|
|
|
NewNode = -1,
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
/// Processed - This is a node that has already been processed.
|
|
|
|
|
Processed = -2
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
// 1+ - This is a node which has this many unlegalized operands.
|
|
|
|
|
};
|
2008-02-03 07:13:32 +00:00
|
|
|
private:
|
2007-12-08 20:16:06 +00:00
|
|
|
enum LegalizeAction {
|
2008-07-10 15:25:04 +00:00
|
|
|
Legal, // The target natively supports this type.
|
|
|
|
|
PromoteInteger, // Replace this integer type with a larger one.
|
|
|
|
|
ExpandInteger, // Split this integer type into two of half the size.
|
|
|
|
|
SoftenFloat, // Convert this float type to a same size integer type.
|
|
|
|
|
ExpandFloat, // Split this float type into two of half the size.
|
|
|
|
|
ScalarizeVector, // Replace this one-element vector with its element type.
|
|
|
|
|
SplitVector // This vector type should be split into smaller vectors.
|
2007-12-08 20:16:06 +00:00
|
|
|
};
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
/// ValueTypeActions - This is a bitvector that contains two bits for each
|
|
|
|
|
/// simple value type, where the two bits correspond to the LegalizeAction
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
/// enum from TargetLowering. This can be queried with "getTypeAction(VT)".
|
2007-12-08 20:16:06 +00:00
|
|
|
TargetLowering::ValueTypeActionImpl ValueTypeActions;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
/// getTypeAction - Return how we should legalize values of this type, either
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
/// it is already legal, or we need to promote it to a larger integer type, or
|
|
|
|
|
/// we need to expand it into multiple registers of a smaller integer type, or
|
2008-07-10 15:25:04 +00:00
|
|
|
/// we need to split a vector type into smaller vector types, or we need to
|
|
|
|
|
/// convert it to a different type of the same size.
|
2008-06-06 12:08:01 +00:00
|
|
|
LegalizeAction getTypeAction(MVT VT) const {
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
switch (ValueTypeActions.getTypeAction(VT)) {
|
|
|
|
|
default:
|
|
|
|
|
assert(false && "Unknown legalize action!");
|
|
|
|
|
case TargetLowering::Legal:
|
|
|
|
|
return Legal;
|
|
|
|
|
case TargetLowering::Promote:
|
2008-06-17 14:27:01 +00:00
|
|
|
return PromoteInteger;
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
case TargetLowering::Expand:
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
// Expand can mean
|
|
|
|
|
// 1) split scalar in half, 2) convert a float to an integer,
|
|
|
|
|
// 3) scalarize a single-element vector, 4) split a vector in two.
|
2008-06-06 12:08:01 +00:00
|
|
|
if (!VT.isVector()) {
|
2008-06-17 14:27:01 +00:00
|
|
|
if (VT.isInteger())
|
|
|
|
|
return ExpandInteger;
|
|
|
|
|
else if (VT.getSizeInBits() ==
|
|
|
|
|
TLI.getTypeToTransformTo(VT).getSizeInBits())
|
2008-06-20 17:49:55 +00:00
|
|
|
return SoftenFloat;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
else
|
2008-06-17 14:27:01 +00:00
|
|
|
return ExpandFloat;
|
2008-06-06 12:08:01 +00:00
|
|
|
} else if (VT.getVectorNumElements() == 1) {
|
2008-07-10 15:25:04 +00:00
|
|
|
return ScalarizeVector;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
} else {
|
2008-07-10 15:25:04 +00:00
|
|
|
return SplitVector;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
}
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
}
|
2007-12-08 20:16:06 +00:00
|
|
|
}
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
/// isTypeLegal - Return true if this type is legal on this target.
|
2008-06-06 12:08:01 +00:00
|
|
|
bool isTypeLegal(MVT VT) const {
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal;
|
2007-12-08 20:16:06 +00:00
|
|
|
}
|
LegalizeTypes support for EXTRACT_VECTOR_ELT. The
approach taken is different to that in LegalizeDAG
when it is a question of expanding or promoting the
result type: for example, if extracting an i64 from
a <2 x i64>, when i64 needs expanding, it bitcasts
the vector to <4 x i32>, extracts the appropriate
two i32's, and uses those for the Lo and Hi parts.
Likewise, when extracting an i16 from a <4 x i16>,
and i16 needs promoting, it bitcasts the vector to
<2 x i32>, extracts the appropriate i32, twiddles
the bits if necessary, and uses that as the promoted
value. This puts more pressure on bitcast legalization,
and I've added the appropriate cases. They needed to
be added anyway since users can generate such bitcasts
too if they want to. Also, when considering various
cases (Legal, Promote, Expand, Scalarize, Split) it is
a pain that expand can correspond to Expand, Scalarize
or Split, so I've changed the LegalizeTypes enum so it
lists those different cases - now Expand only means
splitting a scalar in two.
The code produced is the same as by LegalizeDAG for
all relevant testcases, except for
2007-10-31-extractelement-i64.ll, where the code seems
to have improved (see below; can an expert please tell
me if it is better or not).
Before < vs after >.
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 28(%esp)
< movl (%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 28(%esp)
< movl 8(%esp), %eax
< movl %eax, 24(%esp)
< movq 24(%esp), %mm0
< movq %mm0, 56(%esp)
---
> subl $44, %esp
> movaps %xmm0, 16(%esp)
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movq (%esp), %mm0
> movq %mm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 16(%esp), %eax
< movl %eax, 48(%esp)
< movl 20(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 4(%esp), %eax
< movl %eax, 60(%esp)
< movl (%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $1, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
< subl $92, %esp
< movaps %xmm0, 64(%esp)
---
> subl $44, %esp
< movl 24(%esp), %eax
< movl %eax, 48(%esp)
< movl 28(%esp), %eax
< movl %eax, 52(%esp)
< movaps %xmm0, (%esp)
< movl 12(%esp), %eax
< movl %eax, 60(%esp)
< movl 8(%esp), %eax
< movl %eax, 56(%esp)
---
> pshufd $3, %xmm0, %xmm1
> movd %xmm1, 4(%esp)
> movhlps %xmm0, %xmm0
> movd %xmm0, (%esp)
> movd %xmm1, 12(%esp)
> movd %xmm0, 8(%esp)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-27 13:34:40 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
/// PromotedIntegers - For integer nodes that are below legal width, this map
|
|
|
|
|
/// indicates what promoted value to use.
|
|
|
|
|
DenseMap<SDOperand, SDOperand> PromotedIntegers;
|
|
|
|
|
|
|
|
|
|
/// ExpandedIntegers - For integer nodes that need to be expanded this map
|
|
|
|
|
/// indicates which operands are the expanded version of the input.
|
|
|
|
|
DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedIntegers;
|
2007-12-08 20:16:06 +00:00
|
|
|
|
2008-06-20 17:49:55 +00:00
|
|
|
/// SoftenedFloats - For floating point nodes converted to integers of
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
/// the same size, this map indicates the converted value to use.
|
2008-06-20 17:49:55 +00:00
|
|
|
DenseMap<SDOperand, SDOperand> SoftenedFloats;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
/// ExpandedFloats - For float nodes that need to be expanded this map
|
|
|
|
|
/// indicates which operands are the expanded version of the input.
|
|
|
|
|
DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedFloats;
|
|
|
|
|
|
|
|
|
|
/// ScalarizedVectors - For nodes that are <1 x ty>, this map indicates the
|
2007-12-08 20:16:06 +00:00
|
|
|
/// scalar value of type 'ty' to use.
|
2008-06-17 14:27:01 +00:00
|
|
|
DenseMap<SDOperand, SDOperand> ScalarizedVectors;
|
2007-12-08 22:40:18 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
/// SplitVectors - For nodes that need to be split this map indicates
|
2007-12-08 22:40:18 +00:00
|
|
|
/// which operands are the expanded version of the input.
|
2008-06-17 14:27:01 +00:00
|
|
|
DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > SplitVectors;
|
|
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
/// ReplacedNodes - For nodes that have been replaced with another,
|
|
|
|
|
/// indicates the replacement node to use.
|
2008-04-16 16:15:27 +00:00
|
|
|
DenseMap<SDOperand, SDOperand> ReplacedNodes;
|
2007-12-08 20:16:06 +00:00
|
|
|
|
|
|
|
|
/// Worklist - This defines a worklist of nodes to process. In order to be
|
|
|
|
|
/// pushed onto this worklist, all operands of a node must have already been
|
|
|
|
|
/// processed.
|
|
|
|
|
SmallVector<SDNode*, 128> Worklist;
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
public:
|
|
|
|
|
explicit DAGTypeLegalizer(SelectionDAG &dag)
|
|
|
|
|
: TLI(dag.getTargetLoweringInfo()), DAG(dag),
|
|
|
|
|
ValueTypeActions(TLI.getValueTypeActions()) {
|
|
|
|
|
assert(MVT::LAST_VALUETYPE <= 32 &&
|
|
|
|
|
"Too many value types for ValueTypeActions to hold!");
|
2008-06-17 14:27:01 +00:00
|
|
|
}
|
|
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
void run();
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-02-26 11:21:42 +00:00
|
|
|
/// ReanalyzeNode - Recompute the NodeID and correct processed operands
|
|
|
|
|
/// for the specified node, adding it to the worklist if ready.
|
|
|
|
|
void ReanalyzeNode(SDNode *N) {
|
2008-02-03 07:08:51 +00:00
|
|
|
N->setNodeId(NewNode);
|
2008-02-26 11:21:42 +00:00
|
|
|
AnalyzeNewNode(N);
|
2008-02-03 07:08:51 +00:00
|
|
|
}
|
2008-02-26 11:21:42 +00:00
|
|
|
|
2008-07-02 09:56:41 +00:00
|
|
|
void NoteDeletion(SDNode *Old, SDNode *New) {
|
|
|
|
|
ExpungeNode(Old);
|
|
|
|
|
ExpungeNode(New);
|
|
|
|
|
for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
|
|
|
|
|
ReplacedNodes[SDOperand(Old, i)] = SDOperand(New, i);
|
2008-06-11 11:42:12 +00:00
|
|
|
}
|
|
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
private:
|
2008-02-26 11:21:42 +00:00
|
|
|
void AnalyzeNewNode(SDNode *&N);
|
|
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
void ReplaceValueWith(SDOperand From, SDOperand To);
|
|
|
|
|
void ReplaceNodeWith(SDNode *From, SDNode *To);
|
|
|
|
|
|
|
|
|
|
void RemapNode(SDOperand &N);
|
2008-07-02 09:56:41 +00:00
|
|
|
void ExpungeNode(SDNode *N);
|
2007-12-08 20:16:06 +00:00
|
|
|
|
2007-12-08 21:59:32 +00:00
|
|
|
// Common routines.
|
2008-06-06 12:08:01 +00:00
|
|
|
SDOperand CreateStackStoreLoad(SDOperand Op, MVT DestVT);
|
2008-06-15 20:00:14 +00:00
|
|
|
SDOperand MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
|
|
|
|
|
const SDOperand *Ops, unsigned NumOps, bool isSigned);
|
|
|
|
|
|
|
|
|
|
SDOperand BitConvertToInteger(SDOperand Op);
|
2008-03-11 06:41:14 +00:00
|
|
|
SDOperand JoinIntegers(SDOperand Lo, SDOperand Hi);
|
|
|
|
|
void SplitInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
|
2008-06-06 12:08:01 +00:00
|
|
|
void SplitInteger(SDOperand Op, MVT LoVT, MVT HiVT,
|
2008-03-11 06:41:14 +00:00
|
|
|
SDOperand &Lo, SDOperand &Hi);
|
2008-06-15 20:00:14 +00:00
|
|
|
|
|
|
|
|
SDOperand GetVectorElementPointer(SDOperand VecPtr, MVT EltVT,
|
|
|
|
|
SDOperand Index);
|
2007-12-08 21:59:32 +00:00
|
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Integer Promotion Support: LegalizeIntegerTypes.cpp
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
|
SDOperand GetPromotedInteger(SDOperand Op) {
|
|
|
|
|
SDOperand &PromotedOp = PromotedIntegers[Op];
|
2007-12-08 20:16:06 +00:00
|
|
|
RemapNode(PromotedOp);
|
|
|
|
|
assert(PromotedOp.Val && "Operand wasn't promoted?");
|
|
|
|
|
return PromotedOp;
|
|
|
|
|
}
|
2008-06-17 14:27:01 +00:00
|
|
|
void SetPromotedInteger(SDOperand Op, SDOperand Result);
|
|
|
|
|
|
|
|
|
|
/// ZExtPromotedInteger - Get a promoted operand and zero extend it to the
|
|
|
|
|
/// final size.
|
|
|
|
|
SDOperand ZExtPromotedInteger(SDOperand Op) {
|
2008-06-06 12:08:01 +00:00
|
|
|
MVT OldVT = Op.getValueType();
|
2008-06-17 14:27:01 +00:00
|
|
|
Op = GetPromotedInteger(Op);
|
2007-12-08 20:16:06 +00:00
|
|
|
return DAG.getZeroExtendInReg(Op, OldVT);
|
2008-06-17 14:27:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Integer Result Promotion.
|
|
|
|
|
void PromoteIntegerResult(SDNode *N, unsigned ResNo);
|
|
|
|
|
SDOperand PromoteIntRes_BIT_CONVERT(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_BUILD_PAIR(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_Constant(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_CTLZ(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_CTPOP(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_CTTZ(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_FP_TO_XINT(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_INT_EXTEND(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_LOAD(LoadSDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SDIV(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SELECT (SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SELECT_CC(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SETCC(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SHL(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SimpleIntBinOp(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SRA(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_SRL(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_TRUNCATE(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_UDIV(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntRes_UNDEF(SDNode *N);
|
2008-06-30 13:55:15 +00:00
|
|
|
SDOperand PromoteIntRes_VAARG(SDNode *N);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
|
// Integer Operand Promotion.
|
|
|
|
|
bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
|
|
|
|
|
SDOperand PromoteIntOp_ANY_EXTEND(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_BUILD_PAIR(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand PromoteIntOp_BUILD_VECTOR(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_FP_EXTEND(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_FP_ROUND(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_INT_TO_FP(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand PromoteIntOp_MEMBARRIER(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
|
2008-06-30 11:50:11 +00:00
|
|
|
SDOperand PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
|
2008-06-17 14:27:01 +00:00
|
|
|
SDOperand PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand PromoteIntOp_SIGN_EXTEND(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand PromoteIntOp_TRUNCATE(SDNode *N);
|
|
|
|
|
SDOperand PromoteIntOp_ZERO_EXTEND(SDNode *N);
|
2008-02-15 19:34:17 +00:00
|
|
|
|
2007-12-08 21:59:32 +00:00
|
|
|
void PromoteSetCCOperands(SDOperand &LHS,SDOperand &RHS, ISD::CondCode Code);
|
|
|
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Integer Expansion Support: LegalizeIntegerTypes.cpp
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
|
void GetExpandedInteger(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SetExpandedInteger(SDOperand Op, SDOperand Lo, SDOperand Hi);
|
|
|
|
|
|
|
|
|
|
// Integer Result Expansion.
|
|
|
|
|
void ExpandIntegerResult(SDNode *N, unsigned ResNo);
|
|
|
|
|
void ExpandIntRes_ANY_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_AssertZext (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_Constant (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_CTLZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_CTPOP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_CTTZ (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_LOAD (LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_TRUNCATE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_FP_TO_SINT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_FP_TO_UINT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
|
|
|
|
|
void ExpandIntRes_Logical (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_ADDSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_ADDSUBC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_ADDSUBE (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-23 15:08:15 +00:00
|
|
|
void ExpandIntRes_BSWAP (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
void ExpandIntRes_MUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_SDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_SREM (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_UDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_UREM (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandIntRes_Shift (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
|
|
|
|
|
void ExpandShiftByConstant(SDNode *N, unsigned Amt,
|
2007-12-08 20:16:06 +00:00
|
|
|
SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
bool ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
// Integer Operand Expansion.
|
|
|
|
|
bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
|
|
|
|
|
SDOperand ExpandIntOp_BIT_CONVERT(SDNode *N);
|
|
|
|
|
SDOperand ExpandIntOp_BR_CC(SDNode *N);
|
|
|
|
|
SDOperand ExpandIntOp_BUILD_VECTOR(SDNode *N);
|
|
|
|
|
SDOperand ExpandIntOp_EXTRACT_ELEMENT(SDNode *N);
|
2008-06-25 16:34:21 +00:00
|
|
|
SDOperand ExpandIntOp_SELECT_CC(SDNode *N);
|
2008-06-17 14:27:01 +00:00
|
|
|
SDOperand ExpandIntOp_SETCC(SDNode *N);
|
|
|
|
|
SDOperand ExpandIntOp_SINT_TO_FP(SDOperand Source, MVT DestTy);
|
|
|
|
|
SDOperand ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand ExpandIntOp_TRUNCATE(SDNode *N);
|
|
|
|
|
SDOperand ExpandIntOp_UINT_TO_FP(SDOperand Source, MVT DestTy);
|
2008-02-16 10:29:26 +00:00
|
|
|
|
2008-06-25 16:34:21 +00:00
|
|
|
void IntegerExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
|
|
|
|
|
ISD::CondCode &CCCode);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Float to Integer Conversion Support: LegalizeFloatTypes.cpp
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
2008-06-20 17:49:55 +00:00
|
|
|
SDOperand GetSoftenedFloat(SDOperand Op) {
|
|
|
|
|
SDOperand &SoftenedOp = SoftenedFloats[Op];
|
|
|
|
|
RemapNode(SoftenedOp);
|
|
|
|
|
assert(SoftenedOp.Val && "Operand wasn't converted to integer?");
|
|
|
|
|
return SoftenedOp;
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
}
|
2008-06-20 17:49:55 +00:00
|
|
|
void SetSoftenedFloat(SDOperand Op, SDOperand Result);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
|
|
|
|
// Result Float to Integer Conversion.
|
2008-06-20 17:49:55 +00:00
|
|
|
void SoftenFloatResult(SDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand SoftenFloatRes_BIT_CONVERT(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_BUILD_PAIR(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_ConstantFP(ConstantFPSDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_FADD(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_FCOPYSIGN(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_FMUL(SDNode *N);
|
2008-07-08 10:50:55 +00:00
|
|
|
SDOperand SoftenFloatRes_FP_EXTEND(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_FP_ROUND(SDNode *N);
|
2008-07-09 11:11:47 +00:00
|
|
|
SDOperand SoftenFloatRes_FPOWI(SDNode *N);
|
2008-06-20 17:49:55 +00:00
|
|
|
SDOperand SoftenFloatRes_FSUB(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_LOAD(SDNode *N);
|
2008-07-08 20:03:24 +00:00
|
|
|
SDOperand SoftenFloatRes_SELECT(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_SELECT_CC(SDNode *N);
|
2008-07-09 12:07:22 +00:00
|
|
|
SDOperand SoftenFloatRes_SINT_TO_FP(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatRes_UINT_TO_FP(SDNode *N);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
|
|
|
|
// Operand Float to Integer Conversion.
|
2008-06-20 17:49:55 +00:00
|
|
|
bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand SoftenFloatOp_BIT_CONVERT(SDNode *N);
|
2008-06-25 16:34:21 +00:00
|
|
|
SDOperand SoftenFloatOp_BR_CC(SDNode *N);
|
2008-07-09 11:13:46 +00:00
|
|
|
SDOperand SoftenFloatOp_FP_TO_SINT(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatOp_FP_TO_UINT(SDNode *N);
|
2008-06-25 16:34:21 +00:00
|
|
|
SDOperand SoftenFloatOp_SELECT_CC(SDNode *N);
|
|
|
|
|
SDOperand SoftenFloatOp_SETCC(SDNode *N);
|
2008-07-07 00:08:12 +00:00
|
|
|
SDOperand SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
|
2008-06-25 16:34:21 +00:00
|
|
|
|
|
|
|
|
void SoftenSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
|
|
|
|
|
ISD::CondCode &CCCode);
|
Initial soft-float support for LegalizeTypes. I rewrote
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit... I also generalized it to work for
any sized floating point types, and removed the bogosity:
SDOperand Mask1 = (SrcVT == MVT::f64)
? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
: DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant! So I just
generate this integer constant directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 21:27:04 +00:00
|
|
|
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Float Expansion Support: LegalizeFloatTypes.cpp
|
2007-12-08 21:59:32 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
|
void GetExpandedFloat(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SetExpandedFloat(SDOperand Op, SDOperand Lo, SDOperand Hi);
|
|
|
|
|
|
|
|
|
|
// Float Result Expansion.
|
|
|
|
|
void ExpandFloatResult(SDNode *N, unsigned ResNo);
|
2008-06-25 20:24:48 +00:00
|
|
|
void ExpandFloatRes_ConstantFP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandFloatRes_FADD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandFloatRes_FDIV (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandFloatRes_FMUL (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandFloatRes_FSUB (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandFloatRes_LOAD (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
|
// Float Operand Expansion.
|
|
|
|
|
bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
|
2008-06-25 16:34:21 +00:00
|
|
|
SDOperand ExpandFloatOp_BR_CC(SDNode *N);
|
2008-06-25 20:24:48 +00:00
|
|
|
SDOperand ExpandFloatOp_FP_ROUND(SDNode *N);
|
|
|
|
|
SDOperand ExpandFloatOp_FP_TO_SINT(SDNode *N);
|
|
|
|
|
SDOperand ExpandFloatOp_FP_TO_UINT(SDNode *N);
|
2008-06-25 16:34:21 +00:00
|
|
|
SDOperand ExpandFloatOp_SELECT_CC(SDNode *N);
|
|
|
|
|
SDOperand ExpandFloatOp_SETCC(SDNode *N);
|
2008-06-21 17:00:47 +00:00
|
|
|
SDOperand ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
2008-06-25 16:34:21 +00:00
|
|
|
void FloatExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
|
|
|
|
|
ISD::CondCode &CCCode);
|
|
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
// Scalarization Support: LegalizeVectorTypes.cpp
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
SDOperand GetScalarizedVector(SDOperand Op) {
|
|
|
|
|
SDOperand &ScalarizedOp = ScalarizedVectors[Op];
|
|
|
|
|
RemapNode(ScalarizedOp);
|
|
|
|
|
assert(ScalarizedOp.Val && "Operand wasn't scalarized?");
|
|
|
|
|
return ScalarizedOp;
|
2007-12-08 21:59:32 +00:00
|
|
|
}
|
2008-06-17 14:27:01 +00:00
|
|
|
void SetScalarizedVector(SDOperand Op, SDOperand Result);
|
|
|
|
|
|
|
|
|
|
// Vector Result Scalarization: <1 x ty> -> ty.
|
2008-07-10 15:25:04 +00:00
|
|
|
void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
|
2008-06-20 18:40:50 +00:00
|
|
|
SDOperand ScalarizeVecRes_BinOp(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecRes_UnaryOp(SDNode *N);
|
2008-02-27 10:18:23 +00:00
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
SDOperand ScalarizeVecRes_BIT_CONVERT(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecRes_FPOWI(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecRes_LOAD(LoadSDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecRes_SELECT(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecRes_UNDEF(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
|
2008-02-27 10:18:23 +00:00
|
|
|
|
2008-06-17 14:27:01 +00:00
|
|
|
// Vector Operand Scalarization: <1 x ty> -> ty.
|
2008-07-10 15:25:04 +00:00
|
|
|
bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
|
2008-06-20 18:40:50 +00:00
|
|
|
SDOperand ScalarizeVecOp_BIT_CONVERT(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
|
|
|
|
|
SDOperand ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
|
2007-12-08 20:16:06 +00:00
|
|
|
|
2007-12-08 22:37:41 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
// Vector Splitting Support: LegalizeVectorTypes.cpp
|
2007-12-08 22:37:41 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
|
void GetSplitVector(SDOperand Op, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SetSplitVector(SDOperand Op, SDOperand Lo, SDOperand Hi);
|
|
|
|
|
|
|
|
|
|
// Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
|
2008-07-10 15:25:04 +00:00
|
|
|
void SplitVectorResult(SDNode *N, unsigned OpNo);
|
2007-12-08 23:08:49 +00:00
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
void SplitVecRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_BUILD_PAIR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2007-12-08 23:58:27 +00:00
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
void SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-17 14:27:01 +00:00
|
|
|
|
|
|
|
|
// Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
|
2008-07-10 15:25:04 +00:00
|
|
|
bool SplitVectorOperand(SDNode *N, unsigned OpNo);
|
2008-02-20 17:38:09 +00:00
|
|
|
|
2008-06-20 18:40:50 +00:00
|
|
|
SDOperand SplitVecOp_BIT_CONVERT(SDNode *N);
|
|
|
|
|
SDOperand SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
|
|
|
|
|
SDOperand SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
|
|
|
|
|
SDOperand SplitVecOp_RET(SDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
|
|
|
|
|
SDOperand SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo);
|
|
|
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
// Generic Splitting: LegalizeTypesGeneric.cpp
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
// Legalization methods which only use that the illegal type is split into two
|
|
|
|
|
// not necessarily identical types. As such they can be used for splitting
|
|
|
|
|
// vectors and expanding integers and floats.
|
|
|
|
|
|
|
|
|
|
void GetSplitOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) {
|
|
|
|
|
if (Op.getValueType().isVector())
|
|
|
|
|
GetSplitVector(Op, Lo, Hi);
|
|
|
|
|
else if (Op.getValueType().isInteger())
|
|
|
|
|
GetExpandedInteger(Op, Lo, Hi);
|
|
|
|
|
else
|
|
|
|
|
GetExpandedFloat(Op, Lo, Hi);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
|
|
|
|
|
/// which is split (or expanded) into two not necessarily identical pieces.
|
|
|
|
|
void GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT);
|
|
|
|
|
|
|
|
|
|
// Generic Result Splitting.
|
|
|
|
|
void SplitRes_MERGE_VALUES(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitRes_SELECT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitRes_SELECT_CC (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void SplitRes_UNDEF (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
// Generic Expansion: LegalizeTypesGeneric.cpp
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
// Legalization methods which only use that the illegal type is split into two
|
|
|
|
|
// identical types of half the size, and that the Lo/Hi part is stored first
|
|
|
|
|
// in memory on little/big-endian machines, followed by the Hi/Lo part. As
|
|
|
|
|
// such they can be used for expanding integers and floats.
|
|
|
|
|
|
|
|
|
|
void GetExpandedOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi) {
|
|
|
|
|
if (Op.getValueType().isInteger())
|
|
|
|
|
GetExpandedInteger(Op, Lo, Hi);
|
|
|
|
|
else
|
|
|
|
|
GetExpandedFloat(Op, Lo, Hi);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Generic Result Expansion.
|
|
|
|
|
void ExpandRes_BIT_CONVERT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
|
|
|
|
void ExpandRes_BUILD_PAIR (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-23 15:08:15 +00:00
|
|
|
void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-20 18:40:50 +00:00
|
|
|
void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-23 14:19:45 +00:00
|
|
|
void ExpandRes_NormalLoad (SDNode *N, SDOperand &Lo, SDOperand &Hi);
|
2008-06-20 18:40:50 +00:00
|
|
|
|
|
|
|
|
// Generic Operand Expansion.
|
|
|
|
|
SDOperand ExpandOp_BIT_CONVERT (SDNode *N);
|
|
|
|
|
SDOperand ExpandOp_BUILD_VECTOR (SDNode *N);
|
|
|
|
|
SDOperand ExpandOp_EXTRACT_ELEMENT(SDNode *N);
|
2008-06-23 14:19:45 +00:00
|
|
|
SDOperand ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
|
2008-06-20 18:40:50 +00:00
|
|
|
|
2007-12-08 20:16:06 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
} // end namespace llvm.
|
|
|
|
|
|
|
|
|
|
#endif
|
