2013-03-13 00:54:29 +00:00
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//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 16:26:38 +00:00
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
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#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
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2013-03-13 00:54:29 +00:00
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#include "MipsISelLowering.h"
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2013-03-30 01:12:05 +00:00
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#include "MipsRegisterInfo.h"
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2013-03-13 00:54:29 +00:00
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namespace llvm {
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class MipsSETargetLowering : public MipsTargetLowering {
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public:
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2014-09-19 23:30:42 +00:00
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explicit MipsSETargetLowering(const MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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2013-03-13 00:54:29 +00:00
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2013-09-23 12:02:46 +00:00
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/// \brief Enable MSA support for the given integer type and Register
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/// class.
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void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
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/// \brief Enable MSA support for the given floating-point type and
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/// Register class.
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void addMSAFloatType(MVT::SimpleValueType Ty,
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const TargetRegisterClass *RC);
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-15 12:24:57 +00:00
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2014-07-27 17:46:40 +00:00
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0,
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unsigned Align = 1,
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bool *Fast = nullptr) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const override;
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
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EVT VT) const override {
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return false;
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}
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2014-07-02 23:18:40 +00:00
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const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
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private:
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bool isEligibleForTailCallOptimization(
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const CCState &CCInfo, unsigned NextStackOffset,
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const MipsFunctionInfo &FI) const override;
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void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
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SDValue Chain) const override;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
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SelectionDAG &DAG) const;
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2013-04-13 02:13:30 +00:00
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
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/// depending on the indices in the shuffle.
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SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned BranchOp) const;
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2013-09-27 12:17:32 +00:00
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/// \brief Emit the COPY_FW pseudo instruction
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MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the COPY_FD pseudo instruction
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MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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2013-09-27 12:31:32 +00:00
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/// \brief Emit the INSERT_FW pseudo instruction
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MachineBasicBlock *emitINSERT_FW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the INSERT_FD pseudo instruction
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MachineBasicBlock *emitINSERT_FD(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
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MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned EltSizeInBytes,
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bool IsFP) const;
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/// \brief Emit the FILL_FW pseudo instruction
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MachineBasicBlock *emitFILL_FW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the FILL_FD pseudo instruction
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MachineBasicBlock *emitFILL_FD(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the FEXP2_W_1 pseudo instructions.
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MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the FEXP2_D_1 pseudo instructions.
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MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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};
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}
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#endif
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