U test/Makefile
U Makefile.rules
--- Merging r127240 into '.':
U utils/llvm-lit/Makefile
--- Merging r127726 into '.':
U lib/Support/raw_ostream.cpp
--- Merging r127730 into '.':
U test/CodeGen/X86/dyn-stackalloc.ll
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U test/CodeGen/X86/byval2.ll
U test/CodeGen/X86/byval4.ll
U test/CodeGen/X86/byval.ll
U test/CodeGen/X86/byval3.ll
U test/CodeGen/X86/byval5.ll
--- Merging r127732 into '.':
U test/CodeGen/X86/stdarg.ll
U test/CodeGen/X86/fold-mul-lohi.ll
U test/CodeGen/X86/scalar-min-max-fill-operand.ll
U test/CodeGen/X86/tailcallbyval64.ll
U test/CodeGen/X86/stride-reuse.ll
U test/CodeGen/X86/sse-align-3.ll
U test/CodeGen/X86/sse-commute.ll
U test/CodeGen/X86/stride-nine-with-base-reg.ll
U test/CodeGen/X86/coalescer-commute2.ll
U test/CodeGen/X86/sse-align-7.ll
U test/CodeGen/X86/sse_reload_fold.ll
U test/CodeGen/X86/sse-align-0.ll
--- Merging r127733 into '.':
U test/CodeGen/X86/peep-vector-extract-concat.ll
U test/CodeGen/X86/pmulld.ll
U test/CodeGen/X86/widen_load-0.ll
U test/CodeGen/X86/v2f32.ll
U test/CodeGen/X86/apm.ll
U test/CodeGen/X86/h-register-store.ll
U test/CodeGen/X86/h-registers-0.ll
--- Merging r127734 into '.':
U test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll
U test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
U test/CodeGen/X86/avoid-lea-scale2.ll
U test/CodeGen/X86/lea-3.ll
U test/CodeGen/X86/vec_set-8.ll
U test/CodeGen/X86/i64-mem-copy.ll
U test/CodeGen/X86/x86-64-malloc.ll
U test/CodeGen/X86/mmx-copy-gprs.ll
U test/CodeGen/X86/vec_shuffle-17.ll
U test/CodeGen/X86/2007-07-18-Vector-Extract.ll
--- Merging r127775 into '.':
U test/CodeGen/X86/constant-pool-remat-0.ll
--- Merging r127872 into '.':
U utils/lit/lit/TestingConfig.py
U lib/Support/raw_ostream.cpp
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U include/llvm/Target/TargetLowering.h
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86ISelLowering.h
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Transforms/Scalar/CodeGenPrepare.cpp
--- Merging r128194 into '.':
G lib/Transforms/Scalar/CodeGenPrepare.cpp
--- Merging r128196 into '.':
G lib/Transforms/Scalar/CodeGenPrepare.cpp
--- Merging r128197 into '.':
A test/CodeGen/X86/tailcall-returndup-void.ll
G lib/Transforms/Scalar/CodeGenPrepare.cpp
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--- Merging r127350 into '.':
D test/CodeGen/X86/2009-03-11-CoalescerBug.ll
--- Merging r127351 into '.':
A test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll
U test/CodeGen/X86/fold-pcmpeqd-2.ll
U lib/CodeGen/SimpleRegisterCoalescing.cpp
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it. It's been assumed up til now that it would be in its immediate
successor. However, this isn't necessarily the case. It could be in one of its
successor's successors.
Modify the code to more thoroughly check for an 'eh.selector' call in
successors. It only looks at a successor if we get there as a result of an
unconditional branch.
Testcase ObjC/exceptions-4.m in r126968.
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InstAlias<{alias}, {aliasee}>;
The InstAlias instruction should be able to go from the MCInst to the
{alias}. All of the information is there to match the MCInst with the
{aliasee}. From there, it's a simple matter to emit the {alias}, with the
correct operands from the {aliasee}.
The code this patch generates can be used by the InstPrinter to automatically
print out the alias without having to write special C++ code to handle the
situation.
This is a WIP, and therefore are several limitations. For instance, it cannot
handle AsmOperands at the moment. It also doesn't know what to do when two
{alias}es match the same {aliasee}. (Currently, it just ignores those two cases
and allows the printInstruction method to handle them.)
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encoding. It's up to the individual back-ends to convert it to their preferred
representation when printing.
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beginning of the "main" function. The assembler complains about the invalid
suffix for the 'call' instruction. The right instruction is "callq __main".
Patch by KS Sreeram!
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tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>
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ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.
There is a test case, but unfortunately it's sensitive to random code changes.
<rdar://problem/8782223>
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may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.
Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)
<rdar://problem/8782198>
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is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
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class A<bit a, bits<3> x, bits<3> y> {
bits<3> z;
let z = !if(a, x, y);
}
The variable z will get the value of x when 'a' is 1 and 'y' when a is '0'.
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particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
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may determine that they cannot be used uninitialized. But that might be a bit
too much for the compiler to determine.
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Bill Wendling