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195 Commits

Author SHA1 Message Date
Bob Wilson eb1641d54a Add LLVM support for Swift. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-29 21:43:49 +00:00
Anton Korobeynikov 6d655a50f9 fp16-to-fp32 conversion instructions are available in Thumb mode as well. 
Make sure the generic pattern is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162170 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-18 13:08:43 +00:00
Evan Cheng a99c508c8d Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows unaligned access. rdar://12091029 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-15 17:44:53 +00:00
Anton Korobeynikov 652199961a The names of VFP variants of half-to-float conversion instructions were 
reversed. This leads to wrong codegen for float-to-half conversion
intrinsics which are used to support storage-only fp16 type.
NEON variants of same instructions are fine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-14 23:36:01 +00:00
Richard Barton fae96f17b4 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-10 12:51:09 +00:00
Chad Rosier 270e3625b2 Revert r159938 (and r159945) to appease the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 20:43:34 +00:00
Richard Barton 2e7e34ba54 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-09 16:41:33 +00:00
Lang Hames dc13d2ed2f Add a missing llvm.fma -> VFNMS pattern to the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-21 06:10:00 +00:00
Lang Hames 7787800481 Fix the order of the operands in the llvm.fma intrinsic patterns for ARM, 
<rdar://problem/11325085>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-27 18:51:24 +00:00
Jim Grosbach c92ba4e905 Tidy up. 80 columns, whitespace, et. al. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155399 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-23 22:04:10 +00:00
Jim Grosbach 181b147975 ARM some VFP tblgen'erated two-operand aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-20 00:15:00 +00:00
Evan Cheng 14b4c03580 Add more fused mul+add/sub patterns. rdar://10139676 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154484 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 06:59:47 +00:00
Evan Cheng bee78fe5fc Clean up ARM fused multiply + add/sub support some more: rename some isel 
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 05:33:07 +00:00
Evan Cheng 92c904539a Match (fneg (fma) to vfnma. rdar://10139676 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154469 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 01:21:25 +00:00
Evan Cheng 3aef2ff514 Handle llvm.fma.* intrinsics. rdar://10914096 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154439 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-10 21:40:28 +00:00
Jim Grosbach 66cba302f0 ARM divided syntax fmrx/fmxr mnemonics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 21:06:13 +00:00
Jim Grosbach 9426ac7b57 ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 00:27:18 +00:00
Jim Grosbach b84ad4aa7d ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 21:34:14 +00:00
Jim Grosbach 6357caec78 ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. 
rdar://11056647

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 20:48:18 +00:00
Kristof Beyls 8a6bcc3722 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-15 17:50:29 +00:00
Lang Hames 4f92b5e616 Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-06 00:19:55 +00:00
Jim Grosbach bc978a60d9 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 23:16:31 +00:00
Sebastian Pop 74bebde7c4 updated patch for the ARM fused multiply add/sub 
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-05 17:39:52 +00:00
Jia Liu 31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Anton Korobeynikov 4b4e62219b Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 12:07:33 +00:00
Jim Grosbach 4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 22:19:05 +00:00
Jim Grosbach 8c748113eb Remove some bogus comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:45:01 +00:00
Jim Grosbach 1aa149f5ac ARM pre-UAL aliases. fcmp[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:20:45 +00:00
Jim Grosbach af33a0cfe0 ARM VFP optional data type on VMOV GPR<-->SPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:24:15 +00:00
Jim Grosbach 6849019079 ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:43:50 +00:00
Jim Grosbach 9c39789c36 ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:02:41 +00:00
Jim Grosbach 0f293de207 ARM NEON two-operand aliases for VQDMULH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:40:37 +00:00
Jim Grosbach f10154010e ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146508 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:13:48 +00:00
Jim Grosbach 485d8bf7e5 ARM add more 'gas' compatibility aliases for NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:08:32 +00:00
Jim Grosbach 48171e7fbe ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-10 00:01:02 +00:00
Jim Grosbach 21d7fb814a ARM add some pre-UAL VFP mnemonics for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 23:34:09 +00:00
Jim Grosbach 976c0da213 ARM convenience aliases for VSQRT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:51:25 +00:00
Jim Grosbach 8254f02231 ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:52:55 +00:00
Jim Grosbach 67ca1adf82 ARM VFP support 'flds/fldd' aliases for 'vldr' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:49:29 +00:00
Jim Grosbach 1ceef1a491 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:50:36 +00:00
Jim Grosbach 88d012a9c3 ARM VFP assembly parsing for VADD and VSUB two-operand forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 22:15:10 +00:00
Jim Grosbach eaf2056709 ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 21:18:35 +00:00
Jim Grosbach a68e90c36e ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:29:42 +00:00
Jim Grosbach bfb0a1717b ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-15 20:14:51 +00:00
Jim Grosbach ffc658b056 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 23:03:21 +00:00
Jim Grosbach 02e3d9268f ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-14 22:28:39 +00:00
Jim Grosbach c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Jim Grosbach 9d39036f62 ARM assembly parsing and encoding for VMOV immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:38:36 +00:00
Jim Grosbach 5cd5ac6ad4 ARM assembly parsing and encoding for VMRS/FMSTAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:12:43 +00:00
Jim Grosbach 4ebbf7b8a8 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 00:50:06 +00:00