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r237790 | dsanders | 2015-05-20 14:19:19 +0100 (Wed, 20 May 2015) | 15 lines
[mips] Fix ehframe-indirect.ll test.
Summary:
-check-prefix replaces the default CHECK prefix rather than adding to it and
must be explicitly re-added.
Also added the N32 cases.
Reviewers: petarj
Reviewed By: petarj
Subscribers: tberghammer, llvm-commits
Differential Revision: http://reviews.llvm.org/D9668
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Merged all except the N32 cases which seem to require later patches that
are fine on the trunk but don't seem to work on the branch.
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r238147 | thomas.stellard | 2015-05-25 12:15:54 -0400 (Mon, 25 May 2015) | 4 lines
R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
The src and dst register cannot be the same on chips with 16 lds banks.
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r237152 | thomas.stellard | 2015-05-12 13:13:02 -0400 (Tue, 12 May 2015) | 20 lines
R600/SI: add pass to mark CF live ranges as non-spillable
Spilling can insert instructions almost anywhere, and this can mess
up control flow lowering in a multitude of ways, due to instruction
reordering. Let's sort this out the easy way: never spill registers
involved with control flow, i.e. saved EXEC masks.
Unfortunately, this does not work at all with optimizations disabled,
as the register allocator ignores spill weights. This should be
addressed in a future commit.
The test was reduced from the "stacks" shader of [1]. Some issues
trigger the machine verifier while another one is checked manually.
[1] http://madebyevan.com/webgl-path-tracing/
v2: only insert pass with optimizations enabled, merge test runs.
Patch by: Grigori Goronzy
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r236457 | tnorthover | 2015-05-04 13:41:51 -0700 (Mon, 04 May 2015) |
9 lines
CodeGen: match up correct insertvalue indices when assessing tail
calls.
When deciding whether a value comes from the aggregate or inserted
value of an insertvalue instruction, we compare the indices against
those of the location we're interested in. One of the lists needs
reversing because the input data is backwards (so that modifications
take place at the end of the SmallVector), but we were reversing both
before leading to incorrect results.
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r236635 | tnorthover | 2015-05-06 13:07:38 -0700 (Wed, 06 May 2015) |
12 lines
CodeGen: move over-zealous assert into actual if statement.
It's quite possible to encounter an insertvalue instruction that's
more deeply nested than the value we're looking for, but when that
happens we really mustn't compare beyond the end of the index array.
Since I couldn't see any guarantees about what comparisons std::equal
makes, we probably need to directly check the size beforehand. In
practice, I suspect most std::equal implementations would probably
bail early, which would be OK. But just in case...
rdar://20834485
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It introduced two regressions (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) on 3 out of 23 cross-compilation
test-runs used by Mips for release validation.
The issue is that on 64-bit targets comparisons such as BEQ compare the whole
GPR64 but incorrectly tell the instruction selector that they operate on
GPR32's. This leads to the elimination of i32->i64 extensions that are actually
required by comparisons to work correctly.
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r229413 | atrick | 2015-02-16 13:10:47 -0500 (Mon, 16 Feb 2015) | 16 lines
AArch64: Safely handle the incoming sret call argument.
This adds a safe interface to the machine independent InputArg struct
for accessing the index of the original (IR-level) argument. When a
non-native return type is lowered, we generate the hidden
machine-level sret argument on-the-fly. Before this fix, we were
representing this argument as OrigArgIndex == 0, which is an outright
lie. In particular this crashed in the AArch64 backend where we
actually try to access the type of the original argument.
Now we use a sentinel value for machine arguments that have no
original argument index. AArch64, ARM, Mips, and PPC now check for this
case before accessing the original argument.
Fixes <rdar://19792160> Null pointer assertion in AArch64TargetLowering
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r236307 | thomas.stellard | 2015-04-30 23:44:09 -0400 (Thu, 30 Apr 2015) | 4 lines
R600/SI: Add VCC as an implict def of SI_KILL
When SI_KILL has a register operand, its lowered form writes to vcc.
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r236306 | thomas.stellard | 2015-04-30 23:44:08 -0400 (Thu, 30 Apr 2015) | 11 lines
R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass
This pass was generating 'Instruction does not dominate all uses!'
errors for programs which had loops with a condition variable that
depended on the result of a phi instruction from outside of the loop.
The pass was inserting new phi nodes outside of the loop which used values
defined inside the loop.
http://bugs.freedesktop.org/show_bug.cgi?id=90056
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r235641 | thomas.stellard | 2015-04-23 16:32:01 -0400 (Thu, 23 Apr 2015) | 9 lines
R600/SI: Fix indirect addressing with a negative constant offset
When the base register index of the vector plus the constant offset
was less than zero, we were passing the wrong base register to the indirect
addressing instruction.
In this case, we need to set the base register to v0 and then add
the computed (negative) index to m0.
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r227519 | reid | 2015-01-29 18:58:04 -0500 (Thu, 29 Jan 2015) | 10 lines
x86: Fix large model calls to __chkstk for dynamic allocas
In the large code model, we now put __chkstk in %r11 before calling it.
Refactor the code so that we only do this once. Simplify things by using
__chkstk_ms instead of __chkstk on cygming. We already use that symbol
in the prolog emission, and it simplifies our logic.
Second half of PR18582.
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r227503 | reid | 2015-01-29 17:33:00 -0500 (Thu, 29 Jan 2015) | 11 lines
Update comments to use unreachable instead of llvm.trap, as implemented now
win64: Call __chkstk through a register with the large code model
Fixes half of PR18582. True dynamic allocas will still have a
CALL64pcrel32 which will fail.
Reviewers: majnemer
Differential Revision: http://reviews.llvm.org/D7267
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CodeGen incorrectly ignores (assert from APInt) constant index bigger
than 2^64 in getelementptr instruction. This is a test and fix for that.
Patch by Paweł Bylica!
Reviewed By: rnk
Subscribers: majnemer, rnk, mcrosier, resistor, llvm-commits
Differential Revision: http://reviews.llvm.org/D8219
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r234891 | thomas.stellard | 2015-04-14 10:36:45 -0400 (Tue, 14 Apr 2015) | 12 lines
R600/SI: Fix verifier error caused by SIAnnotateControlFlow
This pass will always try to insert llvm.SI.ifbreak intrinsics
in the same block that its conditional value is computed in. This is
a problem when conditions for breaks or continue are computed outside
of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted
outside of the loop.
This patch fixes this problem by inserting the llvm.SI.ifbreak
intrinsics in the loop header when the condition is computed outside
the loop.
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r233075 | marek.olsak | 2015-03-24 09:40:08 -0400 (Tue, 24 Mar 2015) | 8 lines
R600/SI: Expand fract to floor, then only select V_FRACT on CI
V_FRACT is buggy on SI.
R600-specific code is left intact.
v2: drop the multiclass, use complex VOP3 patterns
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r232957 | thomas.stellard | 2015-03-23 12:06:01 -0400 (Mon, 23 Mar 2015) | 5 lines
R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()
This function assumed that SMRD instructions always have immediate
offsets, which is not always the case.
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r233410 | ahmed.bougacha | 2015-03-27 16:35:49 -0400 (Fri, 27 Mar 2015) | 10 lines
[CodeGen] Don't attempt a tail-call with a non-forwarded explicit sret.
Tailcalls are only OK with forwarded sret pointers. With explicit sret,
one approximation is to check that the pointer isn't an Instruction, as
in that case it might point into some local memory (alloca). That's not
OK with tailcalls.
Explicit sret counterpart to r233409.
Differential Revison: http://reviews.llvm.org/D8510
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r233409 | ahmed.bougacha | 2015-03-27 16:28:30 -0400 (Fri, 27 Mar 2015) | 7 lines
[CodeGen] Don't attempt a tail-call with implicit sret.
Tailcalls are only OK with forwarded sret pointers. With sret demotion,
they're not, as we'd have a pointer into a soon-to-be-dead stack frame.
Differential Revison: http://reviews.llvm.org/D8510
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r232386 | thomas.stellard | 2015-03-16 11:53:55 -0400 (Mon, 16 Mar 2015) | 8 lines
R600/SI: don't try min3/max3/med3 with f64
There are no opcodes for this. This also adds a test case.
v2: make test more robust
Patch by: Grigori Goronzy
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r231659 | marek.olsak | 2015-03-09 11:48:09 -0400 (Mon, 09 Mar 2015) | 4 lines
R600/SI: Limit SGPRs to 80 on Tonga and Iceland
This is a candidate for stable.
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r232943 | petarj | 2015-03-23 12:28:13 +0000 (Mon, 23 Mar 2015) | 10 lines
Fix sign extension for MIPS64 in makeLibCall function
Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all
32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign
extended. This fixes test "MultiSource/Applications/oggenc/".
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D7791
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r228765 | petarj | 2015-02-10 23:30:14 +0000 (Tue, 10 Feb 2015) | 12 lines
Fix makeLibCall argument (signed) in SoftenFloatRes_XINT_TO_FP function
The isSigned argument of makeLibCall function was hard-coded to false
(unsigned). This caused zero extension on MIPS64 soft float.
As the result SingleSource/Benchmarks/Stanford/FloatMM test and
SingleSource/UnitTests/2005-07-17-INT-To-FP test failed.
The solution was to use the proper argument.
Patch by Strahinja Petrovic.
Differential Revision: http://reviews.llvm.org/D7292
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r230956 | vkalintiris | 2015-03-02 12:47:32 +0000 (Mon, 02 Mar 2015) | 10 lines
[mips] Optimize conditional moves where RHS is zero.
Summary:
When the RHS of a conditional move node is zero, we can utilize the $zero
register by inverting the conditional move instruction and by swapping the
order of its True/False operands.
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D7945
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r230500 | vmedic | 2015-02-25 15:24:37 +0000 (Wed, 25 Feb 2015) | 1 line
[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.
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r232382 | petarj | 2015-03-16 15:01:09 +0000 (Mon, 16 Mar 2015) | 13 lines
[MIPS] Fix justify error for small structures
Fix justify error for small structures bigger than 32 bits in fixed
arguments for MIPS64 big endian. There was a problem when small structures
are passed as fixed arguments. The structures that are bigger than 32 bits
but smaller than 64 bits were not left justified properly on MIPS64 big
endian. This is fixed by shifting the value to make it left justified when
appropriate.
Patch by Aleksandar Beserminji.
Differential Revision: http://reviews.llvm.org/D8174
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r230742 | vkalintiris | 2015-02-27 09:01:39 +0000 (Fri, 27 Feb 2015) | 12 lines
[mips] Account for constant-zero operands in ADDE nodes.
Summary:
We identify the cases where the operand to an ADDE node is a constant
zero. In such cases, we can avoid generating an extra ADDu instruction
disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r).
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7906
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r230657 | petarj | 2015-02-26 18:35:15 +0000 (Thu, 26 Feb 2015) | 13 lines
Fix justify error for small structures in varargs for MIPS64BE
There was a problem when passing structures as variable arguments.
The structures smaller than 64 bit were not left justified on MIPS64
big endian. This is now fixed by shifting the value to make it left-
justified when appropriate.
This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608
Patch by Aleksandar Beserminji.
Differential Revision: http://reviews.llvm.org/D7881
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r230235 | dsanders | 2015-02-23 17:22:16 +0000 (Mon, 23 Feb 2015) | 16 lines
[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.
Summary:
-mno-odd-spreg prohibits the use of odd-numbered single-precision floating
point registers. However, vector insert/extract was still using them when
manipulating the subregisters of an MSA register. Fixed this by ensuring
that insertion/extraction is only performed on even-numbered vector
registers when -mno-odd-spreg is given.
Reviewers: vmedic, sstankovic
Reviewed By: sstankovic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7672
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r229236 | Matthew.Arsenault | 2015-02-13 23:22:00 -0500 (Fri, 13 Feb 2015) | 7 lines
R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation.
Test is disabled for VI since there seems to be a problem with one
of the buffer load instructions on it.
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r228374 | michel.daenzer | 2015-02-05 21:51:29 -0500 (Thu, 05 Feb 2015) | 4 lines
R600/SI: Amend a test to ensure WQM is enabled for LDS in pixel shaders
Reviewed-by: Tom Stellard <tom@stellard.net>
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r228372 | michel.daenzer | 2015-02-05 21:51:20 -0500 (Thu, 05 Feb 2015) | 12 lines
R600/SI: Also enable WQM for image opcodes which calculate LOD v3
If whole quad mode isn't enabled for these, the level of detail is
calculated incorrectly for pixels along diagonal triangle edges, causing
artifacts.
v2: Use a TSFlag instead of lots of switch cases
v3: Add test coverage
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
Reviewed-by: Tom Stellard <tom@stellard.net>
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r228189 | thomas.stellard | 2015-02-04 15:49:51 -0500 (Wed, 04 Feb 2015) | 9 lines
R600/SI: Make more store operations legal
v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for
all address spaces. We had marked them as custom in order to lower
them for the private address space, but this is no longer necessary.
This enables lowering of misaligned stores of these types in the
DAGLegalizer.
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r228188 | thomas.stellard | 2015-02-04 15:49:49 -0500 (Wed, 04 Feb 2015) | 5 lines
R600: Don't promote i64 stores to v2i32 during DAG legalization
We take care of this during instruction selection now. This
fixes a potential infinite loop when lowering misaligned stores.
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Daniel Sanders
Tom Stellard
Tim Northover
Pawel Bylica