Commit Graph

95182 Commits

Author SHA1 Message Date
Reed Kotler
0323d4b169 Add an option which permits the user to specify using a bitmask, that various
functions be compiled as mips32, without having to add attributes. This
is useful in certain situations where you don't want to have to edit the
function attributes in the source. For now it's only an option used for
the compiler developers when debugging the mips16 port.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 20:53:09 +00:00
Akira Hatanaka
93877b3cbc [mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 20:46:51 +00:00
Jim Grosbach
8b262e5ab8 ARM: Fix fast-isel copy/paste-o.
Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.

rdar://14779513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 19:12:42 +00:00
Andrew Kaylor
11873fc85a Still more MCJIT PIC test XFAILs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 18:13:48 +00:00
Andrew Kaylor
17b06b899e Clarifying two MCJIT PIC tests as XFAIL on i686-pc-linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 17:01:35 +00:00
Andrew Kaylor
c90825d1ae Removing duplicate XFAIL markers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 16:42:22 +00:00
Andrew Kaylor
58a81a1c62 Marking two more MCJIT PIC tests as XFAIL on i686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 15:47:04 +00:00
Andrew Kaylor
2d219d67d2 Marking MCJIT PIC tests as XFAIL on arm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 15:36:04 +00:00
Vladimir Medic
7b0a79601b Fix style issues in AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 13:33:18 +00:00
Elena Demikhovsky
38cd21a3e9 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 11:00:29 +00:00
Daniel Sanders
c5158b869b [mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:41:47 +00:00
Richard Sandiford
0371d01fb9 [SystemZ] Update README
We now use MVST, CLST and SRST for the obvious cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:40:35 +00:00
Richard Sandiford
8c20158fb0 [SystemZ] Use SRST to optimize memchr
SystemZTargetLowering::emitStringWrapper() previously loaded the character
into R0 before the loop and made R0 live on entry.  I'd forgotten that
allocatable registers weren't allowed to be live across blocks at this stage,
and it confused LiveVariables enough to cause a miscompilation of f3 in
memchr-02.ll.

This patch instead loads R0 in the loop and leaves LICM to hoist it
after RA.  This is actually what I'd tried originally, but I went for
the manual optimisation after noticing that R0 often wasn't being hoisted.
This bug forced me to go back and look at why, now fixed as r188774.

We should also try to optimize null checks so that they test the CC result
of the SRST directly.  The select between null and the SRST GPR result could
then usually be deleted as dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:38:48 +00:00
Benjamin Kramer
74e81aae7c memcmp is not a valid way to compare structs with padding in them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:27:31 +00:00
Daniel Sanders
6ef333501e [mips][msa] Added insve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:22:54 +00:00
Richard Sandiford
7a4dd51e12 Fix test typo and add usual "br %r14" test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:14:46 +00:00
Richard Sandiford
9608ed1311 Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs.  When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too.  E.g. the final candidate loop just has:

    unsigned Def = Candidates[i].Def;
    if (!PhysRegClobbers.test(Def) && ...) {

to test whether register Def is multiply defined.

However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1.  If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).

This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:11:13 +00:00
Tim Northover
32c2bfda77 ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:57:11 +00:00
Michael Gottesman
ade3075030 [stackprotector] Small cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:56:28 +00:00
Michael Gottesman
d4f478899e [stackprotector] Small Bit of computation hoisting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:56:26 +00:00
Michael Gottesman
b99272a521 [stackprotector] Added significantly longer comment to FindPotentialTailCall to make clear its relationship to llvm::isInTailCallPosition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:56:23 +00:00
Michael Gottesman
c02dbeb429 Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:46:16 +00:00
Michael Gottesman
47d6e07a9b [stackprotector] Removed stale TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188768 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:46:13 +00:00
Daniel Sanders
c149fbbe27 [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:38:21 +00:00
Michael Gottesman
3480d1b84e [stackprotector] Added support for emitting the llvm intrinsic stack protector check.
rdar://13935163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:36:53 +00:00
Michael Gottesman
9d6852cf98 [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall.
This allows me to use returnTypeIsEligibleForTailCall in the stack protector pass.

rdar://13935163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188765 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 08:36:50 +00:00
Michael Gottesman
1a6de17273 Remove unused variables that crept in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 07:17:27 +00:00
Michael Gottesman
657484f494 Teach selectiondag how to handle the stackprotectorcheck intrinsic.
Previously, generation of stack protectors was done exclusively in the
pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
splitting basic blocks at the IR level to create the success/failure basic
blocks in the tail of the basic block in question. As a result of this,
calls that would have qualified for the sibling call optimization were no
longer eligible for optimization since said calls were no longer right in
the "tail position" (i.e. the immediate predecessor of a ReturnInst
instruction).

Then it was noticed that since the sibling call optimization causes the
callee to reuse the caller's stack, if we could delay the generation of
the stack protector check until later in CodeGen after the sibling call
decision was made, we get both the tail call optimization and the stack
protector check!

A few goals in solving this problem were:

  1. Preserve the architecture independence of stack protector generation.

  2. Preserve the normal IR level stack protector check for platforms like
     OpenBSD for which we support platform specific stack protector
     generation.

The main problem that guided the present solution is that one can not
solve this problem in an architecture independent manner at the IR level
only. This is because:

  1. The decision on whether or not to perform a sibling call on certain
     platforms (for instance i386) requires lower level information
     related to available registers that can not be known at the IR level.

  2. Even if the previous point were not true, the decision on whether to
     perform a tail call is done in LowerCallTo in SelectionDAG which
     occurs after the Stack Protector Pass. As a result, one would need to
     put the relevant callinst into the stack protector check success
     basic block (where the return inst is placed) and then move it back
     later at SelectionDAG/MI time before the stack protector check if the
     tail call optimization failed. The MI level option was nixed
     immediately since it would require platform specific pattern
     matching. The SelectionDAG level option was nixed because
     SelectionDAG only processes one IR level basic block at a time
     implying one could not create a DAG Combine to move the callinst.

To get around this problem a few things were realized:

  1. While one can not handle multiple IR level basic blocks at the
     SelectionDAG Level, one can generate multiple machine basic blocks
     for one IR level basic block. This is how we handle bit tests and
     switches.

  2. At the MI level, tail calls are represented via a special return
     MIInst called "tcreturn". Thus if we know the basic block in which we
     wish to insert the stack protector check, we get the correct behavior
     by always inserting the stack protector check right before the return
     statement. This is a "magical transformation" since no matter where
     the stack protector check intrinsic is, we always insert the stack
     protector check code at the end of the BB.

Given the aforementioned constraints, the following solution was devised:

  1. On platforms that do not support SelectionDAG stack protector check
     generation, allow for the normal IR level stack protector check
     generation to continue.

  2. On platforms that do support SelectionDAG stack protector check
     generation:

    a. Use the IR level stack protector pass to decide if a stack
       protector is required/which BB we insert the stack protector check
       in by reusing the logic already therein. If we wish to generate a
       stack protector check in a basic block, we place a special IR
       intrinsic called llvm.stackprotectorcheck right before the BB's
       returninst or if there is a callinst that could potentially be
       sibling call optimized, before the call inst.

    b. Then when a BB with said intrinsic is processed, we codegen the BB
       normally via SelectBasicBlock. In said process, when we visit the
       stack protector check, we do not actually emit anything into the
       BB. Instead, we just initialize the stack protector descriptor
       class (which involves stashing information/creating the success
       mbbb and the failure mbb if we have not created one for this
       function yet) and export the guard variable that we are going to
       compare.

    c. After we finish selecting the basic block, in FinishBasicBlock if
       the StackProtectorDescriptor attached to the SelectionDAGBuilder is
       initialized, we first find a splice point in the parent basic block
       before the terminator and then splice the terminator of said basic
       block into the success basic block. Then we code-gen a new tail for
       the parent basic block consisting of the two loads, the comparison,
       and finally two branches to the success/failure basic blocks. We
       conclude by code-gening the failure basic block if we have not
       code-gened it already (all stack protector checks we generate in
       the same function, use the same failure basic block).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 07:00:16 +00:00
Craig Topper
1299e49ba7 Fix formatting. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 05:23:59 +00:00
Craig Topper
3b7722cf3a Add AVX-512 and related features to the CPUID detection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 05:22:42 +00:00
Craig Topper
b5e1d5b46f Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 04:24:14 +00:00
Craig Topper
5cc16a9d89 Add an error check for a typo I accidentally made in a td file that caused an assert to fire.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 04:22:09 +00:00
Bill Schmidt
6af35e9576 [PowerPC] More refactoring prior to real PPC emitPrologue/Epilogue changes.
(Patch committed on behalf of Mark Minich, whose log entry follows.)

This is a continuation of the refactorings performed in svn rev 188573
(see that rev's comments for more detail).

This is my stage 2 refactoring: I combined the emitPrologue() &
emitEpilogue() PPC32 & PPC64 code into a single flow, simplifying a
lot of the code since in essence the PPC32 & PPC64 code generation
logic is the same, only the instruction forms are different (in most
cases). This simplification is necessary because my functional changes
(yet to come) add significant complexity, and without the
simplification of my stage 2 refactoring, the overall complexity of
both emitPrologue() & emitEpilogue() would have become almost
intractable for most mortal programmers (like me).

This submission was intended to be a pure refactoring (no functional
changes whatsoever). However, in the process of combining the PPC32 &
PPC64 flows, I spotted a difference that I believe is a bug (see svn
rev 186478 line 863, or svn rev 188573 line 888): This line appears to
be restoring the BP with the original FP content, not the original BP
content. When I merged the 32-bit and 64-bit code, I used the
corresponding code from the 64-bit flow, which I believe uses the
correct offset (BPOffset) for this operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188741 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 03:12:23 +00:00
Andrew Kaylor
fbeb4a2520 Marking MCJIT PIC tests as XFAIL on AArch64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188740 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 01:50:50 +00:00
Venkatraman Govindaraju
e3b29fbc5f [Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188738 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 01:26:14 +00:00
Andrew Kaylor
ec28c7d8ec Fixing XPASSes among MCJIT PIC test on i686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 00:37:33 +00:00
Andrew Kaylor
43bdcdcad5 Second attempt to mark Large/PIC MCJIT test as XFAIL for PowerPC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 00:22:03 +00:00
Andrew Kaylor
93c25ccdff Marking two MCJIT PIC tests as XFAIL on Darwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 00:14:50 +00:00
Andrew Kaylor
d464018e7a Trying again with PIC tests for MCJIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188730 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 23:52:53 +00:00
Hal Finkel
66d1fa6f4b Add a llvm.copysign intrinsic
This adds a llvm.copysign intrinsic; We already have Libfunc recognition for
copysign (which is turned into the FCOPYSIGN SDAG node). In order to
autovectorize calls to copysign in the loop vectorizer, we need a corresponding
intrinsic as well.

In addition to the expected changes to the language reference, the loop
vectorizer, BasicTTI, and the SDAG builder (the intrinsic is transformed into
an FCOPYSIGN node, just like the function call), this also adds FCOPYSIGN to a
few lists in LegalizeVector{Ops,Types} so that vector copysigns can be
expanded.

In TargetLoweringBase::initActions, I've made the default action for FCOPYSIGN
be Expand for vector types. This seems correct for all in-tree targets, and I
think is the right thing to do because, previously, there was no way to generate
vector-values FCOPYSIGN nodes (and most targets don't specify an action for
vector-typed FCOPYSIGN).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188728 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 23:35:46 +00:00
Hal Finkel
30cbccb029 Don't form PPC CTR-based loops around a copysignl call
copysign/copysignf never become function calls (because the SDAG expansion code
does not lower to the corresponding function call, but rather directly
implements the associated logic), but copysignl almost always is lowered into a
call to the requested libm functon (and, thus, might clobber CTR).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188727 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 23:35:24 +00:00
Andrew Kaylor
ff9fa05905 Adding PIC support for ELF on x86_64 platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188726 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 23:27:43 +00:00
Peter Collingbourne
abd37961d5 Introduce non-const overloads for GlobalAlias::{get,resolve}AliasedGlobal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 23:13:33 +00:00
Jakub Staszak
c2d722efbf Use pop_back_val() instead of both back() and pop_back().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188723 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 22:47:55 +00:00
Matt Arsenault
8e3367ea36 Teach InstCombine visitGetElementPtr about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 22:17:40 +00:00
Matt Arsenault
c4ad982f0b Cleanup visitGetElementPtr to make address space change easier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188720 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 22:17:34 +00:00
Matt Arsenault
5c40cc2e1e commonPointerCast cleanups to make address space change easier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 22:17:18 +00:00
Jakub Staszak
b937c55e93 Make sure that pop_back_val() result is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188717 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 22:12:00 +00:00
Andrew Kaylor
aa22a4b002 Reverting r188709 until I can figure out the proper way to XFAIL it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 22:05:07 +00:00
Matt Arsenault
c4d070ad07 Fix assert with GEP ptr vector indexing structs
Also fix it calculating the wrong value. The struct index
is not a ConstantInt, so it was being interpreted as an array
index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-19 21:43:16 +00:00