Chad Rosier
1c8fccbc12
[arm-fast-isel] Add support for non-global callee.
...
Patch by Jush Lu <jush.msn@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23 18:38:57 +00:00
Chad Rosier
226ddf5278
[fast-isel] Add support for selecting @llvm.trap().
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 21:33:49 +00:00
Chad Rosier
2b3b335f2d
[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:40:25 +00:00
Chad Rosier
2a2e9d54e9
[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
...
retval. Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 18:51:55 +00:00
Chad Rosier
2f6ae41f14
[fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
...
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 17:41:06 +00:00
Chad Rosier
f4bd21c256
The return type is an unsigned, not a bool.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 16:41:38 +00:00
Craig Topper
420761a0f1
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 07:30:17 +00:00
Jim Grosbach
d4f020a3af
Tidy up. 80 columns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06 23:43:50 +00:00
Jakob Stoklund Olesen
f16936e592
Deduplicate ARM call-related instructions.
...
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154144 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06 00:04:58 +00:00
Craig Topper
c89c744b69
Remove unnecessary llvm:: qualifications
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:21:54 +00:00
Craig Topper
0e5233a9e5
Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26 00:45:15 +00:00
Bill Wendling
5aeff3171c
Check if we can handle the arguments of a call (and therefore the call) in
...
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 23:11:07 +00:00
Chad Rosier
0ac754f6f4
[fast-isel] Address Eli's comments for r152847. Specifically, add a test case
...
and still allow immediate encoding, just not with cmn.
rdar://11038907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 22:54:20 +00:00
Chad Rosier
530b19b702
[fast-isel] Don't try to encode LONG_MIN using cmn instructions.
...
rdar://11038907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 21:40:23 +00:00
Chad Rosier
44c98b7114
[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point
...
condition flags to CPSR. This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 20:59:26 +00:00
Lang Hames
4f92b5e616
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
...
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 00:19:55 +00:00
Jim Grosbach
e751c0069a
ARM use the right opcode for FP<->Integer move in fast-isel.
...
rdar://10965031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 22:47:09 +00:00
Jakob Stoklund Olesen
c54f634886
Switch ARM target to register masks.
...
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.
This patch does cause some assembly changes. Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected. MachineCopyPropagation may sometimes
leave a dead copy behind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 01:19:29 +00:00
Craig Topper
44d23825d6
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 05:59:10 +00:00
Chad Rosier
b8703fe265
[fast-isel] Add support for returning non-legal types with no sign- or zero-
...
entend flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 01:21:28 +00:00
Chad Rosier
a69feb0f33
Remove unnecessary assignment to temporary, ResultReg.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 22:45:33 +00:00
Chad Rosier
40d552e0be
Add braces to if clause to make symmetric with associate else clause.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 17:36:21 +00:00
Chad Rosier
92fd017364
Use a temporary variable, rather then a series of redundant calls.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 00:23:55 +00:00
Chad Rosier
5793a6586d
Remove unnecessary assignment to temporary, ResultReg.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14 22:29:48 +00:00
Chad Rosier
743e19983e
[fast-isel] Add support for SUBs with non-legal types.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 02:45:44 +00:00
Chad Rosier
6fde875621
[fast-isel] Add support for ORs with non-legal types.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 02:29:21 +00:00
Chad Rosier
60c8fa6bb9
[fast-isel] Add support for indirect branches.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 23:56:08 +00:00
Craig Topper
bc2198133a
Convert assert(0) to llvm_unreachable
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 02:50:20 +00:00
Chad Rosier
3901c3e750
[fast-isel] Add support for ADDs with non-legal types.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 23:50:07 +00:00
Duncan Sands
5b8a1db7ea
Persuade GCC that there is nothing worth warning about here (there isn't).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 14:20:11 +00:00
Chad Rosier
769422f0fc
[fast-isel] Add support for URem.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149716 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:23:45 +00:00
Chad Rosier
ae46a3362d
[fast-isel] Rename isZExt to isSigned. No functional change intended.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:14:11 +00:00
Chad Rosier
7ccb30b596
[fast-isel] Add support for UDIV.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:07:27 +00:00
Chad Rosier
ee8901c08f
[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 20:27:51 +00:00
Chad Rosier
36b7beb429
[fast-isel] Add support for selecting UIToFP.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 19:42:52 +00:00
David Blaikie
4d6ccb5f68
More dead code removal (using -Wunreachable-code)
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
Eric Christopher
fae699a580
Fix assert.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147966 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 20:55:27 +00:00
Jakob Stoklund Olesen
8f37a2422e
Match SelectionDAG logic for enabling movt.
...
Darwin doesn't do static, and ELF targets only support static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 20:49:15 +00:00
Jakob Stoklund Olesen
4964ba01f9
Use getRegForValue() to materialize the address of ARM globals.
...
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.
<rdar://problem/10658692>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 04:07:22 +00:00
Jakob Stoklund Olesen
45ca7c6336
Use movw+movt in ARMFastISel::ARMMaterializeGV.
...
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.
This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.
<rdar://problem/10629774>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 01:47:05 +00:00
Evan Cheng
afff941211
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 18:26:50 +00:00
Chad Rosier
6762f8f302
VFP2 is required for FP loads. Noticed by inspection.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:55:03 +00:00
Chad Rosier
64ac91b4b6
Tidy up.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:32:02 +00:00
Chad Rosier
404ed3c223
Fix 80-column violation and extraneous brackets.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:26:05 +00:00
Evan Cheng
ddfd1377d2
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:11:42 +00:00
Chad Rosier
8a9bce978f
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 19:22:14 +00:00
Evan Cheng
5a96b3dad2
Add bundle aware API for querying instruction properties and switch the code
...
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Chad Rosier
ed42c5f778
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:44:17 +00:00
Bob Wilson
6ce2deacef
Fix 80-column issues.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-04 00:52:23 +00:00
Chad Rosier
9eff1e33f6
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 02:21:57 +00:00