Craig Topper
09a326d3f0
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 04:36:03 +00:00
Craig Topper
1fe132ae7d
Merge an AVX/SSE 256-bit and 128-bit multiclass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 03:56:47 +00:00
Craig Topper
b5c590a586
Mark VANDNPD/VANDNPDS as not commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 03:48:10 +00:00
Craig Topper
174a3d3e63
Remove alignment from a bunch more VEX encoded operations in the folding tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 02:44:47 +00:00
Craig Topper
d83a73adf0
Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 02:14:19 +00:00
Craig Topper
1ac0046fa8
Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 01:47:12 +00:00
Craig Topper
0f77910e6f
Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 00:35:47 +00:00
Hal Finkel
cd9ea51986
Expand PPC64 atomic load and store
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Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 17:22:53 +00:00
Benjamin Kramer
99f78061e0
X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 13:09:08 +00:00
Benjamin Kramer
382ed78d3f
X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.
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pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 12:54:19 +00:00
Nadav Rotem
a4c8a32a9f
VCVTSS2SD requires a strict alignment. Thanks Elena.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 03:29:18 +00:00
Nick Lewycky
71f30bffcf
Quiet gcc's -Wparenthesis warning. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 19:58:45 +00:00
Benjamin Kramer
791dbb3e5f
Use a std::string rather than a dynamically allocated char* buffer.
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This affords us to use std::string's allocation routines and use the destructor
for the memory management. Switching to that also means that we can use
operator==(const std::string&, const char *) to perform the string comparison
rather than resorting to libc functionality (i.e. strcmp).
Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 19:23:30 +00:00
Nadav Rotem
1e1c5f37c3
CostModel: We have API for checking the costs of known shuffles. This patch adds
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support for the insert-subvector and extract-subvector kinds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 10:04:03 +00:00
Nadav Rotem
ace0c2fad7
Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned.
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When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding
tables and removes the alignment restrictions from VEX-encoded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 09:40:33 +00:00
Nadav Rotem
daf7b5c8f2
Change the codegen Cost Model API for shuffeles. This patch removes the API for broadcast and adds a more general API that accepts an enum of known shuffles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171022 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 08:57:47 +00:00
Nadav Rotem
6f3d81a929
CostModel: Change the default target-independent implementation for finding
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the cost of arithmetic functions. We now assume that the cost of arithmetic
operations that are marked as Legal or Promote is low, but ops that are
marked as custom are higher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 17:31:23 +00:00
Nadav Rotem
40b04a481d
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 07:33:44 +00:00
Nadav Rotem
677689cf5d
Rename a function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 07:30:09 +00:00
Nadav Rotem
d54fed2786
Loop Vectorizer: Update the cost model of scatter/gather operations and make
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them more expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 07:23:55 +00:00
Benjamin Kramer
2f8a6cdfa3
X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.
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pmuludq is slow, but it turns out that all the unpacking and packing of the
scalarized mul is even slower. 10% speedup on loop-vectorized paq8p.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22 16:07:56 +00:00
Benjamin Kramer
17347912b4
X86: Emit vector sext as shuffle + sra if vpmovsx is not available.
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Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better
than scalarized loads. Fixes PR14590.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22 11:34:28 +00:00
Nadav Rotem
d0696ef8c3
In some cases, due to scheduling constraints we copy the EFLAGS.
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The only way to read the eflags is using push and pop. If we don't
adjust the stack then we run over the first frame index. This is
not something that we want to do, so we have to make sure that
our machine function does not copy the flags. If it does then
we have to emit the prolog that adjusts the stack.
rdar://12896831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:48:49 +00:00
Akira Hatanaka
dbf51ee459
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:21:32 +00:00
Akira Hatanaka
e8bc10b902
[mips] Refactor SYNC and multiply/divide instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:17:36 +00:00
Akira Hatanaka
aa7c9cd181
[mips] Refactor BAL instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:15:59 +00:00
Akira Hatanaka
1892253694
[mips] Fix encoding of BAL instruction. Also, fix assembler test case which
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was not catching the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:13:59 +00:00
Akira Hatanaka
6a8309e62a
[mips] Refactor jump, jump register, jump-and-link and nop instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:03:50 +00:00
Akira Hatanaka
0a57dc1d14
[mips] Refactor load/store left/right and load-link and store-conditional
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:01:24 +00:00
Akira Hatanaka
16164657d8
[mips] Refactor load/store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:58:55 +00:00
Akira Hatanaka
5f5770baae
[mips] Remove unnecessary isPseudo parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:57:26 +00:00
Akira Hatanaka
8e719fac46
[mips] Refactor LUI instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:46:07 +00:00
Akira Hatanaka
35242e27c5
[mips] Refactor count leading zero or one instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:43:58 +00:00
Akira Hatanaka
8aaed99a99
[mips] Refactor sign-extension-in-register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:41:52 +00:00
Akira Hatanaka
7de001b97e
[mips] Refactor instructions which copy from and to HI/LO registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:39:17 +00:00
Akira Hatanaka
2a732ec272
[mips] Refactor logical NOR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:35:47 +00:00
Akira Hatanaka
a8215f4ec2
[mips] Move instruction definitions in MipsInstrInfo.td.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:33:43 +00:00
Tom Stellard
b06c540f9f
R600: Coding style - remove empty spaces from the beginning of functions
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170923 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 20:12:02 +00:00
Tom Stellard
eef0d5a0d6
R600: Fix MAX_UINT definition
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Patch by: Vadim Girlin
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 20:12:01 +00:00
Tom Stellard
fe13e70f6f
R600: Add SHADOWCUBE to TEX_SHADOW pattern
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Patch by: Vadim Girlin
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170921 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 20:11:59 +00:00
Benjamin Kramer
4e23ebe766
Cleanup compiler warnings on discarding type qualifiers in casts. Switch to C++ style casts.
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Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 19:09:53 +00:00
Benjamin Kramer
2556c6b4b6
X86: Match pmin/pmax as a target specific dag combine. This occurs during vectorization.
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Part of PR14667.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 17:46:58 +00:00
Roman Divacky
38b06020db
Remove duplicate includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 17:06:44 +00:00
Tom Stellard
519b456fe1
R600: Expand vec4 INT <-> FP conversions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170901 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 16:33:24 +00:00
Benjamin Kramer
739c7a83e1
X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics
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This is very mechanical, no functionality change. Preparation for PR14667.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 14:04:55 +00:00
Nadav Rotem
042a9a2666
Add a missing "virtual" keyword.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 05:02:12 +00:00
Quentin Colombet
e0f1d712f6
Add ARM cortex-r5 subtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 04:35:05 +00:00
Nadav Rotem
f5637c3997
Improve the X86 cost model for loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 01:33:59 +00:00
Nadav Rotem
c2a537bd08
BB-Vectorizer: Check the cost of the store pointer type
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and not the return type, which is void. A number of test
cases fail after adding the assertion in TTImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170828 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 01:24:36 +00:00
Reed Kotler
a40ba2b3b2
Call llvm_unreachable instead of assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170822 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 00:44:59 +00:00