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16 Commits

Author SHA1 Message Date
Evan Cheng
ba647becb9 Specify S registers as D registers' sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 21:20:10 +00:00
Evan Cheng
bf822eb6a3 Change register allocation order to Dale's suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35021 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-08 02:56:40 +00:00
Evan Cheng
cb20998b3f ARM always use register scavenger. No longer reserves R12. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34999 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-07 02:46:23 +00:00
Evan Cheng
36230cdda4 Make requiresRegisterScavenging determination on a per MachineFunction basis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:59:19 +00:00
Evan Cheng
41a4d562f7 Temporary: make R12 available in ARM mode if RegScavenger is being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34709 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-28 00:22:44 +00:00
Evan Cheng
15991bf775 Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be livein to a function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34701 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-02-27 23:03:55 +00:00
Evan Cheng
24f7fb3267 Comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33633 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-29 22:23:02 +00:00
Evan Cheng
dc77540d95 hasFP() is now a virtual method of MRegisterInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-23 00:57:47 +00:00
Evan Cheng
75e18c403e Clean up ARM PEI code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33389 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-20 02:09:25 +00:00
Evan Cheng
a8e2989ece ARM backend contribution from Apple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-01-19 07:51:42 +00:00
Rafael Espindola
7ae68ab3bc initial support for frame pointers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31197 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-26 13:31:26 +00:00
Rafael Espindola
9e071f0ae3 fix the names of the 64bit fp register 
initial support for returning 64bit floating point numbers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-02 19:30:56 +00:00
Rafael Espindola
27185190e6 add floating point registers 
implement SINT_TO_FP


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-29 21:20:16 +00:00
Chris Lattner
5ea64fd9eb Constify some methods. Patch provided by Anton Vayvod, thanks! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-08-17 22:00:08 +00:00
Rafael Espindola
58421d7d08 initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-18 00:08:07 +00:00
Rafael Espindola
7bc59bc395 added a skeleton of the ARM backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-14 22:18:28 +00:00