Commit Graph

12475 Commits

Author SHA1 Message Date
Cameron Zwarich
0a00615b34 Add a test for i1 zeroext arguments on x86-64. We currently generate code that
conforms to the ABI, but DAGCombine could in theory recognize the sequence of
zext asserts and truncates and generate incorrect code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 20:15:44 +00:00
Richard Osborne
bb057453db Add checkevent intrinsic to check if any resources owned by the current thread
can event.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 18:34:00 +00:00
NAKAMURA Takumi
bfc4c983a6 test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and x86_64-win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:53:07 +00:00
NAKAMURA Takumi
37947c6bad test/CodeGen/X86: Add a pattern for Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:51 +00:00
NAKAMURA Takumi
ddbfbcf72e test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They are useless to Win64 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:38 +00:00
NAKAMURA Takumi
4491aa49b3 test/CodeGen/X86/byval*.ll: Win64 has not supported byval yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:20 +00:00
NAKAMURA Takumi
67bf77e8fd test/CodeGen/X86/dyn-stackalloc.ll: FileCheck-ize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:08 +00:00
Cameron Zwarich
85b0f468cf Only convert allocas to scalars if it is profitable. The profitability metric I
chose is having a non-memcpy/memset use and being larger than any native integer
type. Originally I chose having an access of a size smaller than the total size
of the alloca, but this caused some minor issues on the spirit benchmark where
SRoA runs again after some inlining.

This fixes <rdar://problem/8613163>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:13:44 +00:00
Cameron Zwarich
0a0f6f342b Add native integer type TargetData to some existing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127717 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:13:40 +00:00
Johnny Chen
276f6f9cf9 There were two issues fixed:
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 22:27:33 +00:00
Bill Wendling
a24cb40be2 Some minor cleanups based on feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 20:47:26 +00:00
Evan Cheng
0191952296 Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 18:41:52 +00:00
Richard Osborne
8ae8cf4559 On the XCore the scavenging slot should be closest to the SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 15:10:11 +00:00
Richard Osborne
5aad8b3e78 Add XCore intrinsics for getps, setps, setsr and clrsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 13:45:47 +00:00
Justin Holewinski
625eec10fe PTX: Set PTX 2.0 as the minimum supported version
- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 13:24:15 +00:00
Cameron Zwarich
838b97edfa Do not add PHIs with no users when creating LCSSA form. Patch by Andrew Clinton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 07:41:25 +00:00
Evan Cheng
d158fba3e4 Add a peephole optimization to optimize pairs of bitcasts. e.g.
v2 = bitcast v1
...
v3 = bitcast v2
...
   = v3
=>
v2 = bitcast v1
...
   = v1
if v1 and v3 are of in the same register class.

bitcast between i32 and fp (and others) are often not nops since they
are in different register classes. These bitcast instructions are often
left because they are in different basic blocks and cannot be
eliminated by dag combine.

rdar://9104514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 05:13:13 +00:00
Eli Friedman
b1a6eab655 PR9450: Make switch optimization in SimplifyCFG not dependent on the ordering
of pointers in an std::map.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 02:23:35 +00:00
Evan Cheng
bf34a5ec22 sext(undef) = 0, because the top bits will all be the same.
zext(undef) = 0, because the top bits will be zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 02:22:10 +00:00
Bill Wendling
49c69bb70f Testcase for r127630.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127648 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:49:08 +00:00
Sean Callanan
9a9d8b9732 Basic sanity checks to ensure that 2- and 3-byte
VEX prefixes are working for triadic AVX
instructions.  This concludes the patch set to
enable AVX support for the X86 disassebler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:32:46 +00:00
Johnny Chen
085ea1b633 Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
register operand was erroneously added.  Remove an incorrect assert which triggers the bug.

rdar://problem/9131529


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:13:17 +00:00
Andrew Trick
c343c1e27e Propagate SCEV no-wrap flags whenever possible.
This needs review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127638 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 00:37:00 +00:00
Jim Grosbach
5edf24efac Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 00:30:40 +00:00
Eric Christopher
b9b80c3268 If we don't know how long a string is we can't fold an _chk version to the
normal version.

Fixes rdar://9123638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 00:25:41 +00:00
Bill Wendling
69a05a7b92 Generate a VTBL instruction instead of a series of loads and stores when we
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:

_shuf:
@ BB#0:       @ %entry
  push        {r4, r7, lr}
  add         r7, sp, #4
  sub         sp, #12
  mov         r4, sp
  bic         r4, r4, #7
  mov         sp, r4
  mov         r2, sp
  vmov        d16, r0, r1
  orr         r0, r2, #6
  orr         r3, r2, #7
  vst1.8      {d16[0]}, [r3]
  vst1.8      {d16[5]}, [r0]
  subs        r4, r7, #4
  orr         r0, r2, #5
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, #4
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, #3
  vst1.8      {d16[0]}, [r0]
  orr         r0, r2, #2
  vst1.8      {d16[2]}, [r0]
  orr         r0, r2, #1
  vst1.8      {d16[1]}, [r0]
  vst1.8      {d16[3]}, [r2]
  vldr.64     d16, [sp]
  vmov        r0, r1, d16
  mov         sp, r4
  pop         {r4, r7, pc}

The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 23:02:38 +00:00
Eric Christopher
29cfa21326 Fix this test up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 21:05:21 +00:00
Evan Cheng
5ae1da96f2 Minor optimization. sign-ext/anyext of undef is still undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 18:15:55 +00:00
Justin Holewinski
ae3ce17bac PTX: Emit global arrays with proper sizes
- Emit all arrays as type .b8 and proper sizes in bytes to conform
  to the output of nvcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 15:40:11 +00:00
Justin Holewinski
ba02495a57 PTX: Add support for sqrt/sin/cos intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 14:09:33 +00:00
Che-Liang Chiou
f78847ee7b ptx: add set.p instruction and related changes to predicate execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14 11:26:01 +00:00
Benjamin Kramer
14b2a59301 Teach ComputeMaskedBits about sub nsw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 17:18:11 +00:00
Eric Christopher
8b3000b08e Saving files before committing is overrated.
Add a RUN line to this test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:36:23 +00:00
Eric Christopher
af3dce5149 Sometimes isPredicable lies to us and tells us we don't need the operands.
Go ahead and add them on when we might want to use them and let
later passes remove them.

Fixes rdar://9118569


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-12 01:09:29 +00:00
Jim Grosbach
dd11988c99 Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
effect that we get proper instruction printing using the "pop" mnemonic for it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 22:51:41 +00:00
Cameron Zwarich
899eaa3569 Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:52:04 +00:00
Cameron Zwarich
53aac15a60 Fix the GCC test suite issue exposed by r127477, which was caused by stack
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 21:51:56 +00:00
Daniel Dunbar
950d3db5f4 Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
created from the", it broke some GCC test suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 19:30:30 +00:00
Benjamin Kramer
2715a58149 ComputeMaskedBits: sub falls through to add, and sub doesn't have the same overflow semantics as add.
Should fix the selfhost failures that started with r127463.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 14:46:49 +00:00
Benjamin Kramer
6b4972518c InstCombine: Fix a thinko where transform an icmp under the assumption that it's a zero comparison when it's not.
Fixes PR9454.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 11:37:40 +00:00
Nick Lewycky
b69050a94c Teach ComputeMaskedBits about nsw on add. I don't think there's anything we can
do with nuw here, but sub and mul should be given similar treatment.
Fixes PR9343 #15!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 09:00:19 +00:00
Cameron Zwarich
592ca3fda9 Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 04:54:27 +00:00
Eric Christopher
de5e101b0d Change the x86 32-bit scheduler to register pressure and fix up the
corresponding testcases back to the previous versions.

Fixes some performance regressions only seen on 32-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 01:05:58 +00:00
Evan Cheng
9ef82ce4fe Avoid replacing the value of a directly stored load with the stored value if the load is indexed. rdar://9117613.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11 00:48:56 +00:00
Jim Grosbach
d4a16ad85d Properly pseudo-ize MOVCCr and MOVCCs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 23:56:09 +00:00
Dan Gohman
fa0e6facc7 Fix reassociate to postpone certain instruction deletions until
after it has finished all of its reassociations, because its
habit of unlinking operands and holding them in a datastructure
while working means that it's not easy to determine when an
instruction is really dead until after all its regular work is
done. rdar://9096268.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 19:51:54 +00:00
Benjamin Kramer
6b96fe7e14 InstCombine: Turn umul_with_overflow into mul nuw if we can prove that it cannot overflow.
This happens a lot in clang-compiled C++ code because it adds overflow checks to operator new[]:
  unsigned *foo(unsigned n) { return new unsigned[n]; }
We can optimize away the overflow check on 64 bit targets because (uint64_t)n*4 cannot overflow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127418 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 18:40:14 +00:00
Justin Holewinski
fca9efcbc4 PTX: Add preliminary support for floating-point divide and multiply-and-add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 16:57:18 +00:00
Che-Liang Chiou
2f5565d21c ptx: add the rest of special registers of ISA version 2.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 04:05:57 +00:00
Stuart Hastings
03d5826164 Revert 127359; it broke lencod.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10 00:25:53 +00:00