Commit Graph

27843 Commits

Author SHA1 Message Date
Artyom Skrobov
e708238373 ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202257 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 11:27:28 +00:00
Daniel Sanders
f6679de299 [mips] Treat -mcpu=generic the same way as an empty CPU string.
Summary:
This should fix the MCJIT unit tests that were broken by r201792 on the MIPS buildbot.
MIPS currently uses the default implementation of sys::getHostCPUName() which
always returns "generic". For now, we will accept "generic" and coerce it to
"mips32" or "mips64" depending on the target architecture like we do for empty
CPU names.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202253 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 10:20:15 +00:00
Craig Topper
ecb903c1b5 [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:50:27 +00:00
Craig Topper
9262808ecd [x86] Remove some unused instruction format classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202234 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:06:38 +00:00
Craig Topper
df24b19e45 [x86] Simplify disassembler code slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202233 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:01:21 +00:00
Rafael Espindola
356deb5ecd Use DataLayout from the module when easily available.
Eventually DataLayoutPass should go away, but for now that is the only easy
way to get a DataLayout in some APIs. This patch only changes the ones that
have easy access to a Module.

One interesting issue with sometimes using DataLayoutPass and sometimes
fetching it from the Module is that we have to make sure they are equivalent.
We can get most of the way there by always constructing the pass with a Module.
In fact, the pass could be changed to point to an external DataLayout instead
of owning one to make this stricter.

Unfortunately, the C api passes a DataLayout, so it has to be up to the caller
to make sure the pass and the module are in sync.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 23:25:17 +00:00
Tom Stellard
431e9f0310 R600: Don't unconditionally unroll loops with private memory accesses
This causes the size of the scrypt kernel to explode and eats all the
memory on some systems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:21 +00:00
Tom Stellard
d8c31046a9 R600/SI: Custom select 64-bit ADD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:18 +00:00
Hal Finkel
15ac7dfb90 Account for 128-bit integer operations in PPCCTRLoops
We need to abort the formation of counter-register-based loops where there are
128-bit integer operations that might become function calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 20:51:50 +00:00
Richard Osborne
150f810744 [XCore] Add intrinsic for CLRPT (clear port time) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202172 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 17:31:15 +00:00
Richard Osborne
fb2f73acb9 [XCore] Add intrinsic for EDU (event disable unconditional) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 17:31:06 +00:00
Rafael Espindola
57edc9d4ff Make DataLayout a plain object, not a pass.
Instead, have a DataLayoutPass that holds one. This will allow parts of LLVM
don't don't handle passes to also use DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202168 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 17:30:31 +00:00
Richard Osborne
6dc9f732ce [XCore] Prefer to word align functions.
The behaviour of the XCore's instruction buffer means that the performance
of the same code sequence can differ depending on whether it starts at a 4
byte aligned address or not. Since we don't model the instruction buffer
in the backend we have no way of knowing for sure if it is beneficial to
word align a specific function. However, in the absence of precise
modelling, it is better on balance to word align functions because:

* It makes a fetch-nop while executing the prologue slightly less likely.
* If we don't word align functions then a small perturbation in one
  function can have a dramatic knock on effect. If the size of the function
  changes it might change the alignment and therefore the performance of
  all the functions that happen to follow it in the binary. This butterfly
  effect makes it harder to reason about and measure the performance of
  code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202163 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 16:37:15 +00:00
Alp Toker
bf930d5c1f Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 04:21:15 +00:00
Rafael Espindola
ec89b9fb9e Make some DataLayout pointers const.
No functionality change. Just reduces the noise of an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202087 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 23:12:18 +00:00
Albrecht Kadlec
0aedb78442 trivial test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202084 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 22:18:38 +00:00
Matt Arsenault
2e4ab2aa8a Fix unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:16:50 +00:00
Matt Arsenault
bc247e4afd R600/SI - Add new CI arithmetic instructions.
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:28 +00:00
Matt Arsenault
3f9f4bc0af R600: Make check clearer.
The check is clearer as southern islands or later,
rather than checking for later than northern islands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:23 +00:00
Matt Arsenault
e87a1a9e2c Fix DOT4 missing from getTargetOpcodeName
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202075 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:21 +00:00
Quentin Colombet
b55c398992 [X86][SchedModel] Add missing scheduling model for SSE related instructions.
The patch defines new or refines existing generic scheduling classes to match
the behavior of the SSE instructions.
It also maps those scheduling classes on the related SSE instructions.

<rdar://problem/15607571>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202065 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 19:33:51 +00:00
Roman Divacky
68e1531d39 Add a dwarf number to the Y register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202057 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 18:41:31 +00:00
Rafael Espindola
ac69459e0f Replace the F_Binary flag with a F_Text one.
After this I will set the default back to F_None. The advantage is that
before this patch forgetting to set F_Binary would corrupt a file on windows.
Forgetting to set F_Text produces one that cannot be read in notepad, which
is a better failure mode :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202052 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 18:20:12 +00:00
Christian Pirker
d7e12561a5 Add AArch64 big endian Target (aarch64_be)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202024 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 11:34:50 +00:00
Elena Demikhovsky
58423c8f1a AVX-512: Fixed encoding of VPCMPEQ and VPCMPGT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202015 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 10:08:30 +00:00
Benjamin Kramer
570d544799 SPARC: Implement TRAP lowering. Matches what GCC emits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201994 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 21:43:52 +00:00
Saleem Abdulrasool
b4702e215e ARMAsmParser: whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201989 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 17:45:36 +00:00
Saleem Abdulrasool
ec1c80576d ARM IAS: support .align without parameters
.align is handled specially on certain targets.  .align without any parameters
on ARM indicates a default alignment (4).  Handle the special case in the target
parser, but fall back to the generic parser for the normal version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 17:45:32 +00:00
Elena Demikhovsky
73f1a5fe45 AVX-512: Fixed encoding of VPTESTMQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201980 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 14:28:35 +00:00
Saleem Abdulrasool
be66089390 ARM IAS: support .short and .hword
This adds support for the .short and its alias .hword for adding literal values
into the object file.  This is similar to the .word directive, however, rather
than inserting a value of 4 bytes, adds a 2-byte value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201968 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 06:22:09 +00:00
Logan Chien
80668d18e8 Move get[S|U]LEB128Size() to LEB128.h.
This commit moves getSLEB128Size() and getULEB128Size() from
MCAsmInfo to LEB128.h and removes some copy-and-paste code.

Besides, this commit also adds some unit tests for the LEB128
functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201937 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-22 14:00:39 +00:00
Juergen Ributzka
94f20bfe6e [Stackmaps] Move the target-independent frame index elimination for stackmaps and patchpoints into target-specific code.
The lowering of the frame index for stackmaps and patchpoints requires some
target-specific magic and should therefore be handled in the target-specific
eliminateFrameIndex method.

This is related to <rdar://problem/16106219>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-21 23:29:32 +00:00
Kevin Qin
10ecde5c34 [AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201841 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-21 07:45:48 +00:00
Rafael Espindola
eb6e1d3165 Rename a few more DataLayout variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201833 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-21 01:53:35 +00:00
Benjamin Kramer
3e552a331b Remove unnecessary copy of array_lengthof.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201798 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 17:36:31 +00:00
Oliver Stannard
71f63717a8 AArch64: __va_list.__stack must be 8-byte aligned
The va_start macro for AArch64 must set va_list.__stack to the address
following the last named argument on the stack, rounded up to an alignment
of 8 bytes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201797 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 17:19:26 +00:00
Chad Rosier
fda2dfbca7 [AArch64] Add support for TargetTransformInfo Analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 16:00:08 +00:00
Daniel Sanders
5c86661f15 [mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.
Summary:
This removes the need to coerce UnknownABI to the default ABI (O32 for
MIPS32, N64 for MIPS64 [*]) in both MipsSubtarget and MipsAsmParser.

Clang has been updated to disable both possible default ABI's before enabling
the ABI it intends to use.

[*] N64 being the default for MIPS64 is not actually correct.
    However N32 is not fully implemented/tested yet.

Depends on: D2830

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2832
Differential Revision: http://llvm-reviews.chandlerc.com/D2846



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 14:58:19 +00:00
NAKAMURA Takumi
1e3bb3fc41 [CMake] Move intrinsics_gen to lib/Target out of add_public_tablegen_target.
add_public_tablegen_target is used somewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 13:42:30 +00:00
Daniel Sanders
7934a2a9f1 [mips] Make mips64 the default CPU for the mips64 architecture
Summary:
This is consistent with the integrated assembler.
All mips64 codegen tests previously passed -mcpu. Removed -mcpu from
blez_bgez.ll and const-mult.ll to cover the default case.

Ideally, the two implementations of selectMipsCPU() will be merged but it's
proven difficult to find a home for the function that doesn't cause link errors.
For now, we'll hoist the common functionality into a function and mark it with
FIXME's.

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201782 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 13:13:33 +00:00
Craig Topper
46aa7fb720 [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 07:59:43 +00:00
Elena Demikhovsky
143df776e2 AVX-512: Fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201761 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 07:00:10 +00:00
Elena Demikhovsky
08316a11e4 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com)
Fixed truncate i32 to i1; a test will be provided in the next commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 06:34:39 +00:00
Reed Kotler
fccbee8faf Make one statement easier to understand from post commmit feedback from a
review of the previous patch that introduced this week.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201723 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 22:11:45 +00:00
Roman Divacky
3bd3f426a5 Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201718 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 21:35:39 +00:00
Rafael Espindola
b4aaffffd3 move getNameWithPrefix and getSymbol to TargetMachine.
TargetLoweringBase is implemented in CodeGen, so before this patch we had
a dependency fom Target to CodeGen. This would show up as a link failure of
llvm-stress when building with -DBUILD_SHARED_LIBS=ON.

This fixes pr18900.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 20:30:41 +00:00
Rafael Espindola
737c9f6005 Add back r201608, r201622, r201624 and r201625
r201608 made llvm corretly handle private globals with MachO. r201622 fixed
a bug in it and r201624 and r201625 were changes for using private linkage,
assuming that llvm would do the right thing.

They all got reverted because r201608 introduced a crash in LTO. This patch
includes a fix for that. The issue was that TargetLoweringObjectFile now has
to be initialized before we can mangle names of private globals. This is
trivially true during the normal codegen pipeline (the asm printer does it),
but LTO has to do it manually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201700 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 17:23:20 +00:00
Christian Pirker
eb5fe7002a Test commit - remove the new line to lib/Target/AArch64/AArch64TargetMachine.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201698 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 16:58:28 +00:00
Daniel Sanders
ffac49bd7f [mips] In the integrated assembler, select the default feature bits by changing the CPU value.
This is consistent with the way CodeGen acheives this. However, CodeGen
always selects mips32 (even when the architecture is mips64).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201694 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 16:13:26 +00:00
Christian Pirker
f47b32ed76 Test commit - added a new line to lib/Target/AArch64/AArch64TargetMachine.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201692 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 16:07:32 +00:00