to the TargetAsmLexer class so that clients can
actually use the TargetAsmLexer they get from a
Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94940 91177308-0d34-0410-b5e6-96231b3b80d8
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
unconditionally. Besides checking the offset, also check that the underlying
object is aligned as much as the load itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94875 91177308-0d34-0410-b5e6-96231b3b80d8
something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
movl $0, %eax
as
movl 0, %eax
Feel free to guess how well that worked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94869 91177308-0d34-0410-b5e6-96231b3b80d8
needed for this test, but otherwise, there's nothing ARM-specific about
it and no need to specify the calling convention.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94862 91177308-0d34-0410-b5e6-96231b3b80d8
line. Turns out edit_distance can be slow if the string we are scanning for
happens to be quite large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94860 91177308-0d34-0410-b5e6-96231b3b80d8
This bug was exposed by my inliner cost changes in r94615, and caused failures
of lencod on most architectures when building with LTO.
This patch fixes lencod and 464.h264ref on x86-64 (and likely others).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94858 91177308-0d34-0410-b5e6-96231b3b80d8
- This test case is auto generated, and has been verified to round-trip
correctly through llvm-mc by checking the assembled .o file before and after
piping through llvm-mc. It will be extended over time as the matcher grows
support for more instructions.
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bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94855 91177308-0d34-0410-b5e6-96231b3b80d8
create a testcase where this matters. The select+load transformation only
occurs when isSafeToLoadUnconditionally is true, and in those situations,
instcombine also changes the underlying objects to be aligned. This seems
like a good idea regardless, and I've verified that it doesn't pessimize
the subsequent realignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94850 91177308-0d34-0410-b5e6-96231b3b80d8
Before:
<stdin>:94:1: note: possible intended match here
movsd 4096(%rsi), %xmm0
^
After:
<stdin>:94:2: note: possible intended match here
movsd 4096(%rsi), %xmm0
^
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that loads its contents lazily from bitcode. I think these are the
only remaining mis-named functions.
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(via APInt &RHSKnownZero = KnownZero, etc) seems dangerous and confusing to me: it
is easy not to notice this, and then wonder why KnownZero/RHSKnownZero changed
underneath you when you modified RHSKnownZero/KnownZero etc. So get rid of this.
No intended functionality change (tested with "make check" + llvm-gcc bootstrap).
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