Owen Anderson
33e57515b1
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 00:03:03 +00:00
Eric Christopher
8c09e2a701
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 00:02:39 +00:00
Eric Christopher
125feacf5b
clang is the new black.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137187 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:59:05 +00:00
Jakob Stoklund Olesen
c66d36028b
Trim an unneeded header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:49:21 +00:00
Jakob Stoklund Olesen
c70c2cafe1
Promote VMOVS to VMOVD when possible.
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On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
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vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:41:44 +00:00
Owen Anderson
de317f40f7
Tighten operand checking of register-shifted-register operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:33:27 +00:00
Bruno Cardoso Lopes
d40aa24ebf
Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:27:13 +00:00
Eli Friedman
8fa281a471
Fix minor typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:26:12 +00:00
Owen Anderson
c36481c474
Tighten operand checking on memory barrier instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:25:42 +00:00
NAKAMURA Takumi
77c714027c
VMCore/BasicBlock.cpp: Don't assume BasicBlock::iterator might end with a non-PHInode Instruction in successors.
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Frontends(eg. clang) might pass incomplete form of IR, to step off the way beyond iterator end. In the case I had met, it took infinite loop due to meeting bogus PHInode.
Thanks to Jay Foad and John McCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:13:05 +00:00
NAKAMURA Takumi
8fc9b3db53
Fix whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:12:56 +00:00
Owen Anderson
35008c2f8d
Tighten operand checking on CPS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:05:39 +00:00
Owen Anderson
438f68df35
Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:05:23 +00:00
Eli Friedman
21006d40ac
Representation of 'atomic load' and 'atomic store' in IR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:02:53 +00:00
Owen Anderson
51c9805c4b
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes
18deb04e9c
Add v16i16 and v32i8 store patterns
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:39:53 +00:00
Chad Rosier
6ff9aa2aa7
Fix 80-column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:23:40 +00:00
Rafael Espindola
dd3d68f7a9
Add missing file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137162 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:19:52 +00:00
Bruno Cardoso Lopes
cde4a1abd5
Use fp unpack instructions to unpack int types. Until we have AVX2, this
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is the best we can do for these patterns. This fix PR10554.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:18:37 +00:00
Eli Friedman
fc430a662f
Fix a couple ridiculous copy-paste errors. rdar://9914773 .
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:17:39 +00:00
Rafael Espindola
69cb216009
Add a C interface to PassManagerBuilder. It is missing the addExtension
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functionality since in the C api a pass is created and added to a pass
manager in a single call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:17:34 +00:00
Jim Grosbach
739b5576ad
Don't truncate MachO addresses.
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Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms.
That's obviously bogus.
For example,
.globl _foo
.equ _foo, 0x987654321ULL
rdar://9922863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:12:37 +00:00
Benjamin Kramer
793b811c50
ARM Disassembler: sign extend branch immediates.
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Not sure about BLXi, but this is what the old disassembler did.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:02:50 +00:00
Owen Anderson
51157d2234
Silence an false-positive warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:38:14 +00:00
Owen Anderson
65e95d950d
Don't generate the old-style disassembler in CMake builds either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:36:11 +00:00
Benjamin Kramer
9bd7c2836e
The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:34:19 +00:00
Owen Anderson
ad0d36b79f
Don't continue generating the old-style decoder file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:30:29 +00:00
Jim Grosbach
6cd5716f61
ARM fix typo in pre-indexed store lowering.
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rdar://9915869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:22:41 +00:00
Owen Anderson
e6afbabb63
Attempt to fix CMake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137147 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:09:59 +00:00
Owen Anderson
bd9091c18d
Tighten Thumb1 branch predicate decoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:07:45 +00:00
Eli Friedman
138515df66
First draft of the practical guide to atomics.
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This is mostly descriptive of the intended state once atomic load and store have landed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137145 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 21:07:10 +00:00
Owen Anderson
8d7d2e1238
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 20:55:18 +00:00
Bob Wilson
0dc8b42987
Put Darwin-specific code inside an __APPLE__ ifdef.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 19:54:32 +00:00
Bill Wendling
c6fbe5636d
Revert r137134. It breaks some code as Eli pointed out.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 18:56:35 +00:00
Bill Wendling
a0f596c1fc
Print out the variable declaration only if it is a declaration. Otherwise, a
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'static' variable will be emitted twice.
PR10081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 18:31:50 +00:00
Jakob Stoklund Olesen
4a74b3b933
Inflate register classes after coalescing.
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Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class. Examples are:
x86: GR32_ABCD:sub_8bit_hi -> GR32
arm: DPR_VFP2:ssub0 -> DPR
Recompute the register class of any virtual registers that are used by
less instructions after coalescing.
This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:
vadd.f32 d16, d1, d0
vcvt.s32.f32 d0, d16
The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 18:19:41 +00:00
Bruno Cardoso Lopes
e2406dfd89
Reapply a more appropriate solution than in r137114. AVX supports
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v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes
a511b8e519
Revert r137114
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 17:39:01 +00:00
Justin Holewinski
4bdd4ed564
PTX: Add initial support for device function calls
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- Calls are supported on SM 2.0+ for function with no return values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 17:36:31 +00:00
Jakob Stoklund Olesen
6d1fd0b979
Move CalculateRegClass to MRI::recomputeRegClass.
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This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 16:46:27 +00:00
Renato Golin
719927a68f
Emitting ARM build attributes and values as ULEB, rather than char.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 09:50:10 +00:00
Bruno Cardoso Lopes
e321d7ffc5
Handle sitofp between v4f64 <- v4i32. Fix PR10559
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 05:48:01 +00:00
Bob Wilson
f5b757642d
Recognize the UNAME_RELEASE environment variable to match Darwin's uname.
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When this variable is set, "uname -r" will return its value instead of the
real OS version. Make this affect LLVM's triple for consistency.
<rdar://problem/9919167>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 05:13:36 +00:00
Andrew Trick
70d0ca999c
LoopUnroll looks like it has some stale code. Remove it to prove my sanity and avoid further confusion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 03:11:29 +00:00
Bruno Cardoso Lopes
2f613c5fff
Add support for avx vector fextend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes
a1dfb63b78
Add AVX versions of 128-bit sitofp and fptosi
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 03:04:25 +00:00
Bruno Cardoso Lopes
b33ea56448
Rename and tidy up tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 03:04:23 +00:00
Bruno Cardoso Lopes
e5118ab7bb
Add two patterns to match special vmovss and vmovsd cases. Also fix
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the patterns already there to be more strict regarding the predicate.
This fixes PR10558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 01:43:09 +00:00
Bill Wendling
8d676c2199
There is only one instance of this placeholder being created. Just use that
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instead of a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 01:17:10 +00:00
Bill Wendling
4fa93b7ce1
Remove an instance where the 'unwind' instruction was created.
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The 'unwind' instruction was acting essentially as a placeholder, because it
would be replaced at the end of this function by a branch to the "unwind
handler". The 'unwind' instruction is going away, so use 'unreachable' instead,
which serves the same purpose as a placeholder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 01:09:21 +00:00