Commit Graph

1043 Commits

Author SHA1 Message Date
Saleem Abdulrasool
8f57233536 ARM: bkpt has an implicit immediate constant 0
The bkpt mnemonic has an implicit immediate constant of 0 unless otherwise
specified.  Add an instruction alias for the unvalued breakpoint mnemonic to
treat it as a 0.  This improves compatibility with GNU AS.

Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197913 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-23 17:23:58 +00:00
Chad Rosier
e834f41f7a Update the UseFusedMAC definition to directly specify its dependence on having
VFP4.
Patch by Daniel Stewart!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-04 17:16:36 +00:00
Tim Northover
f715d51769 ARM: add pseudo-instructions for lit-pool global materialisation
These are used by MachO only at the moment, and (much like the existing
MOVW/MOVT set) work around the fact that the labels used in the actual
instructions often contain PC-dependent components, which means that repeatedly
materialising the same global can't be CSEed.

With small modifications, it could be adapted to how ELF finds the address of
_GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 10:35:41 +00:00
Tim Northover
ff3808915c ARM: remove special cases for Darwin dynamic-no-pic mode.
These are handled almost identically to static mode (and ELF's global address
materialisation), except that a symbol may have "$non_lazy_ptr" appended. This
can be handled by passing appropriate flags along with the instruction instead
of using entirely separate pseudo-instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195655 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 16:24:52 +00:00
Tim Northover
761bf235a8 ARM: remove unused patterns.
There is no sane way for an LEApcrel (= single ADR) instruction to generate a
global address on any ARM target I know of. Fortunately, no-one was trying to
any more, but there were vestigial patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195644 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-25 14:40:57 +00:00
Artyom Skrobov
fa840ba402 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:16:30 +00:00
Bernard Ogden
47c6d17b1c ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 09:47:35 +00:00
Tim Northover
44edc227c7 ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.

No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.

rdar://problem/15302004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 15:49:39 +00:00
Artyom Skrobov
b161955ffb Make ARM hint ranges consistent, and add tests for these ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-23 10:14:40 +00:00
Silviu Baranga
b1c480900b Add hardware division as a default feature on Cortex-A15. Also add test cases to check this, and change diagnostics for the hwdiv-arm feature to something useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192963 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-18 10:18:40 +00:00
Tim Northover
cf3e4cb29a ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.

rdar://problem/15144406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-07 11:10:47 +00:00
Amara Emerson
6eef361b73 [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
Patch by Artyom Skrobov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 09:31:51 +00:00
Tim Northover
bba9390fc6 ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.

rdar://problem/14207019

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 14:33:28 +00:00
Joey Gouly
d1311ac171 [ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01 12:39:11 +00:00
Amara Emerson
268c743a3b [ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 12:22:36 +00:00
Amara Emerson
0f22c134be [ARM] Split A/R class into separate subtarget features.
Patch by Bradley Smith.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 14:26:15 +00:00
Amara Emerson
5df37dab76 [ARMv8] Add support for the v8 cryptography extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-19 11:59:01 +00:00
Joey Gouly
a4d46d7fc6 [ARMv8] Add CRC instructions.
Patch by Bradley Smith!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-18 09:45:55 +00:00
Joey Gouly
2a9af9f18e [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options
to be more consistent.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-13 13:46:57 +00:00
Joey Gouly
715d98d657 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12 10:28:05 +00:00
Joey Gouly
4897151df6 [ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 15:35:24 +00:00
Richard Barton
b5523ce1bb Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.

The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.

HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.

Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 14:14:19 +00:00
Joey Gouly
b2e5453821 [ARMv8]
Fix a few things in one swoop.

# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 16:39:20 +00:00
Joey Gouly
0b90c6223d [ARMv8] Add MC support for the new load/store acquire/release instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 17:38:16 +00:00
Joey Gouly
a0b2d332c1 [ARMv8] Add CodeGen for VMAXNM/VMINNM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 12:01:13 +00:00
Tim Northover
287c84a0b4 ARM: make sure ARM-mode pseudo-inst requires IsARM
I'd forgotten that "Requires" blocks override rather than add to the
constraints, so my pseudo-instruction was being selected in Thumb mode leading
to nonsense instructions.

rdar://problem/14817358

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 10:16:39 +00:00
Tim Northover
f7ab3a84b3 ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 09:57:11 +00:00
Mihai Popa
1a9f21abac Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 13:14:58 +00:00
Joey Gouly
3f87f2510c ARMv8: SWP and SWPB are obsoleted on ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 16:40:47 +00:00
Silviu Baranga
fd79485dfa Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 09:25:50 +00:00
Tim Northover
1c6e6ce10c ARM: remove now unneeded custom Asm converters
After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186810 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 09:06:12 +00:00
Tim Northover
2f438131f1 ARM: implement ldrex, strex and clrex intrinsics
Intrinsics already existed for the 64-bit variants, so these support operations
of size at most 32-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 09:46:55 +00:00
Arnold Schwaighofer
fe3b2995aa ARM: Add a pack pattern for matching arithmetic shift right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185714 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 18:57:49 +00:00
Arnold Schwaighofer
ffd3bb8f0d ARM: Fix incorrect pack pattern
A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them
in the bottom half of "x". An arithmetic and logic shift are only equivalent in
this context if the shift amount is 16. We would be shifting in ones into the
bottom 16bits instead of zeros if "y" is negative.

radar://14338767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-05 18:28:39 +00:00
Joey Gouly
929d9ef111 Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 10:04:08 +00:00
Mihai Popa
b81b477cd4 This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 09:21:44 +00:00
Tilmann Scheller
a744d41a3f ARM: Fix pseudo-instructions for SRS (Store Return State).
The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is:

srsfa -> srsib
srsea -> srsia
srsfd -> srsdb
srsed -> srsda

This fixes <rdar://problem/14214734>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185155 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 15:09:46 +00:00
Joey Gouly
849eedce99 Add a subtarget feature 'v8' to the ARM backend.
This allows for targeting the ARMv8 AArch32 variant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 16:58:26 +00:00
Tim Northover
c19bd32136 ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):

+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 16:52:40 +00:00
Joey Gouly
4cbbbf49b6 This reverts r155000.
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.

VFP instructions on v8/AArch32 share the same encoding space as cdp2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 17:42:36 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
Amaury de la Vieuville
4e9a96d810 ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 14:17:08 +00:00
Amaury de la Vieuville
46e136c952 ARM: fix CPS decoding when ambiguous with QADD
Handle the case when the disassembler table can't tell
the difference between some encodings of QADD and CPS.

Add some necessary safe guards in CPS decoding as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 13:38:52 +00:00
Arnold Schwaighofer
87aab6dc96 ARM sched model: Add branch instructions
Reapply 183263.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 18:21:13 +00:00
Arnold Schwaighofer
e022a6b0f4 ARM sched model: Add preload instructions
Reapply 183261.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 17:26:12 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:43:09 +00:00
Arnold Schwaighofer
31588f3005 ARM sched model: Add more ALU and CMP instructions
Reapply of 183258.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183321 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 16:36:51 +00:00
Mihai Popa
2248cf5906 This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 13:23:51 +00:00
Arnold Schwaighofer
8a227084a5 Revert series of sched model patches until I figure out what is going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
36ea791280 ARM sched model: Add branch instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:56 +00:00