Commit Graph

1043 Commits

Author SHA1 Message Date
Jim Grosbach
e91e7bcadc ARM pre-UAL NEG mnemonic for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:23:22 +00:00
Jim Grosbach
840bf7eda7 ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:02:17 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:30:04 +00:00
Jim Grosbach
3bc8a3d3af ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:31:07 +00:00
Jim Grosbach
3b8991cc98 ARM: NEON SHLL instruction immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:07:24 +00:00
Jim Grosbach
23261af193 ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:28:00 +00:00
Jim Grosbach
587f5062b9 ARM NEON VEXT aliases for data type suffices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 23:34:39 +00:00
Jim Grosbach
98b05a57b6 ARM parsing aliases for VLD1 single register all lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 01:09:44 +00:00
Jim Grosbach
40a86ee20f ARM assembly parsing for shifted register operands for MOV instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:50:05 +00:00
Jim Grosbach
b598b04409 ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:12:24 +00:00
Jim Grosbach
48b368bcd5 ARM assembly parsing for RRX mnemonic.
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:05:59 +00:00
Jim Grosbach
23f220705a ARM mode aliases for bitwise instructions w/ register operands.
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:31:45 +00:00
Bob Wilson
d0405aaabc Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 17:09:59 +00:00
Bob Wilson
eaab6ef6eb Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:11:57 +00:00
Jim Grosbach
9f302c4fb3 ARM assembly parsing two operand forms for shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:27:54 +00:00
Jim Grosbach
d2586daf06 ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:02:06 +00:00
Jay Foad
bf8356b37c Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:50:05 +00:00
Jim Grosbach
9588c10b69 ARM refactor simple immediate asm operand render methods.
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12 00:58:43 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate).
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 16:44:55 +00:00
Jim Grosbach
c27f6725b9 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 00:02:33 +00:00
Evan Cheng
c39916b166 Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04 01:48:58 +00:00
Jim Grosbach
e70ec84637 ARM mode 'mov' to 'mvn' assembler alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 22:50:54 +00:00
Owen Anderson
cb9fed6655 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 18:02:13 +00:00
Owen Anderson
82418ff4d1 Revert r143202.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 17:38:30 +00:00
Owen Anderson
7ccee5610a Specify fixed bits on CPS instructions to enable roundtripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 17:29:39 +00:00
Owen Anderson
cd20c58e98 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 22:23:58 +00:00
Owen Anderson
a3a6f215d0 Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 21:24:38 +00:00
Andrew Trick
90b7b12f01 Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 19:18:52 +00:00
David Meyer
928698b14e Remove NaClMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 05:29:23 +00:00
Joe Abbey
895ede819f Commit test, capitalizing store... keep it simple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142336 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 04:44:36 +00:00
Bill Wendling
13a7121858 Now Igor, throw the switch...give my creation life!
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.

It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.

Neat, huh?
<rdar://problem/10116753>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 22:26:23 +00:00
Jim Grosbach
9b8f2a0b36 ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:34:41 +00:00
Jim Grosbach
2bd0118472 ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:55:36 +00:00
Jim Grosbach
2cf8dd384e ARM addressing mode cleanup for LDC/STC.
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 20:17:35 +00:00
Jim Grosbach
57dcb85a30 ARM parse alignment specifier for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 17:29:55 +00:00
Bill Wendling
ef2c86f876 Reapply r141365 now that PR11107 is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:59:55 +00:00
Jim Grosbach
38fbe32315 Add a name to sub-operand for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:55:05 +00:00
Bill Wendling
eba564ceac Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:27:30 +00:00
Anton Korobeynikov
244455e6d6 Peephole optimization for ABS on ARM.
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:15:08 +00:00
Kevin Enderby
9e5887b17e Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 22:44:48 +00:00
James Molloy
acad68da50 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
Andrew Trick
3be654f808 Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 02:20:46 +00:00
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:17:40 +00:00
Jim Grosbach
6053cd956f Thumb2 assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:30:45 +00:00
Jim Grosbach
ab3bf97fe0 Thumb2 assembly parsing and encoding for UQASX/UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 00:18:52 +00:00
Jim Grosbach
6729c48b94 Thumb2 assembly parsing and encoding for UHASX/UHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:13:25 +00:00
Jim Grosbach
4032eaf98c Thumb2 assembly parsing and encoding for UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:05:22 +00:00
Jim Grosbach
50bd470d85 Thumb2 assembly parsing and encoding for SSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139929 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 18:37:10 +00:00
Jim Grosbach
c075d45364 Thumb2 assembly parsing and encoding for SHASX/SHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 22:34:29 +00:00
Jim Grosbach
e4e4a93e9e Thumb2 assembly parsing and encoding for SASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 21:01:23 +00:00
Jim Grosbach
b6e9a83349 ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139796 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 16:16:50 +00:00
Jim Grosbach
e1d58a6556 ARM tighten up the register classes for the PKH instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 22:52:14 +00:00
Eli Friedman
885f1a0c04 Zap some junk from the ARM instruction descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13 02:29:58 +00:00
Owen Anderson
170580e8f4 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 00:11:18 +00:00
Jim Grosbach
94f914e3fd Thumb2 parsing and encoding for LDMDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:57:53 +00:00
Eli Friedman
34c4485b74 Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 20:53:37 +00:00
Evan Cheng
4a51708448 Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 18:52:20 +00:00
Jakob Stoklund Olesen
9b0e1e7a5b Atomic pseudos don't use (as in read) CPSR. They clobber it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06 17:40:35 +00:00
Nick Lewycky
1fac6b50ea Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-05 21:51:43 +00:00
Eli Friedman
4d3f329453 64-bit atomic cmpxchg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 17:52:22 +00:00
Eli Friedman
3d93861c23 Some minor cleanups for r138845.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 00:41:05 +00:00
Eli Friedman
2bdffe4882 Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 00:31:29 +00:00
Evan Cheng
37fefc20d3 Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:09:48 +00:00
Evan Cheng
342e3161d9 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 01:34:54 +00:00
Owen Anderson
1f26758510 Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138760 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 20:42:00 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 23:32:08 +00:00
Owen Anderson
9ab0f25fc1 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 20:43:14 +00:00
Owen Anderson
96425c8464 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:09:22 +00:00
Eli Friedman
069e2ed794 Atomic load/store on ARM/Thumb.
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 02:59:24 +00:00
Jim Grosbach
a33b31be45 Clean up predicates on ARM target instruction aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:04:24 +00:00
Jim Grosbach
ef3bf64bf8 Fix predicate for imm1_32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 21:01:11 +00:00
Owen Anderson
5df7ef6cdb Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:08:25 +00:00
Owen Anderson
0d09499cf3 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:36:11 +00:00
Owen Anderson
79628e92e1 Fix decoding of ARM-mode STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:02:50 +00:00
Owen Anderson
6368119c25 Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 19:41:29 +00:00
Owen Anderson
7cdbf086e4 Fix decoding of pre-indexed stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 18:12:39 +00:00
Owen Anderson
3f3570a38b Separate decoding for STREXD and LDREXD to make each work better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 17:58:32 +00:00
Jim Grosbach
d30970fb6c Remove no-longer-true comments. These are for the assembler, also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:30:30 +00:00
Jim Grosbach
342ebd5f38 ARM STRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:18:00 +00:00
Owen Anderson
41ff834e91 Make the USAT16 operand decoder auto-generate-able.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:10:11 +00:00
Owen Anderson
05b0c9f41e Making SEL decodings auto-generate-able.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:50:56 +00:00
Jim Grosbach
89958d50c3 Tidy up comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:41:59 +00:00
Owen Anderson
cbfc044acd Fix decoding support for STREXD and LDREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:34:58 +00:00
Jim Grosbach
7b8f46cf9e ARM STRH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:17:22 +00:00
Jim Grosbach
45251b3707 Tidy up. Remove unused template parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:41:13 +00:00
Jim Grosbach
14605d1a67 ARM STRD assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:28:23 +00:00
Owen Anderson
26d2f0ac91 Continue to tighten decoding by performing more operand validation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:21:46 +00:00
Jim Grosbach
ade7d00f5a Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:13:35 +00:00
Jim Grosbach
10348e70d5 ARM STRBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:04:56 +00:00
Jim Grosbach
548340c4bf ARM STR(immediate) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:22:40 +00:00
Owen Anderson
2b7b238e84 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:55:42 +00:00
Jim Grosbach
59999264e6 ARM LDRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:43:54 +00:00
Jim Grosbach
e15defc56c Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 23:23:47 +00:00
Jim Grosbach
623a454b0f ARM LDRH(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 22:42:16 +00:00
Jim Grosbach
251bf25e7e ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 21:56:18 +00:00
Jim Grosbach
2fd2b87ded ARM LDRD(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 20:29:19 +00:00
Owen Anderson
fd9085dca3 Tabs --> spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 17:38:05 +00:00
Owen Anderson
33e57515b1 Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 00:03:03 +00:00
Owen Anderson
de317f40f7 Tighten operand checking of register-shifted-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:33:27 +00:00
Owen Anderson
c36481c474 Tighten operand checking on memory barrier instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:25:42 +00:00
Owen Anderson
35008c2f8d Tighten operand checking on CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:05:39 +00:00
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:48:45 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 20:55:18 +00:00
Jim Grosbach
3148a65490 ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 23:28:47 +00:00
Jim Grosbach
f4fa3d6e46 ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 21:28:30 +00:00
Jim Grosbach
19dec207fc ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 20:35:44 +00:00
Jim Grosbach
ca8c70b953 ARM use a dedicated printer for postidx_reg operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05 15:48:21 +00:00
Jim Grosbach
039c2e19c4 ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 23:01:30 +00:00
Owen Anderson
154c41dbbc LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 18:24:14 +00:00
Jim Grosbach
7ce057983e ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03 23:50:40 +00:00
Jim Grosbach
b93509d382 Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02 18:16:36 +00:00
Jim Grosbach
e39389a58d ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02 18:07:32 +00:00
Jim Grosbach
02c8460a74 Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01 22:02:20 +00:00
Jim Grosbach
b2756afa27 Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01 21:55:12 +00:00
Jim Grosbach
e1cf5902ec ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 20:26:09 +00:00
Jim Grosbach
33768dba54 ARM CPS mode immediate is 5 bits, not 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 20:02:39 +00:00
Jim Grosbach
2c6363a62d ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 18:47:24 +00:00
Jim Grosbach
5a28748360 ARM SRS and RFE instructions are not code-gen only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 17:51:39 +00:00
Jim Grosbach
b48ce900f9 ARM range checking for mode on CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 17:42:17 +00:00
Jim Grosbach
96e24fa892 Update FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 17:36:04 +00:00
Jim Grosbach
bd4562e163 Tweak comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 17:33:29 +00:00
Jim Grosbach
cf121c35c4 ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 21:57:55 +00:00
Jim Grosbach
293a2ee306 ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 21:34:26 +00:00
Jim Grosbach
c29769b0e8 Add fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 19:46:12 +00:00
Owen Anderson
8313b48bbe Fill in some encoding information for STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 17:53:25 +00:00
Owen Anderson
aa3402e280 Revert r136295. It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering. I hope to revive this sometime in the future, but it's not strictly necessary for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136362 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 17:18:57 +00:00
Jim Grosbach
70a0915cd1 ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28 16:33:54 +00:00
Owen Anderson
7b2958392c Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 23:36:57 +00:00
Jim Grosbach
addec77b54 ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 22:34:17 +00:00
Jim Grosbach
fb8989e640 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:09:25 +00:00
Owen Anderson
06470311c5 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:29:48 +00:00
Jim Grosbach
7e1547ebf7 ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:15:40 +00:00
Jim Grosbach
766c63e78b ARM assembly parsing aliases for extend instructions w/o rotate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 18:19:32 +00:00
Jim Grosbach
7032741e7b ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 17:48:13 +00:00
Jim Grosbach
c5a8c861c9 ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 16:47:19 +00:00
Jim Grosbach
45f3929ef0 ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:44:37 +00:00
Jim Grosbach
85bfd3b023 ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:28:43 +00:00
Owen Anderson
793e79601f Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:54:26 +00:00
Jim Grosbach
4f6f13db1a ARM assembly parsing and encoding for SWP[B] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:15:11 +00:00
Jim Grosbach
1ef91417bd ARM SWP instructions store, too, not just load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:11:05 +00:00
Jim Grosbach
1355cf1f76 Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:10:22 +00:00
Jim Grosbach
3d5ab367b6 ARM fix asm parsing range check for [0,31] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 16:44:05 +00:00
Jim Grosbach
ed8384806e ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 16:24:27 +00:00
Jim Grosbach
f49433523e ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:09:14 +00:00
Jim Grosbach
580f4a9c1c ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:20:28 +00:00
Jim Grosbach
e4616ace02 Simply ARM so_reg MIOperandInfo definitions.
The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:04:58 +00:00
Jim Grosbach
af6981f2f5 ARM asm operand renaming. Make things a bit more explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 20:49:51 +00:00
Jim Grosbach
5f6c133d7d More simple cleanup of ARM asm operand definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 20:38:18 +00:00
Jim Grosbach
43904299b0 Make assembly parser method names more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135950 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 20:14:50 +00:00
Jim Grosbach
1610a70965 Tidy up formatting.
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 20:06:30 +00:00
Jim Grosbach
1e93b24246 Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 20:00:32 +00:00
Jim Grosbach
4a5ffb399f ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 23:16:18 +00:00
Jim Grosbach
b206daaec1 ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:11:20 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:13:31 +00:00
Jim Grosbach
7931df3d74 Clean up a few more comments.
These instruction definitions are for the assembler, too, not just the
disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:06:01 +00:00
Jim Grosbach
0fdf6ccf17 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:04:10 +00:00
Jim Grosbach
53a89d6f38 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 17:46:13 +00:00
Jim Grosbach
6c1bb77992 Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 16:59:04 +00:00
Owen Anderson
152d4a4bb6 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:38:37 +00:00
Jim Grosbach
7c6e42e927 ARM Asm parser range checking for [0,31] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:26:25 +00:00
Jim Grosbach
f790193aec ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7 ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:37:43 +00:00
Jim Grosbach
10c7d70a4e ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 19:57:11 +00:00
Owen Anderson
92a202213b Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 18:54:16 +00:00
Jim Grosbach
f6c0525d42 ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 17:23:04 +00:00
Jim Grosbach
dde038af59 ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 21:40:26 +00:00
Jim Grosbach
1769a3df4a Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135617 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 20:49:03 +00:00
Jim Grosbach
a0472dc420 ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 20:32:09 +00:00
Jim Grosbach
b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 22:45:10 +00:00
Jim Grosbach
80d01dd3d1 ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 21:59:29 +00:00
Jim Grosbach
ccfd9313d1 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:35:35 +00:00
Jim Grosbach
ffa3225e26 ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 19:13:28 +00:00
Jim Grosbach
6bc1dbc376 ARM range checking for so_imm operands in assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 16:50:30 +00:00
Benjamin Kramer
3be41b748e Port operand types for ARM and X86 over from EDIS to the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135198 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:47:22 +00:00
Jim Grosbach
c8ae39e746 ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:26:42 +00:00
Jim Grosbach
e540c7422c ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:19:17 +00:00
Jim Grosbach
c83d504085 Reorganize ARM assembler aliases.
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 19:47:47 +00:00
Jim Grosbach
3b14a5c546 Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:35:38 +00:00
Jim Grosbach
9dec507ecb ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:00:31 +00:00
Jim Grosbach
e77494e3e3 ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:18:13 +00:00
Jim Grosbach
77f379e2a1 DMB instalias needs the same predicate as the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135112 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 00:10:26 +00:00
Jim Grosbach
032434d622 ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:40:38 +00:00
Jim Grosbach
20fcaffaf7 Update comments. These are for assembler, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:33:10 +00:00
Owen Anderson
16884415db Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:22:26 +00:00
Jim Grosbach
6f9f884502 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:59:38 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:01:08 +00:00
Jim Grosbach
898e7e26a5 Fix encoding for ARM BXJ instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:25:01 +00:00
Jim Grosbach
d447ac6c8c Fix encoding of predicate bits on ARM BX_pred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:21:31 +00:00
Jim Grosbach
fff76ee7ef Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 20:10:10 +00:00
Jim Grosbach
619e0d6d95 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135066 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:24:09 +00:00
Jim Grosbach
21101d60ce Add tests for ARM parsing of 'BKPT' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:17:36 +00:00
Jim Grosbach
37ee464ea9 Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:57:17 +00:00
Jim Grosbach
e8606dc7c8 Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 17:50:29 +00:00
Jim Grosbach
589130fac1 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:48:36 +00:00
Jim Grosbach
e36e21e830 Move Thumb tail call pseudos to Thumb.td file.
Fix a FIXME.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134727 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:13:35 +00:00
Jim Grosbach
245f5e8e2a Use ARMPseudoExpand for ARM tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 18:50:22 +00:00
Jim Grosbach
9ca2a778b6 Shuffle productions around a bit.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 18:26:27 +00:00
Jim Grosbach
4559a7bcfd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134712 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 18:15:12 +00:00